diff options
Diffstat (limited to 'hw/ssi/aspeed_smc.c')
| -rw-r--r-- | hw/ssi/aspeed_smc.c | 53 |
1 files changed, 23 insertions, 30 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index d899be17fd..48305e1574 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -224,7 +224,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, AspeedSegments seg; int i; - for (i = 0; i < asc->max_peripherals; i++) { + for (i = 0; i < asc->cs_num_max; i++) { if (i == cs) { continue; } @@ -290,7 +290,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, */ if ((asc->segments == aspeed_2500_spi1_segments || asc->segments == aspeed_2500_spi2_segments) && - cs == asc->max_peripherals && + cs == asc->cs_num_max && seg.addr + seg.size != asc->segments[cs].addr + asc->segments[cs].size) { aspeed_smc_error("Tried to change CS%d end address to 0x%" @@ -327,7 +327,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, unsigned size) { - aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u" PRIx64, addr, size); + aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); return 0; } @@ -693,13 +693,13 @@ static void aspeed_smc_reset(DeviceState *d) } /* Unselect all peripherals */ - for (i = 0; i < s->num_cs; ++i) { + for (i = 0; i < asc->cs_num_max; ++i) { s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; qemu_set_irq(s->cs_lines[i], true); } /* setup the default segment register values and regions for all */ - for (i = 0; i < asc->max_peripherals; ++i) { + for (i = 0; i < asc->cs_num_max; ++i) { aspeed_smc_flash_set_segment_region(s, i, asc->segment_to_reg(s, &asc->segments[i])); } @@ -729,8 +729,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) || (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) || (addr >= R_SEG_ADDR0 && - addr < R_SEG_ADDR0 + asc->max_peripherals) || - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->max_peripherals)) { + addr < R_SEG_ADDR0 + asc->cs_num_max) || + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); @@ -1042,11 +1042,11 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, addr < s->r_timings + asc->nregs_timings) || addr == s->r_ce_ctrl) { s->regs[addr] = value; - } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { + } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { int cs = addr - s->r_ctrl0; aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); } else if (addr >= R_SEG_ADDR0 && - addr < R_SEG_ADDR0 + asc->max_peripherals) { + addr < R_SEG_ADDR0 + asc->cs_num_max) { int cs = addr - R_SEG_ADDR0; if (value != s->regs[R_SEG_ADDR0 + cs]) { @@ -1090,7 +1090,7 @@ static void aspeed_smc_instance_init(Object *obj) AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); int i; - for (i = 0; i < asc->max_peripherals; i++) { + for (i = 0; i < asc->cs_num_max; i++) { object_initialize_child(obj, "flash[*]", &s->flashes[i], TYPE_ASPEED_SMC_FLASH); } @@ -1127,21 +1127,15 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) s->r_timings = asc->r_timings; s->conf_enable_w0 = asc->conf_enable_w0; - /* Enforce some real HW limits */ - if (s->num_cs > asc->max_peripherals) { - aspeed_smc_error("num_cs cannot exceed: %d", asc->max_peripherals); - s->num_cs = asc->max_peripherals; - } - /* DMA irq. Keep it first for the initialization in the SoC */ sysbus_init_irq(sbd, &s->irq); - s->spi = ssi_create_bus(dev, "spi"); + s->spi = ssi_create_bus(dev, NULL); /* Setup cs_lines for peripherals */ - s->cs_lines = g_new0(qemu_irq, s->num_cs); + s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); - for (i = 0; i < s->num_cs; ++i) { + for (i = 0; i < asc->cs_num_max; ++i) { sysbus_init_irq(sbd, &s->cs_lines[i]); } @@ -1174,7 +1168,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) * module behind to handle the memory accesses. This depends on * the board configuration. */ - for (i = 0; i < asc->max_peripherals; ++i) { + for (i = 0; i < asc->cs_num_max; ++i) { AspeedSMCFlash *fl = &s->flashes[i]; if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s), @@ -1211,7 +1205,6 @@ static const VMStateDescription vmstate_aspeed_smc = { }; static Property aspeed_smc_properties[] = { - DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), @@ -1321,7 +1314,7 @@ static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 1; + asc->cs_num_max = 1; asc->segments = aspeed_2400_smc_segments; asc->flash_window_base = 0x10000000; asc->flash_window_size = 0x6000000; @@ -1366,7 +1359,7 @@ static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 5; + asc->cs_num_max = 5; asc->segments = aspeed_2400_fmc_segments; asc->segment_addr_mask = 0xffff0000; asc->resets = aspeed_2400_fmc_resets; @@ -1408,7 +1401,7 @@ static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data) asc->r_timings = R_SPI_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; - asc->max_peripherals = 1; + asc->cs_num_max = 1; asc->segments = aspeed_2400_spi1_segments; asc->flash_window_base = 0x30000000; asc->flash_window_size = 0x10000000; @@ -1449,7 +1442,7 @@ static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 3; + asc->cs_num_max = 3; asc->segments = aspeed_2500_fmc_segments; asc->segment_addr_mask = 0xffff0000; asc->resets = aspeed_2500_fmc_resets; @@ -1487,7 +1480,7 @@ static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 2; + asc->cs_num_max = 2; asc->segments = aspeed_2500_spi1_segments; asc->segment_addr_mask = 0xffff0000; asc->flash_window_base = 0x30000000; @@ -1522,7 +1515,7 @@ static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 2; + asc->cs_num_max = 2; asc->segments = aspeed_2500_spi2_segments; asc->segment_addr_mask = 0xffff0000; asc->flash_window_base = 0x38000000; @@ -1604,7 +1597,7 @@ static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 1; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 3; + asc->cs_num_max = 3; asc->segments = aspeed_2600_fmc_segments; asc->segment_addr_mask = 0x0ff00ff0; asc->resets = aspeed_2600_fmc_resets; @@ -1643,7 +1636,7 @@ static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 2; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 2; + asc->cs_num_max = 2; asc->segments = aspeed_2600_spi1_segments; asc->segment_addr_mask = 0x0ff00ff0; asc->flash_window_base = 0x30000000; @@ -1682,7 +1675,7 @@ static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data) asc->r_timings = R_TIMINGS; asc->nregs_timings = 3; asc->conf_enable_w0 = CONF_ENABLE_W0; - asc->max_peripherals = 3; + asc->cs_num_max = 3; asc->segments = aspeed_2600_spi2_segments; asc->segment_addr_mask = 0x0ff00ff0; asc->flash_window_base = 0x50000000; |