diff options
Diffstat (limited to 'hw/stellaris.c')
| -rw-r--r-- | hw/stellaris.c | 115 |
1 files changed, 46 insertions, 69 deletions
diff --git a/hw/stellaris.c b/hw/stellaris.c index 2bf1c235dc..ce62a98158 100644 --- a/hw/stellaris.c +++ b/hw/stellaris.c @@ -45,6 +45,7 @@ typedef const struct { typedef struct gptm_state { SysBusDevice busdev; + MemoryRegion iomem; uint32_t config; uint32_t mode[2]; uint32_t control; @@ -140,7 +141,8 @@ static void gptm_tick(void *opaque) gptm_update_irq(s); } -static uint32_t gptm_read(void *opaque, target_phys_addr_t offset) +static uint64_t gptm_read(void *opaque, target_phys_addr_t offset, + unsigned size) { gptm_state *s = (gptm_state *)opaque; @@ -188,7 +190,8 @@ static uint32_t gptm_read(void *opaque, target_phys_addr_t offset) } } -static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value) +static void gptm_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { gptm_state *s = (gptm_state *)opaque; uint32_t oldval; @@ -268,16 +271,10 @@ static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value) gptm_update_irq(s); } -static CPUReadMemoryFunc * const gptm_readfn[] = { - gptm_read, - gptm_read, - gptm_read -}; - -static CPUWriteMemoryFunc * const gptm_writefn[] = { - gptm_write, - gptm_write, - gptm_write +static const MemoryRegionOps gptm_ops = { + .read = gptm_read, + .write = gptm_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_stellaris_gptm = { @@ -305,16 +302,14 @@ static const VMStateDescription vmstate_stellaris_gptm = { static int stellaris_gptm_init(SysBusDevice *dev) { - int iomemtype; gptm_state *s = FROM_SYSBUS(gptm_state, dev); sysbus_init_irq(dev, &s->irq); qdev_init_gpio_out(&dev->qdev, &s->trigger, 1); - iomemtype = cpu_register_io_memory(gptm_readfn, - gptm_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &gptm_ops, s, + "gptm", 0x1000); + sysbus_init_mmio(dev, &s->iomem); s->opaque[0] = s->opaque[1] = s; s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]); @@ -327,6 +322,7 @@ static int stellaris_gptm_init(SysBusDevice *dev) /* System controller. */ typedef struct { + MemoryRegion iomem; uint32_t pborctl; uint32_t ldopctl; uint32_t int_status; @@ -414,7 +410,8 @@ static int ssys_board_class(const ssys_state *s) } } -static uint32_t ssys_read(void *opaque, target_phys_addr_t offset) +static uint64_t ssys_read(void *opaque, target_phys_addr_t offset, + unsigned size) { ssys_state *s = (ssys_state *)opaque; @@ -518,7 +515,8 @@ static void ssys_calculate_system_clock(ssys_state *s) } } -static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value) +static void ssys_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { ssys_state *s = (ssys_state *)opaque; @@ -602,16 +600,10 @@ static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value) ssys_update(s); } -static CPUReadMemoryFunc * const ssys_readfn[] = { - ssys_read, - ssys_read, - ssys_read -}; - -static CPUWriteMemoryFunc * const ssys_writefn[] = { - ssys_write, - ssys_write, - ssys_write +static const MemoryRegionOps ssys_ops = { + .read = ssys_read, + .write = ssys_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ssys_reset(void *opaque) @@ -667,7 +659,6 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, stellaris_board_info * board, uint8_t *macaddr) { - int iomemtype; ssys_state *s; s = (ssys_state *)g_malloc0(sizeof(ssys_state)); @@ -677,10 +668,8 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq, s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); - iomemtype = cpu_register_io_memory(ssys_readfn, - ssys_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00001000, iomemtype); + memory_region_init_io(&s->iomem, &ssys_ops, s, "ssys", 0x00001000); + memory_region_add_subregion(get_system_memory(), base, &s->iomem); ssys_reset(s); vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); return 0; @@ -693,6 +682,7 @@ typedef struct { SysBusDevice busdev; i2c_bus *bus; qemu_irq irq; + MemoryRegion iomem; uint32_t msa; uint32_t mcs; uint32_t mdr; @@ -710,7 +700,8 @@ typedef struct { #define STELLARIS_I2C_MCS_IDLE 0x20 #define STELLARIS_I2C_MCS_BUSBSY 0x40 -static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset) +static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset, + unsigned size) { stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; @@ -747,7 +738,7 @@ static void stellaris_i2c_update(stellaris_i2c_state *s) } static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; @@ -838,16 +829,10 @@ static void stellaris_i2c_reset(stellaris_i2c_state *s) stellaris_i2c_update(s); } -static CPUReadMemoryFunc * const stellaris_i2c_readfn[] = { - stellaris_i2c_read, - stellaris_i2c_read, - stellaris_i2c_read -}; - -static CPUWriteMemoryFunc * const stellaris_i2c_writefn[] = { - stellaris_i2c_write, - stellaris_i2c_write, - stellaris_i2c_write +static const MemoryRegionOps stellaris_i2c_ops = { + .read = stellaris_i2c_read, + .write = stellaris_i2c_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_stellaris_i2c = { @@ -871,16 +856,14 @@ static int stellaris_i2c_init(SysBusDevice * dev) { stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev); i2c_bus *bus; - int iomemtype; sysbus_init_irq(dev, &s->irq); bus = i2c_init_bus(&dev->qdev, "i2c"); s->bus = bus; - iomemtype = cpu_register_io_memory(stellaris_i2c_readfn, - stellaris_i2c_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &stellaris_i2c_ops, s, + "i2c", 0x1000); + sysbus_init_mmio(dev, &s->iomem); /* ??? For now we only implement the master interface. */ stellaris_i2c_reset(s); vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s); @@ -904,6 +887,7 @@ static int stellaris_i2c_init(SysBusDevice * dev) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; uint32_t actss; uint32_t ris; uint32_t im; @@ -1004,7 +988,8 @@ static void stellaris_adc_reset(stellaris_adc_state *s) } } -static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset) +static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset, + unsigned size) { stellaris_adc_state *s = (stellaris_adc_state *)opaque; @@ -1052,7 +1037,7 @@ static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset) } static void stellaris_adc_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { stellaris_adc_state *s = (stellaris_adc_state *)opaque; @@ -1066,7 +1051,7 @@ static void stellaris_adc_write(void *opaque, target_phys_addr_t offset, return; case 0x04: /* SSCTL */ if (value != 6) { - hw_error("ADC: Unimplemented sequence %x\n", + hw_error("ADC: Unimplemented sequence %" PRIx64 "\n", value); } s->ssctl[n] = value; @@ -1109,16 +1094,10 @@ static void stellaris_adc_write(void *opaque, target_phys_addr_t offset, stellaris_adc_update(s); } -static CPUReadMemoryFunc * const stellaris_adc_readfn[] = { - stellaris_adc_read, - stellaris_adc_read, - stellaris_adc_read -}; - -static CPUWriteMemoryFunc * const stellaris_adc_writefn[] = { - stellaris_adc_write, - stellaris_adc_write, - stellaris_adc_write +static const MemoryRegionOps stellaris_adc_ops = { + .read = stellaris_adc_read, + .write = stellaris_adc_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_stellaris_adc = { @@ -1159,17 +1138,15 @@ static const VMStateDescription vmstate_stellaris_adc = { static int stellaris_adc_init(SysBusDevice *dev) { stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev); - int iomemtype; int n; for (n = 0; n < 4; n++) { sysbus_init_irq(dev, &s->irq[n]); } - iomemtype = cpu_register_io_memory(stellaris_adc_readfn, - stellaris_adc_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &stellaris_adc_ops, s, + "adc", 0x1000); + sysbus_init_mmio(dev, &s->iomem); stellaris_adc_reset(s); qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1); vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s); |