diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i386/acpi-common.c | 10 | ||||
| -rw-r--r-- | hw/i386/microvm.c | 82 | ||||
| -rw-r--r-- | hw/i386/x86.c | 35 |
3 files changed, 102 insertions, 25 deletions
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c index 8a76965406..a6a30e8363 100644 --- a/hw/i386/acpi-common.c +++ b/hw/i386/acpi-common.c @@ -103,6 +103,16 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker, io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); io_apic->interrupt = cpu_to_le32(0); + if (x86ms->ioapic2) { + AcpiMadtIoApic *io_apic2; + io_apic2 = acpi_data_push(table_data, sizeof *io_apic); + io_apic2->type = ACPI_APIC_IO; + io_apic2->length = sizeof(*io_apic); + io_apic2->io_apic_id = ACPI_BUILD_IOAPIC_ID + 1; + io_apic2->address = cpu_to_le32(IO_APIC_SECONDARY_ADDRESS); + io_apic2->interrupt = cpu_to_le32(IO_APIC_SECONDARY_IRQBASE); + } + if (x86ms->apic_xrupt_override) { intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 5428448b70..5688608613 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -96,13 +96,6 @@ static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s) rtc_set_memory(s, 0x5d, val >> 16); } -static void microvm_gsi_handler(void *opaque, int n, int level) -{ - GSIState *s = opaque; - - qemu_set_irq(s->ioapic_irq[n], level); -} - static void create_gpex(MicrovmMachineState *mms) { X86MachineState *x86ms = X86_MACHINE(mms); @@ -152,34 +145,56 @@ static void create_gpex(MicrovmMachineState *mms) } } +static int microvm_ioapics(MicrovmMachineState *mms) +{ + if (!x86_machine_is_acpi_enabled(X86_MACHINE(mms))) { + return 1; + } + if (mms->ioapic2 == ON_OFF_AUTO_OFF) { + return 1; + } + return 2; +} + static void microvm_devices_init(MicrovmMachineState *mms) { X86MachineState *x86ms = X86_MACHINE(mms); ISABus *isa_bus; ISADevice *rtc_state; GSIState *gsi_state; + int ioapics; int i; /* Core components */ - + ioapics = microvm_ioapics(mms); gsi_state = g_malloc0(sizeof(*gsi_state)); - if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) { - x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); - } else { - x86ms->gsi = qemu_allocate_irqs(microvm_gsi_handler, - gsi_state, GSI_NUM_PINS); - } + x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, + IOAPIC_NUM_PINS * ioapics); isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(), &error_abort); isa_bus_irqs(isa_bus, x86ms->gsi); ioapic_init_gsi(gsi_state, "machine"); + if (ioapics > 1) { + x86ms->ioapic2 = ioapic_init_secondary(gsi_state); + } kvmclock_create(true); - mms->virtio_irq_base = x86_machine_is_acpi_enabled(x86ms) ? 16 : 5; - for (i = 0; i < VIRTIO_NUM_TRANSPORTS; i++) { + mms->virtio_irq_base = 5; + mms->virtio_num_transports = 8; + if (x86ms->ioapic2) { + mms->pcie_irq_base = 16; /* 16 -> 19 */ + /* use second ioapic (24 -> 47) for virtio-mmio irq lines */ + mms->virtio_irq_base = IO_APIC_SECONDARY_IRQBASE; + mms->virtio_num_transports = IOAPIC_NUM_PINS; + } else if (x86_machine_is_acpi_enabled(x86ms)) { + mms->pcie_irq_base = 12; /* 12 -> 15 */ + mms->virtio_irq_base = 16; /* 16 -> 23 */ + } + + for (i = 0; i < mms->virtio_num_transports; i++) { sysbus_create_simple("virtio-mmio", VIRTIO_MMIO_BASE + i * 512, x86ms->gsi[mms->virtio_irq_base + i]); @@ -221,12 +236,12 @@ static void microvm_devices_init(MicrovmMachineState *mms) mms->gpex.mmio32.size = PCIE_MMIO_SIZE; mms->gpex.ecam.base = PCIE_ECAM_BASE; mms->gpex.ecam.size = PCIE_ECAM_SIZE; - mms->gpex.irq = PCIE_IRQ_BASE; + mms->gpex.irq = mms->pcie_irq_base; create_gpex(mms); - x86ms->pci_irq_mask = ((1 << (PCIE_IRQ_BASE + 0)) | - (1 << (PCIE_IRQ_BASE + 1)) | - (1 << (PCIE_IRQ_BASE + 2)) | - (1 << (PCIE_IRQ_BASE + 3))); + x86ms->pci_irq_mask = ((1 << (mms->pcie_irq_base + 0)) | + (1 << (mms->pcie_irq_base + 1)) | + (1 << (mms->pcie_irq_base + 2)) | + (1 << (mms->pcie_irq_base + 3))); } else { x86ms->pci_irq_mask = 0; } @@ -550,6 +565,23 @@ static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name, visit_type_OnOffAuto(v, name, &mms->pcie, errp); } +static void microvm_machine_get_ioapic2(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + OnOffAuto ioapic2 = mms->ioapic2; + + visit_type_OnOffAuto(v, name, &ioapic2, errp); +} + +static void microvm_machine_set_ioapic2(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &mms->ioapic2, errp); +} + static bool microvm_machine_get_isa_serial(Object *obj, Error **errp) { MicrovmMachineState *mms = MICROVM_MACHINE(obj); @@ -626,6 +658,7 @@ static void microvm_machine_initfn(Object *obj) mms->pit = ON_OFF_AUTO_AUTO; mms->rtc = ON_OFF_AUTO_AUTO; mms->pcie = ON_OFF_AUTO_AUTO; + mms->ioapic2 = ON_OFF_AUTO_AUTO; mms->isa_serial = true; mms->option_roms = true; mms->auto_kernel_cmdline = true; @@ -699,6 +732,13 @@ static void microvm_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, MICROVM_MACHINE_PCIE, "Enable PCIe"); + object_class_property_add(oc, MICROVM_MACHINE_IOAPIC2, "OnOffAuto", + microvm_machine_get_ioapic2, + microvm_machine_set_ioapic2, + NULL, NULL); + object_class_property_set_description(oc, MICROVM_MACHINE_IOAPIC2, + "Enable second IO-APIC"); + object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL, microvm_machine_get_isa_serial, microvm_machine_set_isa_serial); diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5944fc44ed..d68a9eaefc 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -588,11 +588,21 @@ void gsi_handler(void *opaque, int n, int level) GSIState *s = opaque; trace_x86_gsi_interrupt(n, level); - if (n < ISA_NUM_IRQS) { - /* Under KVM, Kernel will forward to both PIC and IOAPIC */ - qemu_set_irq(s->i8259_irq[n], level); + switch (n) { + case 0 ... ISA_NUM_IRQS - 1: + if (s->i8259_irq[n]) { + /* Under KVM, Kernel will forward to both PIC and IOAPIC */ + qemu_set_irq(s->i8259_irq[n], level); + } + /* fall through */ + case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: + qemu_set_irq(s->ioapic_irq[n], level); + break; + case IO_APIC_SECONDARY_IRQBASE + ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: + qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); + break; } - qemu_set_irq(s->ioapic_irq[n], level); } void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) @@ -618,6 +628,23 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) } } +DeviceState *ioapic_init_secondary(GSIState *gsi_state) +{ + DeviceState *dev; + SysBusDevice *d; + unsigned int i; + + dev = qdev_new(TYPE_IOAPIC); + d = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); + + for (i = 0; i < IOAPIC_NUM_PINS; i++) { + gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); + } + return dev; +} + struct setup_data { uint64_t next; uint32_t type; |