diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/pxa2xx.c | 36 | ||||
| -rw-r--r-- | hw/arm/pxa2xx_pic.c | 11 | ||||
| -rw-r--r-- | hw/intc/arm_gic.c | 2 |
3 files changed, 18 insertions, 31 deletions
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 66bc0dccc9..45a99c819d 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -224,27 +224,24 @@ static const VMStateDescription vmstate_pxa2xx_cm = { } }; -static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t *value) +static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) { PXA2xxState *s = (PXA2xxState *)ri->opaque; - *value = s->clkcfg; - return 0; + return s->clkcfg; } -static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { PXA2xxState *s = (PXA2xxState *)ri->opaque; s->clkcfg = value & 0xf; if (value & 2) { printf("%s: CPU frequency change attempt\n", __func__); } - return 0; } -static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { PXA2xxState *s = (PXA2xxState *)ri->opaque; static const char *pwrmode[8] = { @@ -310,36 +307,29 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, printf("%s: machine entered %s mode\n", __func__, pwrmode[value & 7]); } - - return 0; } -static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t *value) +static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) { PXA2xxState *s = (PXA2xxState *)ri->opaque; - *value = s->pmnc; - return 0; + return s->pmnc; } -static int pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { PXA2xxState *s = (PXA2xxState *)ri->opaque; s->pmnc = value; - return 0; } -static int pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t *value) +static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) { PXA2xxState *s = (PXA2xxState *)ri->opaque; if (s->pmnc & 1) { - *value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); } else { - *value = 0; + return 0; } - return 0; } static const ARMCPRegInfo pxa_cp_reginfo[] = { diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 46d337cf84..345fa4a491 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -217,20 +217,17 @@ static const int pxa2xx_cp_reg_map[0x10] = { [0xa] = ICPR2, }; -static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t *value) +static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri) { int offset = pxa2xx_cp_reg_map[ri->crn]; - *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4); - return 0; + return pxa2xx_pic_mem_read(ri->opaque, offset, 4); } -static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { int offset = pxa2xx_cp_reg_map[ri->crn]; pxa2xx_pic_mem_write(ri->opaque, offset, value, 4); - return 0; } #define REGINFO_FOR_PIC_CP(NAME, CRN) \ diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 93eaa6b2fa..955b8d4945 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -189,7 +189,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) } s->last_active[irq][cpu] = s->running_irq[cpu]; - if (s->revision == REV_11MPCORE) { + if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { /* Clear pending flags for both level and edge triggered interrupts. * Level triggered IRQs will be reasserted once they become inactive. */ |