diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/char/riscv_htif.c | 33 | ||||
| -rw-r--r-- | hw/intc/sifive_plic.c | 20 | ||||
| -rw-r--r-- | hw/riscv/boot.c | 16 | ||||
| -rw-r--r-- | hw/riscv/opentitan.c | 2 | ||||
| -rw-r--r-- | hw/riscv/spike.c | 45 | ||||
| -rw-r--r-- | hw/riscv/virt.c | 83 | ||||
| -rw-r--r-- | hw/timer/ibex_timer.c | 25 |
7 files changed, 153 insertions, 71 deletions
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index ddae738d56..729edbf968 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = { .write = htif_mm_write, }; +bool htif_uses_elf_symbols(void) +{ + return (address_symbol_set == 3) ? true : false; +} + HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, - CPURISCVState *env, Chardev *chr) + CPURISCVState *env, Chardev *chr, uint64_t nonelf_base) { - uint64_t base = MIN(tohost_addr, fromhost_addr); - uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base; - uint64_t tohost_offset = tohost_addr - base; - uint64_t fromhost_offset = fromhost_addr - base; + uint64_t base, size, tohost_offset, fromhost_offset; + + if (!htif_uses_elf_symbols()) { + fromhost_addr = nonelf_base; + tohost_addr = nonelf_base + 8; + } + + base = MIN(tohost_addr, fromhost_addr); + size = MAX(tohost_addr + 8, fromhost_addr + 8) - base; + tohost_offset = tohost_addr - base; + fromhost_offset = fromhost_addr - base; HTIFState *s = g_malloc0(sizeof(HTIFState)); s->address_space = address_space; @@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, qemu_chr_fe_init(&s->chr, chr, &error_abort); qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event, htif_be_change, s, NULL, true); - if (address_symbol_set == 3) { - memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s, - TYPE_HTIF_UART, size); - memory_region_add_subregion_overlap(address_space, base, - &s->mmio, 1); - } + + memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s, + TYPE_HTIF_UART, size); + memory_region_add_subregion_overlap(address_space, base, + &s->mmio, 1); return s; } diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 746c0f0343..eebbcf33d4 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -30,6 +30,7 @@ #include "target/riscv/cpu.h" #include "migration/vmstate.h" #include "hw/irq.h" +#include "sysemu/kvm.h" static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) { @@ -430,7 +431,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t context_stride, uint32_t aperture_size) { DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC); - int i; + int i, j = 0; + SiFivePLICState *plic; assert(enable_stride == (enable_stride & -enable_stride)); assert(context_stride == (context_stride & -context_stride)); @@ -448,13 +450,21 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + plic = SIFIVE_PLIC(dev); for (i = 0; i < num_harts; i++) { CPUState *cpu = qemu_get_cpu(hartid_base + i); - qdev_connect_gpio_out(dev, i, - qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); - qdev_connect_gpio_out(dev, num_harts + i, - qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); + if (plic->addr_config[j].mode == PLICMode_M) { + j++; + qdev_connect_gpio_out(dev, num_harts + i, + qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); + } + + if (plic->addr_config[j].mode == PLICMode_S) { + j++; + qdev_connect_gpio_out(dev, i, + qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); + } } return dev; diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index f67264374e..cae74fcbcd 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -30,6 +30,7 @@ #include "elf.h" #include "sysemu/device_tree.h" #include "sysemu/qtest.h" +#include "sysemu/kvm.h" #include <libfdt.h> @@ -51,7 +52,9 @@ char *riscv_plic_hart_config_string(int hart_count) CPUState *cs = qemu_get_cpu(i); CPURISCVState *env = &RISCV_CPU(cs)->env; - if (riscv_has_ext(env, RVS)) { + if (kvm_enabled()) { + vals[i] = "S"; + } else if (riscv_has_ext(env, RVS)) { vals[i] = "MS"; } else { vals[i] = "M"; @@ -324,3 +327,14 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts return; } + +void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) +{ + CPUState *cs; + + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { + RISCVCPU *riscv_cpu = RISCV_CPU(cs); + riscv_cpu->env.kernel_addr = kernel_addr; + riscv_cpu->env.fdt_addr = fdt_addr; + } +} diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 0856c347e8..aec7cfa33f 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -160,7 +160,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00); qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); - qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18); + qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 288d69cd9f..d059a67f9b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -42,6 +42,7 @@ static const MemMapEntry spike_memmap[] = { [SPIKE_MROM] = { 0x1000, 0xf000 }, + [SPIKE_HTIF] = { 0x1000000, 0x1000 }, [SPIKE_CLINT] = { 0x2000000, 0x10000 }, [SPIKE_DRAM] = { 0x80000000, 0x0 }, }; @@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(fdt, "/htif"); qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); + if (!htif_uses_elf_symbols()) { + qemu_fdt_setprop_cells(fdt, "/htif", "reg", + 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); + } qemu_fdt_add_subnode(fdt, "/soc"); qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); @@ -172,6 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, if (cmdline) { qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); } } @@ -241,10 +247,6 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, machine->ram); - /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); - /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", memmap[SPIKE_MROM].size, &error_fatal); @@ -258,14 +260,15 @@ static void spike_board_init(MachineState *machine) */ if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base, + RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, htif_symbol_callback); } else { firmware_end_addr = riscv_find_and_load_firmware(machine, - RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base, + RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, htif_symbol_callback); } + /* Load kernel */ if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); @@ -273,17 +276,6 @@ static void spike_board_init(MachineState *machine) kernel_entry = riscv_load_kernel(machine->kernel_filename, kernel_start_addr, htif_symbol_callback); - - if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", - end); - } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode @@ -292,6 +284,22 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } + /* Create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(&s->soc[0])); + + /* Load initrd */ + if (machine->kernel_filename && machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + end); + } + /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, machine->ram_size, s->fdt); @@ -303,7 +311,8 @@ static void spike_board_init(MachineState *machine) /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, - &s->soc[0].harts[0].env, serial_hd(0)); + &s->soc[0].harts[0].env, serial_hd(0), + memmap[SPIKE_HTIF].base); } static void spike_machine_instance_init(Object *obj) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 3af074148e..2643c8bc37 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -38,6 +38,7 @@ #include "chardev/char.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" @@ -372,13 +373,22 @@ static void create_fdt_socket_plic(RISCVVirtState *s, "sifive,plic-1.0.0", "riscv,plic0" }; - plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); + if (kvm_enabled()) { + plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); + } else { + plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); + } for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { - plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); - plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); - plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); - plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + if (kvm_enabled()) { + plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); + plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); + } else { + plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); + plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); + plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); + plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + } } plic_phandles[socket] = (*phandle)++; @@ -436,10 +446,12 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, create_fdt_socket_memory(s, memmap, socket); - if (s->have_aclint) { - create_fdt_socket_aclint(s, memmap, socket, intc_phandles); - } else { - create_fdt_socket_clint(s, memmap, socket, intc_phandles); + if (!kvm_enabled()) { + if (s->have_aclint) { + create_fdt_socket_aclint(s, memmap, socket, intc_phandles); + } else { + create_fdt_socket_clint(s, memmap, socket, intc_phandles); + } } create_fdt_socket_plic(s, memmap, socket, phandle, @@ -801,23 +813,25 @@ static void virt_machine_init(MachineState *machine) hart_count, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); - /* Per-socket CLINT */ - riscv_aclint_swi_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, - base_hartid, hart_count, false); - riscv_aclint_mtimer_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size + - RISCV_ACLINT_SWI_SIZE, - RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, - RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); - - /* Per-socket ACLINT SSWI */ - if (s->have_aclint) { + if (!kvm_enabled()) { + /* Per-socket CLINT */ riscv_aclint_swi_create( - memmap[VIRT_ACLINT_SSWI].base + - i * memmap[VIRT_ACLINT_SSWI].size, - base_hartid, hart_count, true); + memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, + base_hartid, hart_count, false); + riscv_aclint_mtimer_create( + memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size + + RISCV_ACLINT_SWI_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, + RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + + /* Per-socket ACLINT SSWI */ + if (s->have_aclint) { + riscv_aclint_swi_create( + memmap[VIRT_ACLINT_SSWI].base + + i * memmap[VIRT_ACLINT_SSWI].size, + base_hartid, hart_count, true); + } } /* Per-socket PLIC hart topology configuration string */ @@ -884,6 +898,16 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); + /* + * Only direct boot kernel is currently supported for KVM VM, + * so the "-bios" parameter is ignored and treated like "-bios none" + * when KVM is enabled. + */ + if (kvm_enabled()) { + g_free(machine->firmware); + machine->firmware = g_strdup("none"); + } + if (riscv_is_32bit(&s->soc[0])) { firmware_end_addr = riscv_find_and_load_firmware(machine, RISCV32_BIOS_BIN, start_addr, NULL); @@ -941,6 +965,15 @@ static void virt_machine_init(MachineState *machine) virt_memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr, machine->fdt); + /* + * Only direct boot kernel is currently supported for KVM VM, + * So here setup kernel start address and fdt address. + * TODO:Support firmware loading and integrate to TCG start + */ + if (kvm_enabled()) { + riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); + } + /* SiFive Test MMIO device */ sifive_test_create(memmap[VIRT_TEST].base); diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 66e1f8e48c..8c2ca364da 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -34,7 +34,9 @@ #include "target/riscv/cpu.h" #include "migration/vmstate.h" -REG32(CTRL, 0x00) +REG32(ALERT_TEST, 0x00) + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1) +REG32(CTRL, 0x04) FIELD(CTRL, ACTIVE, 0, 1) REG32(CFG0, 0x100) FIELD(CFG0, PRESCALE, 0, 12) @@ -130,7 +132,6 @@ static void ibex_timer_reset(DeviceState *dev) s->timer_compare_upper0 = 0xFFFFFFFF; s->timer_intr_enable = 0x00000000; s->timer_intr_state = 0x00000000; - s->timer_intr_test = 0x00000000; ibex_timer_update_irqs(s); } @@ -143,6 +144,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr, uint64_t retvalue = 0; switch (addr >> 2) { + case R_ALERT_TEST: + qemu_log_mask(LOG_GUEST_ERROR, + "Attempted to read ALERT_TEST, a write only register"); + break; case R_CTRL: retvalue = s->timer_ctrl; break; @@ -168,7 +173,8 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr, retvalue = s->timer_intr_state; break; case R_INTR_TEST: - retvalue = s->timer_intr_test; + qemu_log_mask(LOG_GUEST_ERROR, + "Attempted to read INTR_TEST, a write only register"); break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr, uint32_t val = val64; switch (addr >> 2) { + case R_ALERT_TEST: + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); + break; case R_CTRL: s->timer_ctrl = val; break; @@ -215,10 +224,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr, s->timer_intr_state &= ~val; break; case R_INTR_TEST: - s->timer_intr_test = val; - if (s->timer_intr_enable & - s->timer_intr_test & - R_INTR_ENABLE_IE_0_MASK) { + if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) { s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; qemu_set_irq(s->irq, true); } @@ -247,8 +253,8 @@ static int ibex_timer_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_ibex_timer = { .name = TYPE_IBEX_TIMER, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .post_load = ibex_timer_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(timer_ctrl, IbexTimerState), @@ -257,7 +263,6 @@ static const VMStateDescription vmstate_ibex_timer = { VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), VMSTATE_UINT32(timer_intr_enable, IbexTimerState), VMSTATE_UINT32(timer_intr_state, IbexTimerState), - VMSTATE_UINT32(timer_intr_test, IbexTimerState), VMSTATE_END_OF_LIST() } }; |