diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/aspeed.c | 2 | ||||
| -rw-r--r-- | hw/arm/mps2-tz.c | 2 | ||||
| -rw-r--r-- | hw/intc/arm_gic.c | 4 | ||||
| -rw-r--r-- | hw/intc/arm_gicv3_redist.c | 2 | ||||
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 2 | ||||
| -rw-r--r-- | hw/misc/allwinner-r40-dramc.c | 2 | ||||
| -rw-r--r-- | hw/misc/exynos4210_rng.c | 2 |
7 files changed, 8 insertions, 8 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6880998484..263626abea 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1565,7 +1565,7 @@ static void ast1030_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = &bmc->soc; - /* U10 24C08 connects to SDA/SCL Groupt 1 by default */ + /* U10 24C08 connects to SDA/SCL Group 1 by default */ uint8_t *eeprom_buf = g_malloc0(32 * 1024); smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 07aecd9497..5873107302 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -1205,7 +1205,7 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, { /* * The MPS2 TZ FPGA images have IDAUs in them which are connected to - * the Master Security Controllers. Thes have the same logic as + * the Master Security Controllers. These have the same logic as * is used by the IoTKit for the IDAU connected to the CPU, except * that MSCs don't care about the NSC attribute. */ diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 7a34bc0998..074cf50af2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -239,7 +239,7 @@ static inline bool gic_lr_entry_is_free(uint32_t entry) } /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the - * corrsponding bit in EISR is set. + * corresponding bit in EISR is set. */ static inline bool gic_lr_entry_is_eoi(uint32_t entry) { @@ -1333,7 +1333,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, /* ??? This currently clears the pending bit for all CPUs, even for per-CPU interrupts. It's unclear whether this is the - corect behavior. */ + correct behavior. */ if (value & (1 << i)) { GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 297f7f0263..8153525849 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -494,7 +494,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, /* Only the ProcessorSleep bit is writable. When the guest sets * it, it requests that we transition the channel between the * redistributor and the cpu interface to quiescent, and that - * we set the ChildrenAsleep bit once the inteface has reached the + * we set the ChildrenAsleep bit once the interface has reached the * quiescent state. * Setting the ProcessorSleep to 0 reverses the quiescing, and * ChildrenAsleep is cleared once the transition is complete. diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63afe1fdf5..03b6b8c986 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -894,7 +894,7 @@ int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) vec->active = 0; if (vec->level) { /* Re-pend the exception if it's still held high; only - * happens for extenal IRQs + * happens for external IRQs */ assert(irq >= NVIC_FIRST_IRQ); vec->pending = 1; diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c index ea6124744f..6944f84455 100644 --- a/hw/misc/allwinner-r40-dramc.c +++ b/hw/misc/allwinner-r40-dramc.c @@ -368,7 +368,7 @@ static const MemoryRegionOps allwinner_r40_detect_ops = { /* * mctl_r40_detect_rank_count in u-boot will write the high 1G of DDR - * to detect wether the board support dual_rank or not. Create a virtual memory + * to detect whether the board support dual_rank or not. Create a virtual memory * if the board's ram_size less or equal than 1G, and set read time out flag of * REG_DRAMCTL_PGSR when the user touch this high dram. */ diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c index 1b9e8347a1..9214ec14cc 100644 --- a/hw/misc/exynos4210_rng.c +++ b/hw/misc/exynos4210_rng.c @@ -1,5 +1,5 @@ /* - * Exynos4210 Pseudo Random Nubmer Generator Emulation + * Exynos4210 Pseudo Random Number Generator Emulation * * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> * |