diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/9pfs/xen-9pfs.h | 4 | ||||
| -rw-r--r-- | hw/block/dataplane/xen-block.c | 44 | ||||
| -rw-r--r-- | hw/block/dataplane/xen-block.h | 3 | ||||
| -rw-r--r-- | hw/block/nvme.c | 1 | ||||
| -rw-r--r-- | hw/block/xen-block.c | 38 | ||||
| -rw-r--r-- | hw/block/xen_blkif.h | 5 | ||||
| -rw-r--r-- | hw/char/xen_console.c | 2 | ||||
| -rw-r--r-- | hw/display/Kconfig | 2 | ||||
| -rw-r--r-- | hw/display/ati.c | 99 | ||||
| -rw-r--r-- | hw/display/ati_2d.c | 26 | ||||
| -rw-r--r-- | hw/display/ati_dbg.c | 2 | ||||
| -rw-r--r-- | hw/display/ati_int.h | 6 | ||||
| -rw-r--r-- | hw/display/ati_regs.h | 6 | ||||
| -rw-r--r-- | hw/display/xenfb.c | 7 | ||||
| -rw-r--r-- | hw/dma/rc4030.c | 21 | ||||
| -rw-r--r-- | hw/i2c/bitbang_i2c.c | 2 | ||||
| -rw-r--r-- | hw/i2c/bitbang_i2c.h | 12 | ||||
| -rw-r--r-- | hw/i2c/ppc4xx_i2c.c | 1 | ||||
| -rw-r--r-- | hw/i2c/versatile_i2c.c | 2 | ||||
| -rw-r--r-- | hw/i386/xen/xen-hvm.c | 16 | ||||
| -rw-r--r-- | hw/i386/xen/xen-mapcache.c | 2 | ||||
| -rw-r--r-- | hw/mips/gt64xxx_pci.c | 494 | ||||
| -rw-r--r-- | hw/mips/trace-events | 4 | ||||
| -rw-r--r-- | hw/net/xen_nic.c | 2 | ||||
| -rw-r--r-- | hw/usb/xen-usb.c | 3 | ||||
| -rw-r--r-- | hw/xen/xen-bus.c | 92 | ||||
| -rw-r--r-- | hw/xen/xen-legacy-backend.c | 2 |
27 files changed, 524 insertions, 374 deletions
diff --git a/hw/9pfs/xen-9pfs.h b/hw/9pfs/xen-9pfs.h index fbdee3d843..241e2216a4 100644 --- a/hw/9pfs/xen-9pfs.h +++ b/hw/9pfs/xen-9pfs.h @@ -13,8 +13,8 @@ #ifndef HW_9PFS_XEN_9PFS_H #define HW_9PFS_XEN_9PFS_H -#include <xen/io/protocols.h> -#include "hw/xen/io/ring.h" +#include "hw/xen/interface/io/protocols.h" +#include "hw/xen/interface/io/ring.h" /* * Do not merge into xen-9p-backend.c: clang doesn't allow unused static diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c index f7ad452bbd..0f200c5fb0 100644 --- a/hw/block/dataplane/xen-block.c +++ b/hw/block/dataplane/xen-block.c @@ -58,6 +58,7 @@ struct XenBlockDataPlane { int requests_inflight; unsigned int max_requests; BlockBackend *blk; + unsigned int sector_size; QEMUBH *bh; IOThread *iothread; AioContext *ctx; @@ -167,7 +168,7 @@ static int xen_block_parse_request(XenBlockRequest *request) goto err; } - request->start = request->req.sector_number * XEN_BLKIF_SECTOR_SIZE; + request->start = request->req.sector_number * dataplane->sector_size; for (i = 0; i < request->req.nr_segments; i++) { if (i == BLKIF_MAX_SEGMENTS_PER_REQUEST) { error_report("error: nr_segments too big"); @@ -177,14 +178,14 @@ static int xen_block_parse_request(XenBlockRequest *request) error_report("error: first > last sector"); goto err; } - if (request->req.seg[i].last_sect * XEN_BLKIF_SECTOR_SIZE >= + if (request->req.seg[i].last_sect * dataplane->sector_size >= XC_PAGE_SIZE) { error_report("error: page crossing"); goto err; } len = (request->req.seg[i].last_sect - - request->req.seg[i].first_sect + 1) * XEN_BLKIF_SECTOR_SIZE; + request->req.seg[i].first_sect + 1) * dataplane->sector_size; request->size += len; } if (request->start + request->size > blk_getlength(dataplane->blk)) { @@ -218,17 +219,17 @@ static int xen_block_copy_request(XenBlockRequest *request) if (to_domain) { segs[i].dest.foreign.ref = request->req.seg[i].gref; segs[i].dest.foreign.offset = request->req.seg[i].first_sect * - XEN_BLKIF_SECTOR_SIZE; + dataplane->sector_size; segs[i].source.virt = virt; } else { segs[i].source.foreign.ref = request->req.seg[i].gref; segs[i].source.foreign.offset = request->req.seg[i].first_sect * - XEN_BLKIF_SECTOR_SIZE; + dataplane->sector_size; segs[i].dest.virt = virt; } segs[i].len = (request->req.seg[i].last_sect - request->req.seg[i].first_sect + 1) * - XEN_BLKIF_SECTOR_SIZE; + dataplane->sector_size; virt += segs[i].len; } @@ -317,7 +318,9 @@ static void xen_block_complete_aio(void *opaque, int ret) } xen_block_release_request(request); - qemu_bh_schedule(dataplane->bh); + if (dataplane->more_work) { + qemu_bh_schedule(dataplane->bh); + } done: aio_context_release(dataplane->ctx); @@ -336,12 +339,12 @@ static bool xen_block_split_discard(XenBlockRequest *request, /* Wrap around, or overflowing byte limit? */ if (sec_start + sec_count < sec_count || - sec_start + sec_count > INT64_MAX / XEN_BLKIF_SECTOR_SIZE) { + sec_start + sec_count > INT64_MAX / dataplane->sector_size) { return false; } - byte_offset = sec_start * XEN_BLKIF_SECTOR_SIZE; - byte_remaining = sec_count * XEN_BLKIF_SECTOR_SIZE; + byte_offset = sec_start * dataplane->sector_size; + byte_remaining = sec_count * dataplane->sector_size; do { byte_chunk = byte_remaining > BDRV_REQUEST_MAX_BYTES ? @@ -514,12 +517,13 @@ static int xen_block_get_request(XenBlockDataPlane *dataplane, */ #define IO_PLUG_THRESHOLD 1 -static void xen_block_handle_requests(XenBlockDataPlane *dataplane) +static bool xen_block_handle_requests(XenBlockDataPlane *dataplane) { RING_IDX rc, rp; XenBlockRequest *request; int inflight_atstart = dataplane->requests_inflight; int batched = 0; + bool done_something = false; dataplane->more_work = 0; @@ -551,6 +555,7 @@ static void xen_block_handle_requests(XenBlockDataPlane *dataplane) } xen_block_get_request(dataplane, request, rc); dataplane->rings.common.req_cons = ++rc; + done_something = true; /* parse them */ if (xen_block_parse_request(request) != 0) { @@ -602,10 +607,7 @@ static void xen_block_handle_requests(XenBlockDataPlane *dataplane) blk_io_unplug(dataplane->blk); } - if (dataplane->more_work && - dataplane->requests_inflight < dataplane->max_requests) { - qemu_bh_schedule(dataplane->bh); - } + return done_something; } static void xen_block_dataplane_bh(void *opaque) @@ -617,21 +619,23 @@ static void xen_block_dataplane_bh(void *opaque) aio_context_release(dataplane->ctx); } -static void xen_block_dataplane_event(void *opaque) +static bool xen_block_dataplane_event(void *opaque) { XenBlockDataPlane *dataplane = opaque; - qemu_bh_schedule(dataplane->bh); + return xen_block_handle_requests(dataplane); } XenBlockDataPlane *xen_block_dataplane_create(XenDevice *xendev, - BlockConf *conf, + BlockBackend *blk, + unsigned int sector_size, IOThread *iothread) { XenBlockDataPlane *dataplane = g_new0(XenBlockDataPlane, 1); dataplane->xendev = xendev; - dataplane->blk = conf->blk; + dataplane->blk = blk; + dataplane->sector_size = sector_size; QLIST_INIT(&dataplane->inflight); QLIST_INIT(&dataplane->freelist); @@ -803,7 +807,7 @@ void xen_block_dataplane_start(XenBlockDataPlane *dataplane, } dataplane->event_channel = - xen_device_bind_event_channel(xendev, event_channel, + xen_device_bind_event_channel(xendev, dataplane->ctx, event_channel, xen_block_dataplane_event, dataplane, &local_err); if (local_err) { diff --git a/hw/block/dataplane/xen-block.h b/hw/block/dataplane/xen-block.h index d6fa6d26dd..76dcd51c3d 100644 --- a/hw/block/dataplane/xen-block.h +++ b/hw/block/dataplane/xen-block.h @@ -15,7 +15,8 @@ typedef struct XenBlockDataPlane XenBlockDataPlane; XenBlockDataPlane *xen_block_dataplane_create(XenDevice *xendev, - BlockConf *conf, + BlockBackend *blk, + unsigned int sector_size, IOThread *iothread); void xen_block_dataplane_destroy(XenBlockDataPlane *dataplane); void xen_block_dataplane_start(XenBlockDataPlane *dataplane, diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 107a719b95..36d6a8bb3a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1384,7 +1384,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) n->bar.cap = 0; NVME_CAP_SET_MQES(n->bar.cap, 0x7ff); NVME_CAP_SET_CQR(n->bar.cap, 1); - NVME_CAP_SET_AMS(n->bar.cap, 1); NVME_CAP_SET_TO(n->bar.cap, 0xf); NVME_CAP_SET_CSS(n->bar.cap, 1); NVME_CAP_SET_MPSMAX(n->bar.cap, 4); diff --git a/hw/block/xen-block.c b/hw/block/xen-block.c index 4de537aef4..8f224ef81d 100644 --- a/hw/block/xen-block.c +++ b/hw/block/xen-block.c @@ -52,11 +52,25 @@ static void xen_block_connect(XenDevice *xendev, Error **errp) XenBlockDevice *blockdev = XEN_BLOCK_DEVICE(xendev); const char *type = object_get_typename(OBJECT(blockdev)); XenBlockVdev *vdev = &blockdev->props.vdev; + BlockConf *conf = &blockdev->props.conf; + unsigned int feature_large_sector_size; unsigned int order, nr_ring_ref, *ring_ref, event_channel, protocol; char *str; trace_xen_block_connect(type, vdev->disk, vdev->partition); + if (xen_device_frontend_scanf(xendev, "feature-large-sector-size", "%u", + &feature_large_sector_size) != 1) { + feature_large_sector_size = 0; + } + + if (feature_large_sector_size != 1 && + conf->logical_block_size != XEN_BLKIF_SECTOR_SIZE) { + error_setg(errp, "logical_block_size != %u not supported by frontend", + XEN_BLKIF_SECTOR_SIZE); + return; + } + if (xen_device_frontend_scanf(xendev, "ring-page-order", "%u", &order) != 1) { nr_ring_ref = 1; @@ -150,7 +164,7 @@ static void xen_block_set_size(XenBlockDevice *blockdev) const char *type = object_get_typename(OBJECT(blockdev)); XenBlockVdev *vdev = &blockdev->props.vdev; BlockConf *conf = &blockdev->props.conf; - int64_t sectors = blk_getlength(conf->blk) / XEN_BLKIF_SECTOR_SIZE; + int64_t sectors = blk_getlength(conf->blk) / conf->logical_block_size; XenDevice *xendev = XEN_DEVICE(blockdev); trace_xen_block_size(type, vdev->disk, vdev->partition, sectors); @@ -185,6 +199,7 @@ static void xen_block_realize(XenDevice *xendev, Error **errp) const char *type = object_get_typename(OBJECT(blockdev)); XenBlockVdev *vdev = &blockdev->props.vdev; BlockConf *conf = &blockdev->props.conf; + BlockBackend *blk = conf->blk; Error *local_err = NULL; if (vdev->type == XEN_BLOCK_VDEV_TYPE_INVALID) { @@ -206,8 +221,8 @@ static void xen_block_realize(XenDevice *xendev, Error **errp) * The blkif protocol does not deal with removable media, so it must * always be present, even for CDRom devices. */ - assert(conf->blk); - if (!blk_is_inserted(conf->blk)) { + assert(blk); + if (!blk_is_inserted(blk)) { error_setg(errp, "device needs media, but drive is empty"); return; } @@ -224,26 +239,20 @@ static void xen_block_realize(XenDevice *xendev, Error **errp) blkconf_blocksizes(conf); - if (conf->logical_block_size != XEN_BLKIF_SECTOR_SIZE) { - error_setg(errp, "logical_block_size != %u not supported", - XEN_BLKIF_SECTOR_SIZE); - return; - } - if (conf->logical_block_size > conf->physical_block_size) { error_setg( errp, "logical_block_size > physical_block_size not supported"); return; } - blk_set_dev_ops(conf->blk, &xen_block_dev_ops, blockdev); - blk_set_guest_block_size(conf->blk, conf->logical_block_size); + blk_set_dev_ops(blk, &xen_block_dev_ops, blockdev); + blk_set_guest_block_size(blk, conf->logical_block_size); if (conf->discard_granularity == -1) { conf->discard_granularity = conf->physical_block_size; } - if (blk_get_flags(conf->blk) & BDRV_O_UNMAP) { + if (blk_get_flags(blk) & BDRV_O_UNMAP) { xen_device_backend_printf(xendev, "feature-discard", "%u", 1); xen_device_backend_printf(xendev, "discard-granularity", "%u", conf->discard_granularity); @@ -260,12 +269,13 @@ static void xen_block_realize(XenDevice *xendev, Error **errp) blockdev->device_type); xen_device_backend_printf(xendev, "sector-size", "%u", - XEN_BLKIF_SECTOR_SIZE); + conf->logical_block_size); xen_block_set_size(blockdev); blockdev->dataplane = - xen_block_dataplane_create(xendev, conf, blockdev->props.iothread); + xen_block_dataplane_create(xendev, blk, conf->logical_block_size, + blockdev->props.iothread); } static void xen_block_frontend_changed(XenDevice *xendev, diff --git a/hw/block/xen_blkif.h b/hw/block/xen_blkif.h index a353693ea0..99733529c1 100644 --- a/hw/block/xen_blkif.h +++ b/hw/block/xen_blkif.h @@ -1,9 +1,8 @@ #ifndef XEN_BLKIF_H #define XEN_BLKIF_H -#include "hw/xen/io/ring.h" -#include <xen/io/blkif.h> -#include <xen/io/protocols.h> +#include "hw/xen/interface/io/blkif.h" +#include "hw/xen/interface/io/protocols.h" /* * Not a real protocol. Used to generate ring structs which contain diff --git a/hw/char/xen_console.c b/hw/char/xen_console.c index 91f34ef06c..47e1092263 100644 --- a/hw/char/xen_console.c +++ b/hw/char/xen_console.c @@ -28,7 +28,7 @@ #include "chardev/char-fe.h" #include "hw/xen/xen-legacy-backend.h" -#include <xen/io/console.h> +#include "hw/xen/interface/io/console.h" struct buffer { uint8_t *data; diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 910dccb2f7..cbdf7b1a67 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -130,3 +130,5 @@ config ATI_VGA default y if PCI_DEVICES depends on PCI select VGA + select BITBANG_I2C + select DDC diff --git a/hw/display/ati.c b/hw/display/ati.c index 76595d9511..0cb1173848 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "hw/hw.h" #include "ui/console.h" +#include "hw/display/i2c-ddc.h" #include "trace.h" #define ATI_DEBUG_HW_CURSOR 0 @@ -215,6 +216,24 @@ static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) } } +static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base) +{ + bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1); + bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1); + + bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c); + d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d); + + data &= ~0xf00ULL; + if (c) { + data |= BIT(base + 9); + } + if (d) { + data |= BIT(base + 8); + } + return data; +} + static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs, unsigned int size) { @@ -266,7 +285,16 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) case DAC_CNTL: val = s->regs.dac_cntl; break; -/* case GPIO_MONID: FIXME hook up DDC I2C here */ + case GPIO_VGA_DDC: + val = s->regs.gpio_vga_ddc; + break; + case GPIO_DVI_DDC: + val = s->regs.gpio_dvi_ddc; + break; + case GPIO_MONID ... GPIO_MONID + 3: + val = ati_reg_read_offs(s->regs.gpio_monid, + addr - GPIO_MONID, size); + break; case PALETTE_INDEX: /* FIXME unaligned access */ val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16; @@ -391,9 +419,15 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) break; case DEFAULT_OFFSET: val = s->regs.default_offset; + if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { + val >>= 10; + val |= s->regs.default_pitch << 16; + val |= s->regs.default_tile << 30; + } break; case DEFAULT_PITCH: val = s->regs.default_pitch; + val |= s->regs.default_tile << 16; break; case DEFAULT_SC_BOTTOM_RIGHT: val = s->regs.default_sc_bottom_right; @@ -497,7 +531,33 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dac_cntl = data & 0xffffe3ff; s->vga.dac_8bit = !!(data & DAC_8BIT_EN); break; -/* case GPIO_MONID: FIXME hook up DDC I2C here */ + case GPIO_VGA_DDC: + if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { + /* FIXME: Maybe add a property to select VGA or DVI port? */ + } + break; + case GPIO_DVI_DDC: + if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { + s->regs.gpio_dvi_ddc = ati_i2c(s->bbi2c, data, 0); + } + break; + case GPIO_MONID ... GPIO_MONID + 3: + /* FIXME What does Radeon have here? */ + if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { + ati_reg_write_offs(&s->regs.gpio_monid, + addr - GPIO_MONID, data, size); + /* + * Rage128p accesses DDC used to get EDID via these bits. + * Only touch i2c when write overlaps 3rd byte because some + * drivers access this reg via multiple partial writes and + * without this spurious bits would be sent. + */ + if ((s->regs.gpio_monid & BIT(25)) && + addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) { + s->regs.gpio_monid = ati_i2c(s->bbi2c, s->regs.gpio_monid, 1); + } + } + break; case PALETTE_INDEX ... PALETTE_INDEX + 3: if (size == 4) { vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); @@ -628,22 +688,22 @@ static void ati_mm_write(void *opaque, hwaddr addr, break; case SRC_PITCH_OFFSET: if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.src_offset = (data & 0x1fffff) << 5; - s->regs.src_pitch = (data >> 21) & 0x3ff; + s->regs.src_offset = (data & 0x1fffff) << 4; + s->regs.src_pitch = (data & 0x7fe00000) >> 21; s->regs.src_tile = data >> 31; } else { - s->regs.src_offset = (data & 0x3fffff) << 11; + s->regs.src_offset = (data & 0x3fffff) << 10; s->regs.src_pitch = (data & 0x3fc00000) >> 16; s->regs.src_tile = (data >> 30) & 1; } break; case DST_PITCH_OFFSET: if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.dst_offset = (data & 0x1fffff) << 5; - s->regs.dst_pitch = (data >> 21) & 0x3ff; + s->regs.dst_offset = (data & 0x1fffff) << 4; + s->regs.dst_pitch = (data & 0x7fe00000) >> 21; s->regs.dst_tile = data >> 31; } else { - s->regs.dst_offset = (data & 0x3fffff) << 11; + s->regs.dst_offset = (data & 0x3fffff) << 10; s->regs.dst_pitch = (data & 0x3fc00000) >> 16; s->regs.dst_tile = data >> 30; } @@ -723,13 +783,19 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dp_write_mask = data; break; case DEFAULT_OFFSET: - data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ? - 0x03fffc00 : 0xfffffc00); - s->regs.default_offset = data; + if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { + s->regs.default_offset = data & 0xfffffff0; + } else { + /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ + s->regs.default_offset = (data & 0x3fffff) << 10; + s->regs.default_pitch = (data & 0x3fc00000) >> 16; + s->regs.default_tile = data >> 30; + } break; case DEFAULT_PITCH: if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.default_pitch = data & 0x103ff; + s->regs.default_pitch = data & 0x3fff; + s->regs.default_tile = (data >> 16) & 1; } break; case DEFAULT_SC_BOTTOM_RIGHT: @@ -788,6 +854,12 @@ static void ati_vga_realize(PCIDevice *dev, Error **errp) vga->cursor_draw_line = ati_cursor_draw_line; } + /* ddc, edid */ + I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc"); + s->bbi2c = bitbang_i2c_init(i2cbus); + I2CSlave *i2cddc = I2C_SLAVE(qdev_create(BUS(i2cbus), TYPE_I2CDDC)); + i2c_set_slave_address(i2cddc, 0x50); + /* mmio register space */ memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, "ati.mmregs", 0x4000); @@ -813,6 +885,7 @@ static void ati_vga_exit(PCIDevice *dev) ATIVGAState *s = ATI_VGA(dev); graphic_console_close(s->vga.con); + g_free(s->bbi2c); } static Property ati_vga_properties[] = { @@ -837,7 +910,7 @@ static void ati_vga_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_DISPLAY_VGA; k->vendor_id = PCI_VENDOR_ID_ATI; k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF; - k->romfile = "vgabios-stdvga.bin"; + k->romfile = "vgabios-ati.bin"; k->realize = ati_vga_realize; k->exit = ati_vga_exit; } diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index d83c29c6d9..2dbf53f039 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -51,8 +51,9 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); - DPRINTF("%d %d, %d %d, (%d,%d) -> (%d,%d) %dx%d\n", s->regs.src_offset, - s->regs.dst_offset, s->regs.src_pitch, s->regs.dst_pitch, + DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n", + s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, + s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, s->regs.dst_width, s->regs.dst_height); switch (s->regs.dp_mix & GMC_ROP3_MASK) { @@ -60,10 +61,16 @@ void ati_2d_blt(ATIVGAState *s) { uint8_t *src_bits, *dst_bits, *end; int src_stride, dst_stride, bpp = ati_bpp_from_datatype(s); - src_bits = s->vga.vram_ptr + s->regs.src_offset; - dst_bits = s->vga.vram_ptr + s->regs.dst_offset; - src_stride = s->regs.src_pitch; - dst_stride = s->regs.dst_pitch; + src_bits = s->vga.vram_ptr + + (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ? + s->regs.src_offset : s->regs.default_offset); + dst_bits = s->vga.vram_ptr + + (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? + s->regs.dst_offset : s->regs.default_offset); + src_stride = (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL ? + s->regs.src_pitch : s->regs.default_pitch); + dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? + s->regs.dst_pitch : s->regs.default_pitch); if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { src_bits += s->regs.crtc_offset & 0x07ffffff; @@ -111,8 +118,11 @@ void ati_2d_blt(ATIVGAState *s) uint8_t *dst_bits, *end; int dst_stride, bpp = ati_bpp_from_datatype(s); uint32_t filler = 0; - dst_bits = s->vga.vram_ptr + s->regs.dst_offset; - dst_stride = s->regs.dst_pitch; + dst_bits = s->vga.vram_ptr + + (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? + s->regs.dst_offset : s->regs.default_offset); + dst_stride = (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL ? + s->regs.dst_pitch : s->regs.default_pitch); if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { dst_bits += s->regs.crtc_offset & 0x07ffffff; diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c index b045f81d06..88b3a11315 100644 --- a/hw/display/ati_dbg.c +++ b/hw/display/ati_dbg.c @@ -19,6 +19,8 @@ static struct ati_regdesc ati_reg_names[] = { {"CRTC_GEN_CNTL", 0x0050}, {"CRTC_EXT_CNTL", 0x0054}, {"DAC_CNTL", 0x0058}, + {"GPIO_VGA_DDC", 0x0060}, + {"GPIO_DVI_DDC", 0x0064}, {"GPIO_MONID", 0x0068}, {"I2C_CNTL_1", 0x0094}, {"PALETTE_INDEX", 0x00b0}, diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 2f426064cf..9b67d0022a 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -10,6 +10,7 @@ #define ATI_INT_H #include "hw/pci/pci.h" +#include "hw/i2c/bitbang_i2c.h" #include "vga_int.h" /*#define DEBUG_ATI*/ @@ -35,6 +36,9 @@ typedef struct ATIVGARegs { uint32_t crtc_gen_cntl; uint32_t crtc_ext_cntl; uint32_t dac_cntl; + uint32_t gpio_vga_ddc; + uint32_t gpio_dvi_ddc; + uint32_t gpio_monid; uint32_t crtc_h_total_disp; uint32_t crtc_h_sync_strt_wid; uint32_t crtc_v_total_disp; @@ -70,6 +74,7 @@ typedef struct ATIVGARegs { uint32_t dp_write_mask; uint32_t default_offset; uint32_t default_pitch; + uint32_t default_tile; uint32_t default_sc_bottom_right; } ATIVGARegs; @@ -83,6 +88,7 @@ typedef struct ATIVGAState { uint16_t cursor_size; uint32_t cursor_offset; QEMUCursor *cursor; + bitbang_i2c_interface *bbi2c; MemoryRegion io; MemoryRegion mm; ATIVGARegs regs; diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 923bfd33ce..d7155c93d5 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -37,6 +37,8 @@ #define CRTC_GEN_CNTL 0x0050 #define CRTC_EXT_CNTL 0x0054 #define DAC_CNTL 0x0058 +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 #define GPIO_MONID 0x0068 #define I2C_CNTL_1 0x0094 #define PALETTE_INDEX 0x00b0 @@ -368,8 +370,8 @@ #define BRUSH_SOLIDCOLOR 0x00000d00 /* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_CNTL 0x00000001 +#define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 #define GMC_SRC_CLIP_DEFAULT 0x00000000 #define GMC_DST_CLIP_DEFAULT 0x00000000 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c index 6202f1150e..3c79913b31 100644 --- a/hw/display/xenfb.c +++ b/hw/display/xenfb.c @@ -32,10 +32,9 @@ #include "ui/console.h" #include "hw/xen/xen-legacy-backend.h" -#include <xen/event_channel.h> -#include <xen/io/fbif.h> -#include <xen/io/kbdif.h> -#include <xen/io/protocols.h> +#include "hw/xen/interface/io/fbif.h" +#include "hw/xen/interface/io/kbdif.h" +#include "hw/xen/interface/io/protocols.h" #include "trace.h" diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 6ccafece18..155af9b26a 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -23,6 +23,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "hw/hw.h" #include "hw/mips/mips.h" #include "hw/sysbus.h" @@ -57,8 +58,8 @@ typedef struct dma_pagetable_entry { #define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region" -typedef struct rc4030State -{ +typedef struct rc4030State { + SysBusDevice parent; uint32_t config; /* 0x0000: RC4030 config register */ @@ -151,8 +152,9 @@ static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size) case 0x0058: val = s->cache_bmask; /* HACK */ - if (s->cache_bmask == (uint32_t)-1) + if (s->cache_bmask == (uint32_t)-1) { s->cache_bmask = 0; + } break; /* Remote Speed Registers */ case 0x0070: @@ -537,8 +539,9 @@ static void rc4030_reset(DeviceState *dev) s->memory_refresh_rate = 0x18186; s->nvram_protect = 7; - for (i = 0; i < 15; i++) + for (i = 0; i < 15; i++) { s->rem_speed[i] = 7; + } s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ s->isr_jazz = 0; @@ -550,7 +553,7 @@ static void rc4030_reset(DeviceState *dev) static int rc4030_post_load(void *opaque, int version_id) { - rc4030State* s = opaque; + rc4030State *s = opaque; set_next_tick(s); update_jazz_irq(s); @@ -590,7 +593,8 @@ static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_wri hwaddr dma_addr; int dev_to_mem; - s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); + s->dma_regs[n][DMA_REG_ENABLE] &= + ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); /* Check DMA channel consistency */ dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; @@ -602,8 +606,9 @@ static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_wri } /* Get start address and len */ - if (len > s->dma_regs[n][DMA_REG_COUNT]) + if (len > s->dma_regs[n][DMA_REG_COUNT]) { len = s->dma_regs[n][DMA_REG_COUNT]; + } dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; /* Read/write data at right place */ @@ -678,7 +683,7 @@ static void rc4030_realize(DeviceState *dev, Error **errp) memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr), TYPE_RC4030_IOMMU_MEMORY_REGION, - o, "rc4030.dma", UINT32_MAX); + o, "rc4030.dma", 4 * GiB); address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma"); } diff --git a/hw/i2c/bitbang_i2c.c b/hw/i2c/bitbang_i2c.c index 5dfc72d9d7..3cb0509b02 100644 --- a/hw/i2c/bitbang_i2c.c +++ b/hw/i2c/bitbang_i2c.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "hw/hw.h" -#include "bitbang_i2c.h" +#include "hw/i2c/bitbang_i2c.h" #include "hw/sysbus.h" #include "qemu/module.h" diff --git a/hw/i2c/bitbang_i2c.h b/hw/i2c/bitbang_i2c.h deleted file mode 100644 index 9443021710..0000000000 --- a/hw/i2c/bitbang_i2c.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef BITBANG_I2C_H -#define BITBANG_I2C_H - -#include "hw/i2c/i2c.h" - -#define BITBANG_I2C_SDA 0 -#define BITBANG_I2C_SCL 1 - -bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus); -int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level); - -#endif diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index d606d3dbeb..5fb4f86c38 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -30,7 +30,6 @@ #include "cpu.h" #include "hw/hw.h" #include "hw/i2c/ppc4xx_i2c.h" -#include "bitbang_i2c.h" #define PPC4xx_I2C_MEM_SIZE 18 diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c index e07be9890c..24b6e36b6d 100644 --- a/hw/i2c/versatile_i2c.c +++ b/hw/i2c/versatile_i2c.c @@ -23,7 +23,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" -#include "bitbang_i2c.h" +#include "hw/i2c/bitbang_i2c.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 2939122e7c..469f1260a4 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -27,7 +27,6 @@ #include "exec/address-spaces.h" #include <xen/hvm/ioreq.h> -#include <xen/hvm/params.h> #include <xen/hvm/e820.h> //#define DEBUG_XEN_HVM @@ -120,6 +119,8 @@ typedef struct XenIOState { DeviceListener device_listener; hwaddr free_phys_offset; const XenPhysmap *log_for_dirtybit; + /* Buffer used by xen_sync_dirty_bitmap */ + unsigned long *dirty_bitmap; Notifier exit; Notifier suspend; @@ -465,6 +466,8 @@ static int xen_remove_from_physmap(XenIOState *state, QLIST_REMOVE(physmap, list); if (state->log_for_dirtybit == physmap) { state->log_for_dirtybit = NULL; + g_free(state->dirty_bitmap); + state->dirty_bitmap = NULL; } g_free(physmap); @@ -615,7 +618,7 @@ static void xen_sync_dirty_bitmap(XenIOState *state, { hwaddr npages = size >> TARGET_PAGE_BITS; const int width = sizeof(unsigned long) * 8; - unsigned long bitmap[DIV_ROUND_UP(npages, width)]; + size_t bitmap_size = DIV_ROUND_UP(npages, width); int rc, i, j; const XenPhysmap *physmap = NULL; @@ -627,13 +630,14 @@ static void xen_sync_dirty_bitmap(XenIOState *state, if (state->log_for_dirtybit == NULL) { state->log_for_dirtybit = physmap; + state->dirty_bitmap = g_new(unsigned long, bitmap_size); } else if (state->log_for_dirtybit != physmap) { /* Only one range for dirty bitmap can be tracked. */ return; } rc = xen_track_dirty_vram(xen_domid, start_addr >> TARGET_PAGE_BITS, - npages, bitmap); + npages, state->dirty_bitmap); if (rc < 0) { #ifndef ENODATA #define ENODATA ENOENT @@ -647,8 +651,8 @@ static void xen_sync_dirty_bitmap(XenIOState *state, return; } - for (i = 0; i < ARRAY_SIZE(bitmap); i++) { - unsigned long map = bitmap[i]; + for (i = 0; i < bitmap_size; i++) { + unsigned long map = state->dirty_bitmap[i]; while (map != 0) { j = ctzl(map); map &= ~(1ul << j); @@ -678,6 +682,8 @@ static void xen_log_stop(MemoryListener *listener, MemoryRegionSection *section, if (old & ~new & (1 << DIRTY_MEMORY_VGA)) { state->log_for_dirtybit = NULL; + g_free(state->dirty_bitmap); + state->dirty_bitmap = NULL; /* Disable dirty bit tracking */ xen_track_dirty_vram(xen_domid, 0, 0, NULL); } diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c index 254759f776..dc73c86c61 100644 --- a/hw/i386/xen/xen-mapcache.c +++ b/hw/i386/xen/xen-mapcache.c @@ -17,8 +17,6 @@ #include "hw/xen/xen-legacy-backend.h" #include "qemu/bitmap.h" -#include <xen/hvm/params.h> - #include "sysemu/xen-mapcache.h" #include "trace.h" diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index f707e59c7a..2fa313f498 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -23,207 +23,202 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/log.h" #include "hw/hw.h" #include "hw/mips/mips.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" #include "exec/address-spaces.h" +#include "trace.h" -//#define DEBUG - -#ifdef DEBUG -#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) -#else -#define DPRINTF(fmt, ...) -#endif - -#define GT_REGS (0x1000 >> 2) +#define GT_REGS (0x1000 >> 2) /* CPU Configuration */ -#define GT_CPU (0x000 >> 2) -#define GT_MULTI (0x120 >> 2) +#define GT_CPU (0x000 >> 2) +#define GT_MULTI (0x120 >> 2) /* CPU Address Decode */ -#define GT_SCS10LD (0x008 >> 2) -#define GT_SCS10HD (0x010 >> 2) -#define GT_SCS32LD (0x018 >> 2) -#define GT_SCS32HD (0x020 >> 2) -#define GT_CS20LD (0x028 >> 2) -#define GT_CS20HD (0x030 >> 2) -#define GT_CS3BOOTLD (0x038 >> 2) -#define GT_CS3BOOTHD (0x040 >> 2) -#define GT_PCI0IOLD (0x048 >> 2) -#define GT_PCI0IOHD (0x050 >> 2) -#define GT_PCI0M0LD (0x058 >> 2) -#define GT_PCI0M0HD (0x060 >> 2) -#define GT_PCI0M1LD (0x080 >> 2) -#define GT_PCI0M1HD (0x088 >> 2) -#define GT_PCI1IOLD (0x090 >> 2) -#define GT_PCI1IOHD (0x098 >> 2) -#define GT_PCI1M0LD (0x0a0 >> 2) -#define GT_PCI1M0HD (0x0a8 >> 2) -#define GT_PCI1M1LD (0x0b0 >> 2) -#define GT_PCI1M1HD (0x0b8 >> 2) -#define GT_ISD (0x068 >> 2) - -#define GT_SCS10AR (0x0d0 >> 2) -#define GT_SCS32AR (0x0d8 >> 2) -#define GT_CS20R (0x0e0 >> 2) -#define GT_CS3BOOTR (0x0e8 >> 2) - -#define GT_PCI0IOREMAP (0x0f0 >> 2) -#define GT_PCI0M0REMAP (0x0f8 >> 2) -#define GT_PCI0M1REMAP (0x100 >> 2) -#define GT_PCI1IOREMAP (0x108 >> 2) -#define GT_PCI1M0REMAP (0x110 >> 2) -#define GT_PCI1M1REMAP (0x118 >> 2) +#define GT_SCS10LD (0x008 >> 2) +#define GT_SCS10HD (0x010 >> 2) +#define GT_SCS32LD (0x018 >> 2) +#define GT_SCS32HD (0x020 >> 2) +#define GT_CS20LD (0x028 >> 2) +#define GT_CS20HD (0x030 >> 2) +#define GT_CS3BOOTLD (0x038 >> 2) +#define GT_CS3BOOTHD (0x040 >> 2) +#define GT_PCI0IOLD (0x048 >> 2) +#define GT_PCI0IOHD (0x050 >> 2) +#define GT_PCI0M0LD (0x058 >> 2) +#define GT_PCI0M0HD (0x060 >> 2) +#define GT_PCI0M1LD (0x080 >> 2) +#define GT_PCI0M1HD (0x088 >> 2) +#define GT_PCI1IOLD (0x090 >> 2) +#define GT_PCI1IOHD (0x098 >> 2) +#define GT_PCI1M0LD (0x0a0 >> 2) +#define GT_PCI1M0HD (0x0a8 >> 2) +#define GT_PCI1M1LD (0x0b0 >> 2) +#define GT_PCI1M1HD (0x0b8 >> 2) +#define GT_ISD (0x068 >> 2) + +#define GT_SCS10AR (0x0d0 >> 2) +#define GT_SCS32AR (0x0d8 >> 2) +#define GT_CS20R (0x0e0 >> 2) +#define GT_CS3BOOTR (0x0e8 >> 2) + +#define GT_PCI0IOREMAP (0x0f0 >> 2) +#define GT_PCI0M0REMAP (0x0f8 >> 2) +#define GT_PCI0M1REMAP (0x100 >> 2) +#define GT_PCI1IOREMAP (0x108 >> 2) +#define GT_PCI1M0REMAP (0x110 >> 2) +#define GT_PCI1M1REMAP (0x118 >> 2) /* CPU Error Report */ -#define GT_CPUERR_ADDRLO (0x070 >> 2) -#define GT_CPUERR_ADDRHI (0x078 >> 2) -#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ -#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ -#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ +#define GT_CPUERR_ADDRLO (0x070 >> 2) +#define GT_CPUERR_ADDRHI (0x078 >> 2) +#define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ +#define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ +#define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ /* CPU Sync Barrier */ -#define GT_PCI0SYNC (0x0c0 >> 2) -#define GT_PCI1SYNC (0x0c8 >> 2) +#define GT_PCI0SYNC (0x0c0 >> 2) +#define GT_PCI1SYNC (0x0c8 >> 2) /* SDRAM and Device Address Decode */ -#define GT_SCS0LD (0x400 >> 2) -#define GT_SCS0HD (0x404 >> 2) -#define GT_SCS1LD (0x408 >> 2) -#define GT_SCS1HD (0x40c >> 2) -#define GT_SCS2LD (0x410 >> 2) -#define GT_SCS2HD (0x414 >> 2) -#define GT_SCS3LD (0x418 >> 2) -#define GT_SCS3HD (0x41c >> 2) -#define GT_CS0LD (0x420 >> 2) -#define GT_CS0HD (0x424 >> 2) -#define GT_CS1LD (0x428 >> 2) -#define GT_CS1HD (0x42c >> 2) -#define GT_CS2LD (0x430 >> 2) -#define GT_CS2HD (0x434 >> 2) -#define GT_CS3LD (0x438 >> 2) -#define GT_CS3HD (0x43c >> 2) -#define GT_BOOTLD (0x440 >> 2) -#define GT_BOOTHD (0x444 >> 2) -#define GT_ADERR (0x470 >> 2) +#define GT_SCS0LD (0x400 >> 2) +#define GT_SCS0HD (0x404 >> 2) +#define GT_SCS1LD (0x408 >> 2) +#define GT_SCS1HD (0x40c >> 2) +#define GT_SCS2LD (0x410 >> 2) +#define GT_SCS2HD (0x414 >> 2) +#define GT_SCS3LD (0x418 >> 2) +#define GT_SCS3HD (0x41c >> 2) +#define GT_CS0LD (0x420 >> 2) +#define GT_CS0HD (0x424 >> 2) +#define GT_CS1LD (0x428 >> 2) +#define GT_CS1HD (0x42c >> 2) +#define GT_CS2LD (0x430 >> 2) +#define GT_CS2HD (0x434 >> 2) +#define GT_CS3LD (0x438 >> 2) +#define GT_CS3HD (0x43c >> 2) +#define GT_BOOTLD (0x440 >> 2) +#define GT_BOOTHD (0x444 >> 2) +#define GT_ADERR (0x470 >> 2) /* SDRAM Configuration */ -#define GT_SDRAM_CFG (0x448 >> 2) -#define GT_SDRAM_OPMODE (0x474 >> 2) -#define GT_SDRAM_BM (0x478 >> 2) -#define GT_SDRAM_ADDRDECODE (0x47c >> 2) +#define GT_SDRAM_CFG (0x448 >> 2) +#define GT_SDRAM_OPMODE (0x474 >> 2) +#define GT_SDRAM_BM (0x478 >> 2) +#define GT_SDRAM_ADDRDECODE (0x47c >> 2) /* SDRAM Parameters */ -#define GT_SDRAM_B0 (0x44c >> 2) -#define GT_SDRAM_B1 (0x450 >> 2) -#define GT_SDRAM_B2 (0x454 >> 2) -#define GT_SDRAM_B3 (0x458 >> 2) +#define GT_SDRAM_B0 (0x44c >> 2) +#define GT_SDRAM_B1 (0x450 >> 2) +#define GT_SDRAM_B2 (0x454 >> 2) +#define GT_SDRAM_B3 (0x458 >> 2) /* Device Parameters */ -#define GT_DEV_B0 (0x45c >> 2) -#define GT_DEV_B1 (0x460 >> 2) -#define GT_DEV_B2 (0x464 >> 2) -#define GT_DEV_B3 (0x468 >> 2) -#define GT_DEV_BOOT (0x46c >> 2) +#define GT_DEV_B0 (0x45c >> 2) +#define GT_DEV_B1 (0x460 >> 2) +#define GT_DEV_B2 (0x464 >> 2) +#define GT_DEV_B3 (0x468 >> 2) +#define GT_DEV_BOOT (0x46c >> 2) /* ECC */ -#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ -#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ -#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ -#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ -#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ +#define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ +#define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ +#define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ +#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ +#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ /* DMA Record */ -#define GT_DMA0_CNT (0x800 >> 2) -#define GT_DMA1_CNT (0x804 >> 2) -#define GT_DMA2_CNT (0x808 >> 2) -#define GT_DMA3_CNT (0x80c >> 2) -#define GT_DMA0_SA (0x810 >> 2) -#define GT_DMA1_SA (0x814 >> 2) -#define GT_DMA2_SA (0x818 >> 2) -#define GT_DMA3_SA (0x81c >> 2) -#define GT_DMA0_DA (0x820 >> 2) -#define GT_DMA1_DA (0x824 >> 2) -#define GT_DMA2_DA (0x828 >> 2) -#define GT_DMA3_DA (0x82c >> 2) -#define GT_DMA0_NEXT (0x830 >> 2) -#define GT_DMA1_NEXT (0x834 >> 2) -#define GT_DMA2_NEXT (0x838 >> 2) -#define GT_DMA3_NEXT (0x83c >> 2) -#define GT_DMA0_CUR (0x870 >> 2) -#define GT_DMA1_CUR (0x874 >> 2) -#define GT_DMA2_CUR (0x878 >> 2) -#define GT_DMA3_CUR (0x87c >> 2) +#define GT_DMA0_CNT (0x800 >> 2) +#define GT_DMA1_CNT (0x804 >> 2) +#define GT_DMA2_CNT (0x808 >> 2) +#define GT_DMA3_CNT (0x80c >> 2) +#define GT_DMA0_SA (0x810 >> 2) +#define GT_DMA1_SA (0x814 >> 2) +#define GT_DMA2_SA (0x818 >> 2) +#define GT_DMA3_SA (0x81c >> 2) +#define GT_DMA0_DA (0x820 >> 2) +#define GT_DMA1_DA (0x824 >> 2) +#define GT_DMA2_DA (0x828 >> 2) +#define GT_DMA3_DA (0x82c >> 2) +#define GT_DMA0_NEXT (0x830 >> 2) +#define GT_DMA1_NEXT (0x834 >> 2) +#define GT_DMA2_NEXT (0x838 >> 2) +#define GT_DMA3_NEXT (0x83c >> 2) +#define GT_DMA0_CUR (0x870 >> 2) +#define GT_DMA1_CUR (0x874 >> 2) +#define GT_DMA2_CUR (0x878 >> 2) +#define GT_DMA3_CUR (0x87c >> 2) /* DMA Channel Control */ -#define GT_DMA0_CTRL (0x840 >> 2) -#define GT_DMA1_CTRL (0x844 >> 2) -#define GT_DMA2_CTRL (0x848 >> 2) -#define GT_DMA3_CTRL (0x84c >> 2) +#define GT_DMA0_CTRL (0x840 >> 2) +#define GT_DMA1_CTRL (0x844 >> 2) +#define GT_DMA2_CTRL (0x848 >> 2) +#define GT_DMA3_CTRL (0x84c >> 2) /* DMA Arbiter */ -#define GT_DMA_ARB (0x860 >> 2) +#define GT_DMA_ARB (0x860 >> 2) /* Timer/Counter */ -#define GT_TC0 (0x850 >> 2) -#define GT_TC1 (0x854 >> 2) -#define GT_TC2 (0x858 >> 2) -#define GT_TC3 (0x85c >> 2) -#define GT_TC_CONTROL (0x864 >> 2) +#define GT_TC0 (0x850 >> 2) +#define GT_TC1 (0x854 >> 2) +#define GT_TC2 (0x858 >> 2) +#define GT_TC3 (0x85c >> 2) +#define GT_TC_CONTROL (0x864 >> 2) /* PCI Internal */ -#define GT_PCI0_CMD (0xc00 >> 2) -#define GT_PCI0_TOR (0xc04 >> 2) -#define GT_PCI0_BS_SCS10 (0xc08 >> 2) -#define GT_PCI0_BS_SCS32 (0xc0c >> 2) -#define GT_PCI0_BS_CS20 (0xc10 >> 2) -#define GT_PCI0_BS_CS3BT (0xc14 >> 2) -#define GT_PCI1_IACK (0xc30 >> 2) -#define GT_PCI0_IACK (0xc34 >> 2) -#define GT_PCI0_BARE (0xc3c >> 2) -#define GT_PCI0_PREFMBR (0xc40 >> 2) -#define GT_PCI0_SCS10_BAR (0xc48 >> 2) -#define GT_PCI0_SCS32_BAR (0xc4c >> 2) -#define GT_PCI0_CS20_BAR (0xc50 >> 2) -#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) -#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) -#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) -#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) -#define GT_PCI1_CMD (0xc80 >> 2) -#define GT_PCI1_TOR (0xc84 >> 2) -#define GT_PCI1_BS_SCS10 (0xc88 >> 2) -#define GT_PCI1_BS_SCS32 (0xc8c >> 2) -#define GT_PCI1_BS_CS20 (0xc90 >> 2) -#define GT_PCI1_BS_CS3BT (0xc94 >> 2) -#define GT_PCI1_BARE (0xcbc >> 2) -#define GT_PCI1_PREFMBR (0xcc0 >> 2) -#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) -#define GT_PCI1_SCS32_BAR (0xccc >> 2) -#define GT_PCI1_CS20_BAR (0xcd0 >> 2) -#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) -#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) -#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) -#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) -#define GT_PCI1_CFGADDR (0xcf0 >> 2) -#define GT_PCI1_CFGDATA (0xcf4 >> 2) -#define GT_PCI0_CFGADDR (0xcf8 >> 2) -#define GT_PCI0_CFGDATA (0xcfc >> 2) +#define GT_PCI0_CMD (0xc00 >> 2) +#define GT_PCI0_TOR (0xc04 >> 2) +#define GT_PCI0_BS_SCS10 (0xc08 >> 2) +#define GT_PCI0_BS_SCS32 (0xc0c >> 2) +#define GT_PCI0_BS_CS20 (0xc10 >> 2) +#define GT_PCI0_BS_CS3BT (0xc14 >> 2) +#define GT_PCI1_IACK (0xc30 >> 2) +#define GT_PCI0_IACK (0xc34 >> 2) +#define GT_PCI0_BARE (0xc3c >> 2) +#define GT_PCI0_PREFMBR (0xc40 >> 2) +#define GT_PCI0_SCS10_BAR (0xc48 >> 2) +#define GT_PCI0_SCS32_BAR (0xc4c >> 2) +#define GT_PCI0_CS20_BAR (0xc50 >> 2) +#define GT_PCI0_CS3BT_BAR (0xc54 >> 2) +#define GT_PCI0_SSCS10_BAR (0xc58 >> 2) +#define GT_PCI0_SSCS32_BAR (0xc5c >> 2) +#define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) +#define GT_PCI1_CMD (0xc80 >> 2) +#define GT_PCI1_TOR (0xc84 >> 2) +#define GT_PCI1_BS_SCS10 (0xc88 >> 2) +#define GT_PCI1_BS_SCS32 (0xc8c >> 2) +#define GT_PCI1_BS_CS20 (0xc90 >> 2) +#define GT_PCI1_BS_CS3BT (0xc94 >> 2) +#define GT_PCI1_BARE (0xcbc >> 2) +#define GT_PCI1_PREFMBR (0xcc0 >> 2) +#define GT_PCI1_SCS10_BAR (0xcc8 >> 2) +#define GT_PCI1_SCS32_BAR (0xccc >> 2) +#define GT_PCI1_CS20_BAR (0xcd0 >> 2) +#define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) +#define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) +#define GT_PCI1_SSCS32_BAR (0xcdc >> 2) +#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) +#define GT_PCI1_CFGADDR (0xcf0 >> 2) +#define GT_PCI1_CFGDATA (0xcf4 >> 2) +#define GT_PCI0_CFGADDR (0xcf8 >> 2) +#define GT_PCI0_CFGDATA (0xcfc >> 2) /* Interrupts */ -#define GT_INTRCAUSE (0xc18 >> 2) -#define GT_INTRMASK (0xc1c >> 2) -#define GT_PCI0_ICMASK (0xc24 >> 2) -#define GT_PCI0_SERR0MASK (0xc28 >> 2) -#define GT_CPU_INTSEL (0xc70 >> 2) -#define GT_PCI0_INTSEL (0xc74 >> 2) -#define GT_HINTRCAUSE (0xc98 >> 2) -#define GT_HINTRMASK (0xc9c >> 2) -#define GT_PCI0_HICMASK (0xca4 >> 2) -#define GT_PCI1_SERR1MASK (0xca8 >> 2) +#define GT_INTRCAUSE (0xc18 >> 2) +#define GT_INTRMASK (0xc1c >> 2) +#define GT_PCI0_ICMASK (0xc24 >> 2) +#define GT_PCI0_SERR0MASK (0xc28 >> 2) +#define GT_CPU_INTSEL (0xc70 >> 2) +#define GT_PCI0_INTSEL (0xc74 >> 2) +#define GT_HINTRCAUSE (0xc98 >> 2) +#define GT_HINTRMASK (0xc9c >> 2) +#define GT_PCI0_HICMASK (0xca4 >> 2) +#define GT_PCI1_SERR1MASK (0xca8 >> 2) #define PCI_MAPPING_ENTRY(regname) \ hwaddr regname ##_start; \ @@ -248,27 +243,34 @@ typedef struct GT64120State { } GT64120State; /* Adjust range to avoid touching space which isn't mappable via PCI */ -/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 - 0x1fc00000 - 0x1fd00000 */ -static void check_reserved_space (hwaddr *start, - hwaddr *length) +/* + * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 + * 0x1fc00000 - 0x1fd00000 + */ +static void check_reserved_space(hwaddr *start, hwaddr *length) { hwaddr begin = *start; hwaddr end = *start + *length; - if (end >= 0x1e000000LL && end < 0x1f100000LL) + if (end >= 0x1e000000LL && end < 0x1f100000LL) { end = 0x1e000000LL; - if (begin >= 0x1e000000LL && begin < 0x1f100000LL) + } + if (begin >= 0x1e000000LL && begin < 0x1f100000LL) { begin = 0x1f100000LL; - if (end >= 0x1fc00000LL && end < 0x1fd00000LL) + } + if (end >= 0x1fc00000LL && end < 0x1fd00000LL) { end = 0x1fc00000LL; - if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) + } + if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) { begin = 0x1fd00000LL; + } /* XXX: This is broken when a reserved range splits the requested range */ - if (end >= 0x1f100000LL && begin < 0x1e000000LL) + if (end >= 0x1f100000LL && begin < 0x1e000000LL) { end = 0x1e000000LL; - if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) + } + if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) { end = 0x1fc00000LL; + } *start = begin; *length = end - begin; @@ -286,9 +288,7 @@ static void gt64120_isd_mapping(GT64120State *s) check_reserved_space(&start, &length); length = 0x1000; /* Map new address */ - DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx - " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n", - s->ISD_length, s->ISD_start, length, start); + trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start); s->ISD_start = start; s->ISD_length = length; memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem); @@ -377,15 +377,16 @@ static const VMStateDescription vmstate_gt64120 = { } }; -static void gt64120_writel (void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void gt64120_writel(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t saddr; - if (!(s->regs[GT_CPU] & 0x00001000)) + if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); + } saddr = (addr & 0xfff) >> 2; switch (saddr) { @@ -458,12 +459,20 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* CPU Sync Barrier */ case GT_PCI0SYNC: case GT_PCI1SYNC: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* SDRAM and Device Address Decode */ @@ -502,7 +511,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_DEV_B3: case GT_DEV_BOOT: /* Not implemented */ - DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented device register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* ECC */ @@ -512,6 +524,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_ECC_CALC: case GT_ECC_ERRADDR: /* Read-only registers, do nothing */ + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Read-only register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* DMA Record */ @@ -535,23 +551,20 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_DMA1_CUR: case GT_DMA2_CUR: case GT_DMA3_CUR: - /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); - break; /* DMA Channel Control */ case GT_DMA0_CTRL: case GT_DMA1_CTRL: case GT_DMA2_CTRL: case GT_DMA3_CTRL: - /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); - break; /* DMA Arbiter */ case GT_DMA_ARB: /* Not implemented */ - DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented DMA register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* Timer/Counter */ @@ -561,7 +574,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_TC3: case GT_TC_CONTROL: /* Not implemented */ - DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2); + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented timer register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; /* PCI Internal */ @@ -602,6 +618,10 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_PCI1_CFGADDR: case GT_PCI1_CFGDATA: /* not implemented */ + qemu_log_mask(LOG_UNIMP, + "gt64120: Unimplemented timer register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; case GT_PCI0_CFGADDR: phb->config_reg = val & 0x80fffffc; @@ -620,19 +640,19 @@ static void gt64120_writel (void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); - DPRINTF("INTRCAUSE %" PRIx64 "\n", val); + trace_gt64120_write("INTRCAUSE", size << 1, val); break; case GT_INTRMASK: s->regs[saddr] = val & 0x3c3ffffe; - DPRINTF("INTRMASK %" PRIx64 "\n", val); + trace_gt64120_write("INTRMASK", size << 1, val); break; case GT_PCI0_ICMASK: s->regs[saddr] = val & 0x03fffffe; - DPRINTF("ICMASK %" PRIx64 "\n", val); + trace_gt64120_write("ICMASK", size << 1, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] = val & 0x0000003f; - DPRINTF("SERR0MASK %" PRIx64 "\n", val); + trace_gt64120_write("SERR0MASK", size << 1, val); break; /* Reserved when only PCI_0 is configured. */ @@ -650,19 +670,24 @@ static void gt64120_writel (void *opaque, hwaddr addr, case GT_SDRAM_B1: case GT_SDRAM_B2: case GT_SDRAM_B3: - /* We don't simulate electrical parameters of the SDRAM. - Accept, but ignore the values. */ + /* + * We don't simulate electrical parameters of the SDRAM. + * Accept, but ignore the values. + */ s->regs[saddr] = val; break; default: - DPRINTF ("Bad register offset 0x%x\n", (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Illegal register write " + "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + saddr << 2, size, size << 1, val); break; } } -static uint64_t gt64120_readl (void *opaque, - hwaddr addr, unsigned size) +static uint64_t gt64120_readl(void *opaque, + hwaddr addr, unsigned size) { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); @@ -674,8 +699,10 @@ static uint64_t gt64120_readl (void *opaque, /* CPU Configuration */ case GT_MULTI: - /* Only one GT64xxx is present on the CPU bus, return - the initial value */ + /* + * Only one GT64xxx is present on the CPU bus, return + * the initial value. + */ val = s->regs[saddr]; break; @@ -685,17 +712,18 @@ static uint64_t gt64120_readl (void *opaque, case GT_CPUERR_DATALO: case GT_CPUERR_DATAHI: case GT_CPUERR_PARITY: - /* Emulated memory has no error, always return the initial - values */ + /* Emulated memory has no error, always return the initial values. */ val = s->regs[saddr]; break; /* CPU Sync Barrier */ case GT_PCI0SYNC: case GT_PCI1SYNC: - /* Reading those register should empty all FIFO on the PCI - bus, which are not emulated. The return value should be - a random value that should be ignored. */ + /* + * Reading those register should empty all FIFO on the PCI + * bus, which are not emulated. The return value should be + * a random value that should be ignored. + */ val = 0xc000ffee; break; @@ -705,8 +733,7 @@ static uint64_t gt64120_readl (void *opaque, case GT_ECC_MEM: case GT_ECC_CALC: case GT_ECC_ERRADDR: - /* Emulated memory has no error, always return the initial - values */ + /* Emulated memory has no error, always return the initial values. */ val = s->regs[saddr]; break; @@ -785,8 +812,10 @@ static uint64_t gt64120_readl (void *opaque, case GT_SDRAM_B1: case GT_SDRAM_B2: case GT_SDRAM_B3: - /* We don't simulate electrical parameters of the SDRAM. - Just return the last written value. */ + /* + * We don't simulate electrical parameters of the SDRAM. + * Just return the last written value. + */ val = s->regs[saddr]; break; @@ -899,19 +928,19 @@ static uint64_t gt64120_readl (void *opaque, /* Interrupts */ case GT_INTRCAUSE: val = s->regs[saddr]; - DPRINTF("INTRCAUSE %x\n", val); + trace_gt64120_read("INTRCAUSE", size << 1, val); break; case GT_INTRMASK: val = s->regs[saddr]; - DPRINTF("INTRMASK %x\n", val); + trace_gt64120_read("INTRMASK", size << 1, val); break; case GT_PCI0_ICMASK: val = s->regs[saddr]; - DPRINTF("ICMASK %x\n", val); + trace_gt64120_read("ICMASK", size << 1, val); break; case GT_PCI0_SERR0MASK: val = s->regs[saddr]; - DPRINTF("SERR0MASK %x\n", val); + trace_gt64120_read("SERR0MASK", size << 1, val); break; /* Reserved when only PCI_0 is configured. */ @@ -926,12 +955,16 @@ static uint64_t gt64120_readl (void *opaque, default: val = s->regs[saddr]; - DPRINTF ("Bad register offset 0x%x\n", (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "gt64120: Illegal register read " + "reg:0x03%x size:%u value:0x%0*x\n", + saddr << 2, size, size << 1, val); break; } - if (!(s->regs[GT_CPU] & 0x00001000)) + if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); + } return val; } @@ -949,20 +982,20 @@ static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) slot = (pci_dev->devfn >> 3); switch (slot) { - /* PIIX4 USB */ - case 10: + /* PIIX4 USB */ + case 10: return 3; - /* AMD 79C973 Ethernet */ - case 11: + /* AMD 79C973 Ethernet */ + case 11: return 1; - /* Crystal 4281 Sound */ - case 12: + /* Crystal 4281 Sound */ + case 12: return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: + /* PCI slot 1 to 4 */ + case 18 ... 21: return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: + /* Unknown device, don't do any translation */ + default: return irq_num; } } @@ -980,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) /* XXX: optimize */ pic_irq = piix4_dev->config[0x60 + irq_num]; if (pic_irq < 16) { - /* The pic level is the logical OR of all the PCI irqs mapped - to it */ + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[0x60 + i]) + if (pic_irq == piix4_dev->config[0x60 + i]) { pic_level |= pci_irq_levels[i]; + } } qemu_set_irq(pic[pic_irq], pic_level); } @@ -1169,7 +1202,7 @@ PCIBus *gt64120_register(qemu_irq *pic) dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); d = GT64120_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); - memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX); + memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); phb->bus = pci_register_root_bus(dev, "pci", gt64120_pci_set_irq, gt64120_pci_map_irq, @@ -1178,7 +1211,8 @@ PCIBus *gt64120_register(qemu_irq *pic) get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); qdev_init_nofail(dev); - memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000); + memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, + "isd-mem", 0x1000); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); return phb->bus; diff --git a/hw/mips/trace-events b/hw/mips/trace-events new file mode 100644 index 0000000000..75d4c73f2e --- /dev/null +++ b/hw/mips/trace-events @@ -0,0 +1,4 @@ +# gt64xxx.c +gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64 +gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64 +gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 diff --git a/hw/net/xen_nic.c b/hw/net/xen_nic.c index 37cda8e4be..ffb3b5898d 100644 --- a/hw/net/xen_nic.c +++ b/hw/net/xen_nic.c @@ -30,7 +30,7 @@ #include "net/util.h" #include "hw/xen/xen-legacy-backend.h" -#include <xen/io/netif.h> +#include "hw/xen/interface/io/netif.h" /* ------------------------------------------------------------- */ diff --git a/hw/usb/xen-usb.c b/hw/usb/xen-usb.c index b20d0cfadf..dfbb418e77 100644 --- a/hw/usb/xen-usb.c +++ b/hw/usb/xen-usb.c @@ -32,8 +32,7 @@ #include "qapi/qmp/qdict.h" #include "qapi/qmp/qstring.h" -#include "hw/xen/io/ring.h" -#include <xen/io/usbif.h> +#include "hw/xen/interface/io/usbif.h" /* * Check for required support of usbif.h: USBIF_SHORT_NOT_OK was the last diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c index a4416d0bcf..7503eea9e9 100644 --- a/hw/xen/xen-bus.c +++ b/hw/xen/xen-bus.c @@ -924,23 +924,35 @@ done: } struct XenEventChannel { + QLIST_ENTRY(XenEventChannel) list; + AioContext *ctx; + xenevtchn_handle *xeh; evtchn_port_t local_port; XenEventHandler handler; void *opaque; - Notifier notifier; }; -static void event_notify(Notifier *n, void *data) +static bool xen_device_poll(void *opaque) +{ + XenEventChannel *channel = opaque; + + return channel->handler(channel->opaque); +} + +static void xen_device_event(void *opaque) { - XenEventChannel *channel = container_of(n, XenEventChannel, notifier); - unsigned long port = (unsigned long)data; + XenEventChannel *channel = opaque; + unsigned long port = xenevtchn_pending(channel->xeh); if (port == channel->local_port) { - channel->handler(channel->opaque); + xen_device_poll(channel); + + xenevtchn_unmask(channel->xeh, port); } } XenEventChannel *xen_device_bind_event_channel(XenDevice *xendev, + AioContext *ctx, unsigned int port, XenEventHandler handler, void *opaque, Error **errp) @@ -948,24 +960,40 @@ XenEventChannel *xen_device_bind_event_channel(XenDevice *xendev, XenEventChannel *channel = g_new0(XenEventChannel, 1); xenevtchn_port_or_error_t local_port; - local_port = xenevtchn_bind_interdomain(xendev->xeh, + channel->xeh = xenevtchn_open(NULL, 0); + if (!channel->xeh) { + error_setg_errno(errp, errno, "failed xenevtchn_open"); + goto fail; + } + + local_port = xenevtchn_bind_interdomain(channel->xeh, xendev->frontend_id, port); if (local_port < 0) { error_setg_errno(errp, errno, "xenevtchn_bind_interdomain failed"); - - g_free(channel); - return NULL; + goto fail; } channel->local_port = local_port; channel->handler = handler; channel->opaque = opaque; - channel->notifier.notify = event_notify; - notifier_list_add(&xendev->event_notifiers, &channel->notifier); + channel->ctx = ctx; + aio_set_fd_handler(channel->ctx, xenevtchn_fd(channel->xeh), true, + xen_device_event, NULL, xen_device_poll, channel); + + QLIST_INSERT_HEAD(&xendev->event_channels, channel, list); return channel; + +fail: + if (channel->xeh) { + xenevtchn_close(channel->xeh); + } + + g_free(channel); + + return NULL; } void xen_device_notify_event_channel(XenDevice *xendev, @@ -977,7 +1005,7 @@ void xen_device_notify_event_channel(XenDevice *xendev, return; } - if (xenevtchn_notify(xendev->xeh, channel->local_port) < 0) { + if (xenevtchn_notify(channel->xeh, channel->local_port) < 0) { error_setg_errno(errp, errno, "xenevtchn_notify failed"); } } @@ -991,12 +1019,16 @@ void xen_device_unbind_event_channel(XenDevice *xendev, return; } - notifier_remove(&channel->notifier); + QLIST_REMOVE(channel, list); + + aio_set_fd_handler(channel->ctx, xenevtchn_fd(channel->xeh), true, + NULL, NULL, NULL, NULL); - if (xenevtchn_unbind(xendev->xeh, channel->local_port) < 0) { + if (xenevtchn_unbind(channel->xeh, channel->local_port) < 0) { error_setg_errno(errp, errno, "xenevtchn_unbind failed"); } + xenevtchn_close(channel->xeh); g_free(channel); } @@ -1005,6 +1037,7 @@ static void xen_device_unrealize(DeviceState *dev, Error **errp) XenDevice *xendev = XEN_DEVICE(dev); XenDeviceClass *xendev_class = XEN_DEVICE_GET_CLASS(xendev); const char *type = object_get_typename(OBJECT(xendev)); + XenEventChannel *channel, *next; if (!xendev->name) { return; @@ -1021,15 +1054,14 @@ static void xen_device_unrealize(DeviceState *dev, Error **errp) xendev_class->unrealize(xendev, errp); } + /* Make sure all event channels are cleaned up */ + QLIST_FOREACH_SAFE(channel, &xendev->event_channels, list, next) { + xen_device_unbind_event_channel(xendev, channel, NULL); + } + xen_device_frontend_destroy(xendev); xen_device_backend_destroy(xendev); - if (xendev->xeh) { - qemu_set_fd_handler(xenevtchn_fd(xendev->xeh), NULL, NULL, NULL); - xenevtchn_close(xendev->xeh); - xendev->xeh = NULL; - } - if (xendev->xgth) { xengnttab_close(xendev->xgth); xendev->xgth = NULL; @@ -1046,16 +1078,6 @@ static void xen_device_exit(Notifier *n, void *data) xen_device_unrealize(DEVICE(xendev), &error_abort); } -static void xen_device_event(void *opaque) -{ - XenDevice *xendev = opaque; - unsigned long port = xenevtchn_pending(xendev->xeh); - - notifier_list_notify(&xendev->event_notifiers, (void *)port); - - xenevtchn_unmask(xendev->xeh, port); -} - static void xen_device_realize(DeviceState *dev, Error **errp) { XenDevice *xendev = XEN_DEVICE(dev); @@ -1096,16 +1118,6 @@ static void xen_device_realize(DeviceState *dev, Error **errp) xendev->feature_grant_copy = (xengnttab_grant_copy(xendev->xgth, 0, NULL) == 0); - xendev->xeh = xenevtchn_open(NULL, 0); - if (!xendev->xeh) { - error_setg_errno(errp, errno, "failed xenevtchn_open"); - goto unrealize; - } - - notifier_list_init(&xendev->event_notifiers); - qemu_set_fd_handler(xenevtchn_fd(xendev->xeh), xen_device_event, NULL, - xendev); - xen_device_backend_create(xendev, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c index 36fd1e9b09..3715c94fa6 100644 --- a/hw/xen/xen-legacy-backend.c +++ b/hw/xen/xen-legacy-backend.c @@ -34,8 +34,6 @@ #include "hw/xen/xen_pvdev.h" #include "monitor/qdev.h" -#include <xen/grant_table.h> - DeviceState *xen_sysdev; BusState *xen_sysbus; |