diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/irq.c | 17 | ||||
| -rw-r--r-- | hw/irq.h | 5 | ||||
| -rw-r--r-- | hw/mc146818rtc.c | 33 | ||||
| -rw-r--r-- | hw/mc146818rtc.h | 3 | ||||
| -rw-r--r-- | hw/mc146818rtc_regs.h | 62 | ||||
| -rw-r--r-- | hw/milkymist-sysctl.c | 26 | ||||
| -rw-r--r-- | hw/milkymist-vgafb.c | 5 | ||||
| -rw-r--r-- | hw/omap1.c | 10 | ||||
| -rw-r--r-- | hw/pc_piix.c | 3 | ||||
| -rw-r--r-- | hw/pl031.c | 75 | ||||
| -rw-r--r-- | hw/pxa2xx.c | 28 | ||||
| -rw-r--r-- | hw/serial.c | 5 | ||||
| -rw-r--r-- | hw/strongarm.c | 10 | ||||
| -rw-r--r-- | hw/twl92230.c | 9 | ||||
| -rw-r--r-- | hw/xen_console.c | 3 | ||||
| -rw-r--r-- | hw/xen_disk.c | 11 |
16 files changed, 200 insertions, 105 deletions
diff --git a/hw/irq.c b/hw/irq.c index 62f766eb6f..d413a0b235 100644 --- a/hw/irq.c +++ b/hw/irq.c @@ -104,3 +104,20 @@ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n) { return qemu_allocate_irqs(proxy_irq_handler, target, n); } + +void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) +{ + int i; + qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n); + for (i = 0; i < n; i++) { + *old_irqs[i] = *gpio_in[i]; + gpio_in[i]->handler = handler; + gpio_in[i]->opaque = old_irqs; + } +} + +void qemu_irq_intercept_out(qemu_irq **gpio_out, qemu_irq_handler handler, int n) +{ + qemu_irq *old_irqs = *gpio_out; + *gpio_out = qemu_allocate_irqs(handler, old_irqs, n); +} diff --git a/hw/irq.h b/hw/irq.h index 64da2fd601..56c55f0c46 100644 --- a/hw/irq.h +++ b/hw/irq.h @@ -38,4 +38,9 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); */ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n); +/* For internal use in qtest. Similar to qemu_irq_split, but operating + on an existing vector of qemu_irq. */ +void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); +void qemu_irq_intercept_out(qemu_irq **gpio_out, qemu_irq_handler handler, int n); + #endif diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 2b59c36ee6..9c64e0ae25 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -47,39 +47,6 @@ #define RTC_REINJECT_ON_ACK_COUNT 20 -#define RTC_SECONDS 0 -#define RTC_SECONDS_ALARM 1 -#define RTC_MINUTES 2 -#define RTC_MINUTES_ALARM 3 -#define RTC_HOURS 4 -#define RTC_HOURS_ALARM 5 -#define RTC_ALARM_DONT_CARE 0xC0 - -#define RTC_DAY_OF_WEEK 6 -#define RTC_DAY_OF_MONTH 7 -#define RTC_MONTH 8 -#define RTC_YEAR 9 - -#define RTC_REG_A 10 -#define RTC_REG_B 11 -#define RTC_REG_C 12 -#define RTC_REG_D 13 - -#define REG_A_UIP 0x80 - -#define REG_B_SET 0x80 -#define REG_B_PIE 0x40 -#define REG_B_AIE 0x20 -#define REG_B_UIE 0x10 -#define REG_B_SQWE 0x08 -#define REG_B_DM 0x04 -#define REG_B_24H 0x02 - -#define REG_C_UF 0x10 -#define REG_C_IRQF 0x80 -#define REG_C_PF 0x40 -#define REG_C_AF 0x20 - typedef struct RTCState { ISADevice dev; MemoryRegion io; diff --git a/hw/mc146818rtc.h b/hw/mc146818rtc.h index f1199300a4..f286b6a12a 100644 --- a/hw/mc146818rtc.h +++ b/hw/mc146818rtc.h @@ -2,8 +2,7 @@ #define MC146818RTC_H #include "isa.h" - -#define RTC_ISA_IRQ 8 +#include "mc146818rtc_regs.h" ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq); void rtc_set_memory(ISADevice *dev, int addr, int val); diff --git a/hw/mc146818rtc_regs.h b/hw/mc146818rtc_regs.h new file mode 100644 index 0000000000..3ab37709f0 --- /dev/null +++ b/hw/mc146818rtc_regs.h @@ -0,0 +1,62 @@ +/* + * QEMU MC146818 RTC emulation + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef RTC_REGS_H +#define RTC_REGS_H + +#define RTC_ISA_IRQ 8 + +#define RTC_SECONDS 0 +#define RTC_SECONDS_ALARM 1 +#define RTC_MINUTES 2 +#define RTC_MINUTES_ALARM 3 +#define RTC_HOURS 4 +#define RTC_HOURS_ALARM 5 +#define RTC_ALARM_DONT_CARE 0xC0 + +#define RTC_DAY_OF_WEEK 6 +#define RTC_DAY_OF_MONTH 7 +#define RTC_MONTH 8 +#define RTC_YEAR 9 + +#define RTC_REG_A 10 +#define RTC_REG_B 11 +#define RTC_REG_C 12 +#define RTC_REG_D 13 + +#define REG_A_UIP 0x80 + +#define REG_B_SET 0x80 +#define REG_B_PIE 0x40 +#define REG_B_AIE 0x20 +#define REG_B_UIE 0x10 +#define REG_B_SQWE 0x08 +#define REG_B_DM 0x04 +#define REG_B_24H 0x02 + +#define REG_C_UF 0x10 +#define REG_C_IRQF 0x80 +#define REG_C_PF 0x40 +#define REG_C_AF 0x20 + +#endif diff --git a/hw/milkymist-sysctl.c b/hw/milkymist-sysctl.c index a88548e0aa..8878d2bd17 100644 --- a/hw/milkymist-sysctl.c +++ b/hw/milkymist-sysctl.c @@ -1,7 +1,7 @@ /* * QEMU model of the Milkymist System Controller. * - * Copyright (c) 2010 Michael Walle <michael@walle.cc> + * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc> * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -39,20 +39,19 @@ enum { }; enum { - R_GPIO_IN = 0, + R_GPIO_IN = 0, R_GPIO_OUT, R_GPIO_INTEN, - R_RESERVED0, - R_TIMER0_CONTROL, + R_TIMER0_CONTROL = 4, R_TIMER0_COMPARE, R_TIMER0_COUNTER, - R_RESERVED1, - R_TIMER1_CONTROL, + R_TIMER1_CONTROL = 8, R_TIMER1_COMPARE, R_TIMER1_COUNTER, - R_RESERVED2, - R_RESERVED3, - R_ICAP, + R_ICAP = 16, + R_DBG_SCRATCHPAD = 20, + R_DBG_WRITE_LOCK, + R_CLK_FREQUENCY = 29, R_CAPABILITIES, R_SYSTEM_ID, R_MAX @@ -116,6 +115,9 @@ static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr, case R_TIMER1_CONTROL: case R_TIMER1_COMPARE: case R_ICAP: + case R_DBG_SCRATCHPAD: + case R_DBG_WRITE_LOCK: + case R_CLK_FREQUENCY: case R_CAPABILITIES: case R_SYSTEM_ID: r = s->regs[addr]; @@ -145,6 +147,7 @@ static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value, case R_GPIO_INTEN: case R_TIMER0_COUNTER: case R_TIMER1_COUNTER: + case R_DBG_SCRATCHPAD: s->regs[addr] = value; break; case R_TIMER0_COMPARE: @@ -182,11 +185,15 @@ static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value, case R_ICAP: sysctl_icap_write(s, value); break; + case R_DBG_WRITE_LOCK: + s->regs[addr] = 1; + break; case R_SYSTEM_ID: qemu_system_reset_request(); break; case R_GPIO_IN: + case R_CLK_FREQUENCY: case R_CAPABILITIES: error_report("milkymist_sysctl: write to read-only register 0x" TARGET_FMT_plx, addr << 2); @@ -253,6 +260,7 @@ static void milkymist_sysctl_reset(DeviceState *d) /* defaults */ s->regs[R_ICAP] = ICAP_READY; s->regs[R_SYSTEM_ID] = s->systemid; + s->regs[R_CLK_FREQUENCY] = s->freq_hz; s->regs[R_CAPABILITIES] = s->capabilities; s->regs[R_GPIO_IN] = s->strappings; } diff --git a/hw/milkymist-vgafb.c b/hw/milkymist-vgafb.c index 69afd72d8a..cd4365d64b 100644 --- a/hw/milkymist-vgafb.c +++ b/hw/milkymist-vgafb.c @@ -2,7 +2,7 @@ /* * QEMU model of the Milkymist VGA framebuffer. * - * Copyright (c) 2010 Michael Walle <michael@walle.cc> + * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc> * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -54,6 +54,7 @@ enum { R_BASEADDRESS, R_BASEADDRESS_ACT, R_BURST_COUNT, + R_DDC, R_SOURCE_CLOCK, R_MAX }; @@ -173,6 +174,7 @@ static uint64_t vgafb_read(void *opaque, target_phys_addr_t addr, case R_VSCAN: case R_BASEADDRESS: case R_BURST_COUNT: + case R_DDC: case R_SOURCE_CLOCK: r = s->regs[addr]; break; @@ -211,6 +213,7 @@ static void vgafb_write(void *opaque, target_phys_addr_t addr, uint64_t value, case R_VSYNC_END: case R_VSCAN: case R_BURST_COUNT: + case R_DDC: case R_SOURCE_CLOCK: s->regs[addr] = value; break; diff --git a/hw/omap1.c b/hw/omap1.c index 2a341bfe7f..80d47f0b85 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -2888,7 +2888,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s) s->pm_am = 0; s->auto_comp = 0; s->round = 0; - s->tick = qemu_get_clock_ms(rt_clock); + s->tick = qemu_get_clock_ms(rtc_clock); memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); s->alarm_tm.tm_mday = 0x01; s->status = 1 << 7; @@ -2909,7 +2909,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, s->irq = timerirq; s->alarm = alarmirq; - s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s); + s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s); omap_rtc_reset(s); @@ -3497,9 +3497,9 @@ static void omap_lpg_tick(void *opaque) struct omap_lpg_s *s = opaque; if (s->cycle) - qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on); + qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->period - s->on); else - qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on); + qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->on); s->cycle = !s->cycle; printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); @@ -3617,7 +3617,7 @@ static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, struct omap_lpg_s *s = (struct omap_lpg_s *) g_malloc0(sizeof(struct omap_lpg_s)); - s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s); + s->tm = qemu_new_timer_ms(vm_clock, omap_lpg_tick, s); omap_lpg_reset(s); diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 3f99f9a7c2..ec5118f848 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -107,6 +107,9 @@ static void ioapic_init(GSIState *gsi_state) } else { dev = qdev_create(NULL, "ioapic"); } + /* FIXME: this should be under the piix3. */ + object_property_add_child(object_resolve_path("i440fx", NULL), + "ioapic", OBJECT(dev), NULL); qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); diff --git a/hw/pl031.c b/hw/pl031.c index 69abc4f345..9602664da6 100644 --- a/hw/pl031.c +++ b/hw/pl031.c @@ -13,6 +13,7 @@ #include "sysbus.h" #include "qemu-timer.h" +#include "sysemu.h" //#define DEBUG_PL031 @@ -38,6 +39,11 @@ typedef struct { QEMUTimer *timer; qemu_irq irq; + /* Needed to preserve the tick_count across migration, even if the + * absolute value of the rtc_clock is different on the source and + * destination. + */ + uint32_t tick_offset_vmstate; uint32_t tick_offset; uint32_t mr; @@ -47,21 +53,6 @@ typedef struct { uint32_t is; } pl031_state; -static const VMStateDescription vmstate_pl031 = { - .name = "pl031", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32(tick_offset, pl031_state), - VMSTATE_UINT32(mr, pl031_state), - VMSTATE_UINT32(lr, pl031_state), - VMSTATE_UINT32(cr, pl031_state), - VMSTATE_UINT32(im, pl031_state), - VMSTATE_UINT32(is, pl031_state), - VMSTATE_END_OF_LIST() - } -}; - static const unsigned char pl031_id[] = { 0x31, 0x10, 0x14, 0x00, /* Device ID */ 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ @@ -83,27 +74,23 @@ static void pl031_interrupt(void * opaque) static uint32_t pl031_get_count(pl031_state *s) { - /* This assumes qemu_get_clock_ns returns the time since the machine was - created. */ - return s->tick_offset + qemu_get_clock_ns(vm_clock) / get_ticks_per_sec(); + int64_t now = qemu_get_clock_ns(rtc_clock); + return s->tick_offset + now / get_ticks_per_sec(); } static void pl031_set_alarm(pl031_state *s) { - int64_t now; uint32_t ticks; - now = qemu_get_clock_ns(vm_clock); - ticks = s->tick_offset + now / get_ticks_per_sec(); - /* The timer wraps around. This subtraction also wraps in the same way, and gives correct results when alarm < now_ticks. */ - ticks = s->mr - ticks; + ticks = s->mr - pl031_get_count(s); DPRINTF("Alarm set in %ud ticks\n", ticks); if (ticks == 0) { qemu_del_timer(s->timer); pl031_interrupt(s); } else { + int64_t now = qemu_get_clock_ns(rtc_clock); qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec()); } } @@ -205,14 +192,50 @@ static int pl031_init(SysBusDevice *dev) sysbus_init_mmio(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); - /* ??? We assume vm_clock is zero at this point. */ qemu_get_timedate(&tm, 0); - s->tick_offset = mktimegm(&tm); + s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec(); + + s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s); + return 0; +} + +static void pl031_pre_save(void *opaque) +{ + pl031_state *s = opaque; + + /* tick_offset is base_time - rtc_clock base time. Instead, we want to + * store the base time relative to the vm_clock for backwards-compatibility. */ + int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); + s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec(); +} + +static int pl031_post_load(void *opaque, int version_id) +{ + pl031_state *s = opaque; - s->timer = qemu_new_timer_ns(vm_clock, pl031_interrupt, s); + int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock); + s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec(); + pl031_set_alarm(s); return 0; } +static const VMStateDescription vmstate_pl031 = { + .name = "pl031", + .version_id = 1, + .minimum_version_id = 1, + .pre_save = pl031_pre_save, + .post_load = pl031_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32(tick_offset_vmstate, pl031_state), + VMSTATE_UINT32(mr, pl031_state), + VMSTATE_UINT32(lr, pl031_state), + VMSTATE_UINT32(cr, pl031_state), + VMSTATE_UINT32(im, pl031_state), + VMSTATE_UINT32(is, pl031_state), + VMSTATE_END_OF_LIST() + } +}; + static void pl031_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 1d5c35f174..ddaa846882 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -875,7 +875,7 @@ static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) { - int64_t rt = qemu_get_clock_ms(rt_clock); + int64_t rt = qemu_get_clock_ms(rtc_clock); s->last_rcnr += ((rt - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); s->last_rdcr += ((rt - s->last_hz) << 15) / @@ -885,7 +885,7 @@ static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) { - int64_t rt = qemu_get_clock_ms(rt_clock); + int64_t rt = qemu_get_clock_ms(rtc_clock); if (s->rtsr & (1 << 12)) s->last_swcr += (rt - s->last_sw) / 10; s->last_sw = rt; @@ -893,7 +893,7 @@ static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) { - int64_t rt = qemu_get_clock_ms(rt_clock); + int64_t rt = qemu_get_clock_ms(rtc_clock); if (s->rtsr & (1 << 15)) s->last_swcr += rt - s->last_pi; s->last_pi = rt; @@ -1019,16 +1019,16 @@ static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr, case PIAR: return s->piar; case RCNR: - return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) / + return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); case RDCR: - return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) / + return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); case RYCR: return s->last_rycr; case SWCR: if (s->rtsr & (1 << 12)) - return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10; + return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10; else return s->last_swcr; default: @@ -1168,14 +1168,14 @@ static int pxa2xx_rtc_init(SysBusDevice *dev) s->last_swcr = (tm.tm_hour << 19) | (tm.tm_min << 13) | (tm.tm_sec << 7); s->last_rtcpicr = 0; - s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock); - - s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s); - s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s); - s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s); - s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s); - s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s); - s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s); + s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock); + + s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); + s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); + s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); + s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); + s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); + s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); sysbus_init_irq(dev, &s->rtc_irq); diff --git a/hw/serial.c b/hw/serial.c index c0ee55d20c..a421d1e7bc 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -327,9 +327,12 @@ static void serial_xmit(void *opaque) s->tsr = fifo_get(s,XMIT_FIFO); if (!s->xmit_fifo.count) s->lsr |= UART_LSR_THRE; + } else if ((s->lsr & UART_LSR_THRE)) { + return; } else { s->tsr = s->thr; s->lsr |= UART_LSR_THRE; + s->lsr &= ~UART_LSR_TEMT; } } @@ -337,7 +340,7 @@ static void serial_xmit(void *opaque) /* in loopback mode, say that we just received a char */ serial_receive1(s, &s->tsr, 1); } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { - if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { + if ((s->tsr_retry >= 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { s->tsr_retry++; qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); return; diff --git a/hw/strongarm.c b/hw/strongarm.c index 4d5b60fd1f..1b15f399f1 100644 --- a/hw/strongarm.c +++ b/hw/strongarm.c @@ -255,7 +255,7 @@ static inline void strongarm_rtc_int_update(StrongARMRTCState *s) static void strongarm_rtc_hzupdate(StrongARMRTCState *s) { - int64_t rt = qemu_get_clock_ms(rt_clock); + int64_t rt = qemu_get_clock_ms(rtc_clock); s->last_rcnr += ((rt - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); s->last_hz = rt; @@ -308,7 +308,7 @@ static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr, return s->rtar; case RCNR: return s->last_rcnr + - ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) / + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); default: printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); @@ -374,10 +374,10 @@ static int strongarm_rtc_init(SysBusDevice *dev) qemu_get_timedate(&tm, 0); s->last_rcnr = (uint32_t) mktimegm(&tm); - s->last_hz = qemu_get_clock_ms(rt_clock); + s->last_hz = qemu_get_clock_ms(rtc_clock); - s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s); - s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s); + s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s); + s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s); sysbus_init_irq(dev, &s->rtc_irq); sysbus_init_irq(dev, &s->rtc_hz_irq); diff --git a/hw/twl92230.c b/hw/twl92230.c index 22da6f8001..0d70d8498d 100644 --- a/hw/twl92230.c +++ b/hw/twl92230.c @@ -22,6 +22,7 @@ #include "hw.h" #include "qemu-timer.h" #include "i2c.h" +#include "sysemu.h" #include "console.h" #define VERBOSE 1 @@ -71,14 +72,14 @@ static inline void menelaus_update(MenelausState *s) static inline void menelaus_rtc_start(MenelausState *s) { - s->rtc.next += qemu_get_clock_ms(rt_clock); + s->rtc.next += qemu_get_clock_ms(rtc_clock); qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); } static inline void menelaus_rtc_stop(MenelausState *s) { qemu_del_timer(s->rtc.hz_tm); - s->rtc.next -= qemu_get_clock_ms(rt_clock); + s->rtc.next -= qemu_get_clock_ms(rtc_clock); if (s->rtc.next < 1) s->rtc.next = 1; } @@ -781,7 +782,7 @@ static void menelaus_pre_save(void *opaque) { MenelausState *s = opaque; /* Should be <= 1000 */ - s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rt_clock); + s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rtc_clock); } static int menelaus_post_load(void *opaque, int version_id) @@ -842,7 +843,7 @@ static int twl92230_init(I2CSlave *i2c) { MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c); - s->rtc.hz_tm = qemu_new_timer_ms(rt_clock, menelaus_rtc_hz, s); + s->rtc.hz_tm = qemu_new_timer_ms(rtc_clock, menelaus_rtc_hz, s); /* Three output pins plus one interrupt pin. */ qdev_init_gpio_out(&i2c->qdev, s->out, 4); diff --git a/hw/xen_console.c b/hw/xen_console.c index edcb31ce66..3794b1972d 100644 --- a/hw/xen_console.c +++ b/hw/xen_console.c @@ -248,6 +248,9 @@ static void con_disconnect(struct XenDevice *xendev) { struct XenConsole *con = container_of(xendev, struct XenConsole, xendev); + if (!xendev->dev) { + return; + } if (con->chr) qemu_chr_add_handlers(con->chr, NULL, NULL, NULL, NULL); xen_be_unbind_evtchn(&con->xendev); diff --git a/hw/xen_disk.c b/hw/xen_disk.c index 68fa36a1cf..9719395b09 100644 --- a/hw/xen_disk.c +++ b/hw/xen_disk.c @@ -330,6 +330,9 @@ static void qemu_aio_complete(void *opaque, int ret) if (ioreq->aio_inflight > 0) { return; } + if (ioreq->postsync) { + bdrv_flush(ioreq->blkdev->bs); + } ioreq->status = ioreq->aio_errors ? BLKIF_RSP_ERROR : BLKIF_RSP_OKAY; ioreq_unmap(ioreq); @@ -376,9 +379,6 @@ static int ioreq_runio_qemu_aio(struct ioreq *ioreq) goto err; } - if (ioreq->postsync) { - bdrv_flush(blkdev->bs); /* FIXME: aio_flush() ??? */ - } qemu_aio_complete(ioreq, 0); return 0; @@ -584,10 +584,10 @@ static int blk_init(struct XenDevice *xendev) } /* read-only ? */ + qflags = BDRV_O_NOCACHE | BDRV_O_CACHE_WB | BDRV_O_NATIVE_AIO; if (strcmp(blkdev->mode, "w") == 0) { - qflags = BDRV_O_RDWR; + qflags |= BDRV_O_RDWR; } else { - qflags = 0; info |= VDISK_READONLY; } @@ -726,6 +726,7 @@ static void blk_disconnect(struct XenDevice *xendev) if (!blkdev->dinfo) { /* close/delete only if we created it ourself */ bdrv_close(blkdev->bs); + bdrv_detach_dev(blkdev->bs, blkdev); bdrv_delete(blkdev->bs); } blkdev->bs = NULL; |