diff options
Diffstat (limited to 'hw')
90 files changed, 739 insertions, 495 deletions
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 6ce038a453..761cc17ea9 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -3889,7 +3889,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, s->ih[0] = qdev_create(NULL, "omap-intc"); qdev_prop_set_uint32(s->ih[0], "size", 0x100); - qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); + omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); qdev_init_nofail(s->ih[0]); busdev = SYS_BUS_DEVICE(s->ih[0]); sysbus_connect_irq(busdev, 0, @@ -3899,7 +3899,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, sysbus_mmio_map(busdev, 0, 0xfffecb00); s->ih[1] = qdev_create(NULL, "omap-intc"); qdev_prop_set_uint32(s->ih[1], "size", 0x800); - qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); + omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck")); qdev_init_nofail(s->ih[1]); busdev = SYS_BUS_DEVICE(s->ih[1]); sysbus_connect_irq(busdev, 0, @@ -4012,7 +4012,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, s->gpio = qdev_create(NULL, "omap-gpio"); qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); - qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); + omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); qdev_init_nofail(s->gpio); sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); @@ -4030,7 +4030,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, s->i2c[0] = qdev_create(NULL, "omap_i2c"); qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); - qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); + omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); qdev_init_nofail(s->i2c[0]); busdev = SYS_BUS_DEVICE(s->i2c[0]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 457f152bac..e1c11de5ce 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -2308,8 +2308,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ s->ih[0] = qdev_create(NULL, "omap2-intc"); qdev_prop_set_uint8(s->ih[0], "revision", 0x21); - qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); - qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk")); + omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk")); + omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk")); qdev_init_nofail(s->ih[0]); busdev = SYS_BUS_DEVICE(s->ih[0]); sysbus_connect_irq(busdev, 0, @@ -2425,8 +2425,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, s->i2c[0] = qdev_create(NULL, "omap_i2c"); qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); - qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk")); - qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk")); + omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk")); + omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk")); qdev_init_nofail(s->i2c[0]); busdev = SYS_BUS_DEVICE(s->i2c[0]); sysbus_connect_irq(busdev, 0, @@ -2437,8 +2437,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, s->i2c[1] = qdev_create(NULL, "omap_i2c"); qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); - qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk")); - qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk")); + omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk")); + omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk")); qdev_init_nofail(s->i2c[1]); busdev = SYS_BUS_DEVICE(s->i2c[1]); sysbus_connect_irq(busdev, 0, @@ -2449,13 +2449,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, s->gpio = qdev_create(NULL, "omap2-gpio"); qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); - qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk")); - qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk")); - qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk")); - qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk")); - qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk")); + omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 1, omap_findclk(s, "gpio2_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 2, omap_findclk(s, "gpio3_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 3, omap_findclk(s, "gpio4_dbclk")); if (s->mpu_model == omap2430) { - qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4, + omap_findclk(s, "gpio5_dbclk")); } qdev_init_nofail(s->gpio); busdev = SYS_BUS_DEVICE(s->gpio); diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index cdafde2f76..950ff4239a 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -1955,7 +1955,7 @@ static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) pxa2xx_fir_update(s); } -static void pxa2xx_fir_event(void *opaque, int event) +static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 6bee034914..c6776e8479 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1093,7 +1093,7 @@ static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size) strongarm_uart_update_int_status(s); } -static void strongarm_uart_event(void *opaque, int event) +static void strongarm_uart_event(void *opaque, QEMUChrEvent event) { StrongARMUARTState *s = opaque; if (event == CHR_EVENT_BREAK) { diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 63da9bb619..98b383f90e 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -361,7 +361,7 @@ static gboolean vhost_user_blk_watch(GIOChannel *chan, GIOCondition cond, return true; } -static void vhost_user_blk_event(void *opaque, int event) +static void vhost_user_blk_event(void *opaque, QEMUChrEvent event) { DeviceState *dev = opaque; VirtIODevice *vdev = VIRTIO_DEVICE(dev); @@ -383,6 +383,11 @@ static void vhost_user_blk_event(void *opaque, int event) s->watch = 0; } break; + case CHR_EVENT_BREAK: + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; } } diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 0e315b2376..51791bd217 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -348,7 +348,7 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) } } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { CadenceUARTState *s = opaque; uint8_t buf = '\0'; diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 974a2619dd..033eba0a6a 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -131,7 +131,7 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) s->reg_rx = *buf; } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/char/escc.c b/hw/char/escc.c index 8f7bf322cb..c40c1d28f1 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -634,7 +634,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) serial_receive_byte(s, buf[0]); } -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { ESCCChannelState *s = opaque; if (event == CHR_EVENT_BREAK) diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index 15ac12ef22..f34f767c60 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -202,7 +202,7 @@ static int serial_can_receive(void *opaque) return sizeof(s->rx_fifo) - s->rx_fifo_len; } -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index d6b6b62366..7e5c5ce789 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -528,7 +528,7 @@ static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size) } -static void exynos4210_uart_event(void *opaque, int event) +static void exynos4210_uart_event(void *opaque, QEMUChrEvent event) { Exynos4210UartState *s = (Exynos4210UartState *)opaque; diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index fe3cbf41a3..8e59c3bc6e 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -155,7 +155,7 @@ static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) } } -static void grlib_apbuart_event(void *opaque, int event) +static void grlib_apbuart_event(void *opaque, QEMUChrEvent event) { trace_grlib_apbuart_event(event); } diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index fddde9b43d..d09c210709 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -323,7 +323,7 @@ static void imx_receive(void *opaque, const uint8_t *buf, int size) imx_put_data(opaque, *buf); } -static void imx_event(void *opaque, int event) +static void imx_event(void *opaque, QEMUChrEvent event) { if (event == CHR_EVENT_BREAK) { imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR); diff --git a/hw/char/ipoctal232.c b/hw/char/ipoctal232.c index 66c163ba26..80e9dff701 100644 --- a/hw/char/ipoctal232.c +++ b/hw/char/ipoctal232.c @@ -503,7 +503,7 @@ static void hostdev_receive(void *opaque, const uint8_t *buf, int size) } } -static void hostdev_event(void *opaque, int event) +static void hostdev_event(void *opaque, QEMUChrEvent event) { SCC2698Channel *ch = opaque; switch (event) { diff --git a/hw/char/lm32_juart.c b/hw/char/lm32_juart.c index e0b1bd6555..da9dd5668b 100644 --- a/hw/char/lm32_juart.c +++ b/hw/char/lm32_juart.c @@ -104,7 +104,7 @@ static int juart_can_rx(void *opaque) return !(s->jrx & JRX_FULL); } -static void juart_event(void *opaque, int event) +static void juart_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c index 32f29c44cf..8d7a475c91 100644 --- a/hw/char/lm32_uart.c +++ b/hw/char/lm32_uart.c @@ -235,7 +235,7 @@ static int uart_can_rx(void *opaque) return !(s->regs[R_LSR] & LSR_DR); } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index 58323baf43..2de3680b5d 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -256,7 +256,7 @@ static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data) mcf_uart_update(s); } -static void mcf_uart_event(void *opaque, int event) +static void mcf_uart_event(void *opaque, QEMUChrEvent event) { mcf_uart_state *s = (mcf_uart_state *)opaque; diff --git a/hw/char/milkymist-uart.c b/hw/char/milkymist-uart.c index c358ca07f3..1c7b61480e 100644 --- a/hw/char/milkymist-uart.c +++ b/hw/char/milkymist-uart.c @@ -180,7 +180,7 @@ static int uart_can_rx(void *opaque) return !(s->regs[R_STAT] & STAT_RX_EVT); } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index 2777afe366..b67fd21089 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -245,7 +245,7 @@ static int uart_can_receive(void *opaque) return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0; } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { NRF51UARTState *s = NRF51_UART(opaque); diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c index 13e4f43c4c..e8da933378 100644 --- a/hw/char/omap_uart.c +++ b/hw/char/omap_uart.c @@ -27,7 +27,7 @@ struct omap_uart_s { MemoryRegion iomem; hwaddr base; - SerialState *serial; /* TODO */ + SerialMM *serial; /* TODO */ struct omap_target_agent_s *ta; omap_clk fclk; qemu_irq irq; diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 84ad8ff9fb..23cd544cc5 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -280,7 +280,7 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size) pl011_put_fifo(opaque, *buf); } -static void pl011_event(void *opaque, int event) +static void pl011_event(void *opaque, QEMUChrEvent event) { if (event == CHR_EVENT_BREAK) pl011_put_fifo(opaque, 0x400); diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index 9e31c51bb6..db8644551e 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -73,9 +73,8 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp) } index++; - s->baudbase = 115200; isa_init_irq(isadev, &s->irq, isa->isairq); - serial_realize_core(s, errp); + object_property_set_bool(OBJECT(s), true, "realized", errp); qdev_set_legacy_instance_id(dev, isa->iobase, 3); memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8); @@ -111,10 +110,19 @@ static void serial_isa_class_initfn(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } +static void serial_isa_initfn(Object *o) +{ + ISASerialState *self = ISA_SERIAL(o); + + object_initialize_child(o, "serial", &self->state, sizeof(self->state), + TYPE_SERIAL, &error_abort, NULL); +} + static const TypeInfo serial_isa_info = { .name = TYPE_ISA_SERIAL, .parent = TYPE_ISA_DEVICE, .instance_size = sizeof(ISASerialState), + .instance_init = serial_isa_initfn, .class_init = serial_isa_class_initfn, }; diff --git a/hw/char/serial-pci-multi.c b/hw/char/serial-pci-multi.c index 5f13b5663b..e343a1235c 100644 --- a/hw/char/serial-pci-multi.c +++ b/hw/char/serial-pci-multi.c @@ -56,7 +56,7 @@ static void multi_serial_pci_exit(PCIDevice *dev) for (i = 0; i < pci->ports; i++) { s = pci->state + i; - serial_exit_core(s); + object_property_set_bool(OBJECT(s), false, "realized", NULL); memory_region_del_subregion(&pci->iobar, &s->io); g_free(pci->name[i]); } @@ -77,43 +77,43 @@ static void multi_serial_irq_mux(void *opaque, int n, int level) pci_set_irq(&pci->dev, pending); } +static size_t multi_serial_get_port_count(PCIDeviceClass *pc) +{ + switch (pc->device_id) { + case 0x0003: + return 2; + case 0x0004: + return 4; + } + + g_assert_not_reached(); +} + + static void multi_serial_pci_realize(PCIDevice *dev, Error **errp) { PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev); SerialState *s; Error *err = NULL; - int i, nr_ports = 0; - - switch (pc->device_id) { - case 0x0003: - nr_ports = 2; - break; - case 0x0004: - nr_ports = 4; - break; - } - assert(nr_ports > 0); - assert(nr_ports <= PCI_SERIAL_MAX_PORTS); + size_t i, nports = multi_serial_get_port_count(pc); pci->dev.config[PCI_CLASS_PROG] = pci->prog_if; pci->dev.config[PCI_INTERRUPT_PIN] = 0x01; - memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports); + memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports); pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar); - pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, - nr_ports); + pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, nports); - for (i = 0; i < nr_ports; i++) { + for (i = 0; i < nports; i++) { s = pci->state + i; - s->baudbase = 115200; - serial_realize_core(s, &err); + object_property_set_bool(OBJECT(s), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); multi_serial_pci_exit(dev); return; } s->irq = pci->irqs[i]; - pci->name[i] = g_strdup_printf("uart #%d", i + 1); + pci->name[i] = g_strdup_printf("uart #%zu", i + 1); memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, pci->name[i], 8); memory_region_add_subregion(&pci->iobar, 8 * i, &s->io); @@ -180,10 +180,24 @@ static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } +static void multi_serial_init(Object *o) +{ + PCIDevice *dev = PCI_DEVICE(o); + PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev); + size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev)); + + for (i = 0; i < nports; i++) { + object_initialize_child(o, "serial[*]", &pms->state[i], + sizeof(pms->state[i]), + TYPE_SERIAL, &error_abort, NULL); + } +} + static const TypeInfo multi_2x_serial_pci_info = { .name = "pci-serial-2x", .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCIMultiSerialState), + .instance_init = multi_serial_init, .class_init = multi_2x_serial_pci_class_initfn, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, @@ -195,6 +209,7 @@ static const TypeInfo multi_4x_serial_pci_info = { .name = "pci-serial-4x", .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCIMultiSerialState), + .instance_init = multi_serial_init, .class_init = multi_4x_serial_pci_class_initfn, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c index cb9b76e22b..b6a73c65a9 100644 --- a/hw/char/serial-pci.c +++ b/hw/char/serial-pci.c @@ -40,6 +40,8 @@ typedef struct PCISerialState { uint8_t prog_if; } PCISerialState; +#define TYPE_PCI_SERIAL "pci-serial" +#define PCI_SERIAL(s) OBJECT_CHECK(PCISerialState, (s), TYPE_PCI_SERIAL) static void serial_pci_realize(PCIDevice *dev, Error **errp) { @@ -47,8 +49,7 @@ static void serial_pci_realize(PCIDevice *dev, Error **errp) SerialState *s = &pci->state; Error *err = NULL; - s->baudbase = 115200; - serial_realize_core(s, &err); + object_property_set_bool(OBJECT(s), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; @@ -67,7 +68,7 @@ static void serial_pci_exit(PCIDevice *dev) PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev); SerialState *s = &pci->state; - serial_exit_core(s); + object_property_set_bool(OBJECT(s), false, "realized", NULL); qemu_free_irq(s->irq); } @@ -103,10 +104,19 @@ static void serial_pci_class_initfn(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_INPUT, dc->categories); } +static void serial_pci_init(Object *o) +{ + PCISerialState *ps = PCI_SERIAL(o); + + object_initialize_child(o, "serial", &ps->state, sizeof(ps->state), + TYPE_SERIAL, &error_abort, NULL); +} + static const TypeInfo serial_pci_info = { - .name = "pci-serial", + .name = TYPE_PCI_SERIAL, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCISerialState), + .instance_init = serial_pci_init, .class_init = serial_pci_class_initfn, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/char/serial.c b/hw/char/serial.c index b4aa250950..d167c43d40 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -34,6 +34,7 @@ #include "sysemu/runstate.h" #include "qemu/error-report.h" #include "trace.h" +#include "hw/qdev-properties.h" //#define DEBUG_SERIAL @@ -634,7 +635,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) serial_update_irq(s); } -static void serial_event(void *opaque, int event) +static void serial_event(void *opaque, QEMUChrEvent event) { SerialState *s = opaque; DPRINTF("event %x\n", event); @@ -933,8 +934,10 @@ static int serial_be_change(void *opaque) return 0; } -void serial_realize_core(SerialState *s, Error **errp) +static void serial_realize(DeviceState *dev, Error **errp) { + SerialState *s = SERIAL(dev); + s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); @@ -947,8 +950,10 @@ void serial_realize_core(SerialState *s, Error **errp) serial_reset(s); } -void serial_exit_core(SerialState *s) +static void serial_unrealize(DeviceState *dev, Error **errp) { + SerialState *s = SERIAL(dev); + qemu_chr_fe_deinit(&s->chr, false); timer_del(s->modem_status_poll); @@ -980,40 +985,89 @@ const MemoryRegionOps serial_io_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -SerialState *serial_init(int base, qemu_irq irq, int baudbase, - Chardev *chr, MemoryRegion *system_io) +static void serial_io_realize(DeviceState *dev, Error **errp) { - SerialState *s; + SerialIO *sio = SERIAL_IO(dev); + SerialState *s = &sio->serial; + Error *local_err = NULL; + + object_property_set_bool(OBJECT(s), true, "realized", &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8); + sysbus_init_mmio(SYS_BUS_DEVICE(sio), &s->io); + sysbus_init_irq(SYS_BUS_DEVICE(sio), &s->irq); +} - s = g_malloc0(sizeof(SerialState)); +static void serial_io_class_init(ObjectClass *klass, void* data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); - s->irq = irq; - s->baudbase = baudbase; - qemu_chr_fe_init(&s->chr, chr, &error_abort); - serial_realize_core(s, &error_fatal); + dc->realize = serial_io_realize; + /* No dc->vmsd: class has no migratable state */ +} - vmstate_register(NULL, base, &vmstate_serial, s); +static void serial_io_instance_init(Object *o) +{ + SerialIO *sio = SERIAL_IO(o); - memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8); - memory_region_add_subregion(system_io, base, &s->io); + object_initialize_child(o, "serial", &sio->serial, sizeof(sio->serial), + TYPE_SERIAL, &error_abort, NULL); - return s; + qdev_alias_all_properties(DEVICE(&sio->serial), o); } + +static const TypeInfo serial_io_info = { + .name = TYPE_SERIAL_IO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SerialIO), + .instance_init = serial_io_instance_init, + .class_init = serial_io_class_init, +}; + +static Property serial_properties[] = { + DEFINE_PROP_CHR("chardev", SerialState, chr), + DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200), + DEFINE_PROP_END_OF_LIST(), +}; + +static void serial_class_init(ObjectClass *klass, void* data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + /* internal device for serialio/serialmm, not user-creatable */ + dc->user_creatable = false; + dc->realize = serial_realize; + dc->unrealize = serial_unrealize; + dc->vmsd = &vmstate_serial; + dc->props = serial_properties; +} + +static const TypeInfo serial_info = { + .name = TYPE_SERIAL, + .parent = TYPE_DEVICE, + .instance_size = sizeof(SerialState), + .class_init = serial_class_init, +}; + /* Memory mapped interface */ static uint64_t serial_mm_read(void *opaque, hwaddr addr, unsigned size) { - SerialState *s = opaque; - return serial_ioport_read(s, addr >> s->it_shift, 1); + SerialMM *s = SERIAL_MM(opaque); + return serial_ioport_read(&s->serial, addr >> s->regshift, 1); } static void serial_mm_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - SerialState *s = opaque; + SerialMM *s = SERIAL_MM(opaque); value &= 255; - serial_ioport_write(s, addr >> s->it_shift, value, 1); + serial_ioport_write(&s->serial, addr >> s->regshift, value, 1); } static const MemoryRegionOps serial_mm_ops[3] = { @@ -1040,25 +1094,89 @@ static const MemoryRegionOps serial_mm_ops[3] = { }, }; -SerialState *serial_mm_init(MemoryRegion *address_space, - hwaddr base, int it_shift, - qemu_irq irq, int baudbase, - Chardev *chr, enum device_endian end) +static void serial_mm_realize(DeviceState *dev, Error **errp) { - SerialState *s; + SerialMM *smm = SERIAL_MM(dev); + SerialState *s = &smm->serial; + Error *local_err = NULL; - s = g_malloc0(sizeof(SerialState)); + object_property_set_bool(OBJECT(s), true, "realized", &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + memory_region_init_io(&s->io, NULL, &serial_mm_ops[smm->endianness], smm, + "serial", 8 << smm->regshift); + sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io); + sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq); +} + +SerialMM *serial_mm_init(MemoryRegion *address_space, + hwaddr base, int regshift, + qemu_irq irq, int baudbase, + Chardev *chr, enum device_endian end) +{ + SerialMM *smm = SERIAL_MM(qdev_create(NULL, TYPE_SERIAL_MM)); + MemoryRegion *mr; - s->it_shift = it_shift; - s->irq = irq; - s->baudbase = baudbase; - qemu_chr_fe_init(&s->chr, chr, &error_abort); + qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase); + qdev_prop_set_chr(DEVICE(smm), "chardev", chr); + qdev_set_legacy_instance_id(DEVICE(smm), base, 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", end); + qdev_init_nofail(DEVICE(smm)); - serial_realize_core(s, &error_fatal); - vmstate_register(NULL, base, &vmstate_serial, s); + sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq); + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0); + memory_region_add_subregion(address_space, base, mr); - memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s, - "serial", 8 << it_shift); - memory_region_add_subregion(address_space, base, &s->io); - return s; + return smm; } + +static void serial_mm_instance_init(Object *o) +{ + SerialMM *smm = SERIAL_MM(o); + + object_initialize_child(o, "serial", &smm->serial, sizeof(smm->serial), + TYPE_SERIAL, &error_abort, NULL); + + qdev_alias_all_properties(DEVICE(&smm->serial), o); +} + +static Property serial_mm_properties[] = { + /* + * Set the spacing between adjacent memory-mapped UART registers. + * Each register will be at (1 << regshift) bytes after the + * previous one. + */ + DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0), + DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + +static void serial_mm_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->props = serial_mm_properties; + dc->realize = serial_mm_realize; +} + +static const TypeInfo serial_mm_info = { + .name = TYPE_SERIAL_MM, + .parent = TYPE_SYS_BUS_DEVICE, + .class_init = serial_mm_class_init, + .instance_init = serial_mm_instance_init, + .instance_size = sizeof(SerialMM), + .class_init = serial_mm_class_init, +}; + +static void serial_register_types(void) +{ + type_register_static(&serial_info); + type_register_static(&serial_io_info); + type_register_static(&serial_mm_info); +} + +type_init(serial_register_types) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 07dc16be13..167f4d8cb9 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -358,7 +358,7 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) } } -static void sh_serial_event(void *opaque, int event) +static void sh_serial_event(void *opaque, QEMUChrEvent event) { sh_serial_state *s = opaque; if (event == CHR_EVENT_BREAK) diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c index 6859c1bcb2..f7aba12565 100644 --- a/hw/char/terminal3270.c +++ b/hw/char/terminal3270.c @@ -142,7 +142,7 @@ static void terminal_read(void *opaque, const uint8_t *buf, int size) } } -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { Terminal3270 *t = opaque; CcwDevice *ccw_dev = CCW_DEVICE(t); @@ -166,6 +166,11 @@ static void chr_event(void *opaque, int event) sch->curr_status.scsw.dstat = SCSW_DSTAT_DEVICE_END; css_conditional_io_interrupt(sch); break; + case CHR_EVENT_BREAK: + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; } } diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index c13649f1ef..a7d34fe0ed 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -145,7 +145,7 @@ static void chr_read(void *opaque, const uint8_t *buf, int size) virtio_serial_write(port, buf, size); } -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { VirtConsole *vcon = opaque; VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(vcon); @@ -162,6 +162,11 @@ static void chr_event(void *opaque, int event) } virtio_serial_close(port); break; + case CHR_EVENT_BREAK: + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; } } diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 2c47275068..aa6bf02e21 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -206,7 +206,7 @@ static int uart_can_rx(void *opaque) return s->rx_fifo_len < sizeof(s->rx_fifo); } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index ac28890e5a..6ca7697599 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -501,13 +501,6 @@ const PropertyInfo qdev_prop_string = { .set = set_string, }; -/* --- pointer --- */ - -/* Not a proper property, just for dirty hacks. TODO Remove it! */ -const PropertyInfo qdev_prop_ptr = { - .name = "ptr", -}; - /* --- mac address --- */ /* @@ -1165,17 +1158,6 @@ void qdev_prop_set_enum(DeviceState *dev, const char *name, int value) name, &error_abort); } -void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value) -{ - Property *prop; - void **ptr; - - prop = qdev_prop_find(dev, name); - assert(prop && prop->info == &qdev_prop_ptr); - ptr = qdev_get_prop_ptr(dev, prop); - *ptr = value; -} - static GPtrArray *global_props(void) { static GPtrArray *gp; diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 501228ba08..9f1753f5cf 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -394,11 +394,8 @@ static NamedGPIOList *qdev_get_named_gpio_list(DeviceState *dev, NamedGPIOList *ngl; QLIST_FOREACH(ngl, &dev->gpios, node) { - /* NULL is a valid and matchable name, otherwise do a normal - * strcmp match. - */ - if ((!ngl->name && !name) || - (name && ngl->name && strcmp(name, ngl->name) == 0)) { + /* NULL is a valid and matchable name. */ + if (g_strcmp0(name, ngl->name) == 0) { return ngl; } } @@ -739,14 +736,6 @@ void qdev_property_add_static(DeviceState *dev, Property *prop, if (prop->info->create) { prop->info->create(obj, prop, &local_err); } else { - /* - * TODO qdev_prop_ptr does not have getters or setters. It must - * go now that it can be replaced with links. The test should be - * removed along with it: all static properties are read/write. - */ - if (!prop->info->get && !prop->info->set) { - return; - } object_property_add(obj, prop->name, prop->info->name, prop->info->get, prop->info->set, prop->info->release, diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 9e69c83aed..08b0311c5f 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -250,38 +250,6 @@ DeviceState *sysbus_create_varargs(const char *name, return dev; } -DeviceState *sysbus_try_create_varargs(const char *name, - hwaddr addr, ...) -{ - DeviceState *dev; - SysBusDevice *s; - va_list va; - qemu_irq irq; - int n; - - dev = qdev_try_create(NULL, name); - if (!dev) { - return NULL; - } - s = SYS_BUS_DEVICE(dev); - qdev_init_nofail(dev); - if (addr != (hwaddr)-1) { - sysbus_mmio_map(s, 0, addr); - } - va_start(va, addr); - n = 0; - while (1) { - irq = va_arg(va, qemu_irq); - if (!irq) { - break; - } - sysbus_connect_irq(s, n, irq); - n++; - } - va_end(va); - return dev; -} - static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) { SysBusDevice *s = SYS_BUS_DEVICE(dev); diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index 940c7dd122..be7760476a 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -253,7 +253,6 @@ void axisdev88_init(MachineState *machine) const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; CRISCPU *cpu; - CPUCRISState *env; DeviceState *dev; SysBusDevice *s; DriveInfo *nand; @@ -267,7 +266,6 @@ void axisdev88_init(MachineState *machine) /* init CPUs */ cpu = CRIS_CPU(cpu_create(machine->cpu_type)); - env = &cpu->env; /* allocate RAM */ memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram", @@ -297,8 +295,6 @@ void axisdev88_init(MachineState *machine) dev = qdev_create(NULL, "etraxfs,pic"); - /* FIXME: Is there a proper way to signal vectors to the CPU core? */ - qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, 0x3001c000); diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 1f33c87e65..66a1bfbe60 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -1930,7 +1930,7 @@ typedef struct { SM501State state; uint32_t vram_size; uint32_t base; - void *chr_state; + SerialMM serial; } SM501SysBusState; static void sm501_realize_sysbus(DeviceState *dev, Error **errp) @@ -1938,6 +1938,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp) SM501SysBusState *s = SYSBUS_SM501(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); DeviceState *usb_dev; + MemoryRegion *mr; sm501_init(&s->state, dev, s->vram_size); if (get_local_mem_size(&s->state) != s->vram_size) { @@ -1958,17 +1959,15 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp) sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); /* bridge to serial emulation module */ - if (s->chr_state) { - serial_mm_init(&s->state.mmio_region, SM501_UART0, 2, - NULL, /* TODO : chain irq to IRL */ - 115200, s->chr_state, DEVICE_LITTLE_ENDIAN); - } + qdev_init_nofail(DEVICE(&s->serial)); + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial), 0); + memory_region_add_subregion(&s->state.mmio_region, SM501_UART0, mr); + /* TODO : chain irq to IRL */ } static Property sm501_sysbus_properties[] = { DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), - DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state), DEFINE_PROP_END_OF_LIST(), }; @@ -1999,9 +1998,20 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data) dc->props = sm501_sysbus_properties; dc->reset = sm501_reset_sysbus; dc->vmsd = &vmstate_sm501_sysbus; - /* Note: pointer property "chr-state" may remain null, thus - * no need for dc->user_creatable = false; - */ +} + +static void sm501_sysbus_init(Object *o) +{ + SM501SysBusState *sm501 = SYSBUS_SM501(o); + SerialMM *smm = &sm501->serial; + + sysbus_init_child_obj(o, "serial", smm, sizeof(SerialMM), TYPE_SERIAL_MM); + qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); + + object_property_add_alias(o, "chardev", + OBJECT(smm), "chardev", &error_abort); } static const TypeInfo sm501_sysbus_info = { @@ -2009,6 +2019,7 @@ static const TypeInfo sm501_sysbus_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SM501SysBusState), .class_init = sm501_sysbus_class_init, + .instance_init = sm501_sysbus_init, }; #define TYPE_PCI_SM501 "sm501" diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index 0e5bbcdc7f..3e4da0c47f 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -346,7 +346,7 @@ static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp) d = qdev_create(NULL, TYPE_LANCE); object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp); qdev_set_nic_properties(d, nd); - qdev_prop_set_ptr(d, "dma", dev); + object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp); qdev_init_nofail(d); } diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index 41e1aa798c..85c16897ae 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -40,10 +40,6 @@ struct omap_gpio_s { uint16_t pins; }; -#define TYPE_OMAP1_GPIO "omap-gpio" -#define OMAP1_GPIO(obj) \ - OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) - struct omap_gpif_s { SysBusDevice parent_obj; @@ -212,10 +208,6 @@ struct omap2_gpio_s { uint8_t delay; }; -#define TYPE_OMAP2_GPIO "omap2-gpio" -#define OMAP2_GPIO(obj) \ - OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) - struct omap2_gpif_s { SysBusDevice parent_obj; @@ -747,21 +739,13 @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp) } } -/* Using qdev pointer properties for the clocks is not ideal. - * qdev should support a generic means of defining a 'port' with - * an arbitrary interface for connecting two devices. Then we - * could reframe the omap clock API in terms of clock ports, - * and get some type safety. For now the best qdev provides is - * passing an arbitrary pointer. - * (It's not possible to pass in the string which is the clock - * name, because this device does not have the necessary information - * (ie the struct omap_mpu_state_s*) to do the clockname to pointer - * translation.) - */ +void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk) +{ + gpio->clk = clk; +} static Property omap_gpio_properties[] = { DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), - DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk), DEFINE_PROP_END_OF_LIST(), }; @@ -784,15 +768,19 @@ static const TypeInfo omap_gpio_info = { .class_init = omap_gpio_class_init, }; +void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk) +{ + gpio->iclk = clk; +} + +void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk) +{ + assert(i <= 5); + gpio->fclk[i] = clk; +} + static Property omap2_gpio_properties[] = { DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), - DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk), - DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]), - DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]), - DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]), - DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]), - DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]), - DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index 3ba965a58f..3ccbd5cc2c 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -28,10 +28,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" -#define TYPE_OMAP_I2C "omap_i2c" -#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C) - -typedef struct OMAPI2CState { +struct OMAPI2CState { SysBusDevice parent_obj; MemoryRegion iomem; @@ -56,7 +53,7 @@ typedef struct OMAPI2CState { uint8_t divider; uint8_t times[2]; uint16_t test; -} OMAPI2CState; +}; #define OMAP2_INTR_REV 0x34 #define OMAP2_GC_REV 0x34 @@ -504,10 +501,18 @@ static void omap_i2c_realize(DeviceState *dev, Error **errp) } } +void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk) +{ + i2c->iclk = clk; +} + +void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk) +{ + i2c->fclk = clk; +} + static Property omap_i2c_properties[] = { DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0), - DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk), - DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c index 54c86a0112..5adf3b15b5 100644 --- a/hw/i2c/smbus_eeprom.c +++ b/hw/i2c/smbus_eeprom.c @@ -44,7 +44,7 @@ typedef struct SMBusEEPROMDevice { SMBusDevice smbusdev; uint8_t data[SMBUS_EEPROM_SIZE]; - void *init_data; + uint8_t *init_data; uint8_t offset; bool accessed; } SMBusEEPROMDevice; @@ -129,14 +129,14 @@ static void smbus_eeprom_reset(DeviceState *dev) static void smbus_eeprom_realize(DeviceState *dev, Error **errp) { + SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev); + smbus_eeprom_reset(dev); + if (eeprom->init_data == NULL) { + error_setg(errp, "init_data cannot be NULL"); + } } -static Property smbus_eeprom_properties[] = { - DEFINE_PROP_PTR("data", SMBusEEPROMDevice, init_data), - DEFINE_PROP_END_OF_LIST(), -}; - static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -146,9 +146,8 @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) dc->reset = smbus_eeprom_reset; sc->receive_byte = eeprom_receive_byte; sc->write_data = eeprom_write_data; - dc->props = smbus_eeprom_properties; dc->vmsd = &vmstate_smbus_eeprom; - /* Reason: pointer property "data" */ + /* Reason: init_data */ dc->user_creatable = false; } @@ -172,7 +171,8 @@ void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM); qdev_prop_set_uint8(dev, "address", address); - qdev_prop_set_ptr(dev, "data", eeprom_buf); + /* FIXME: use an array of byte or block backend property? */ + SMBUS_EEPROM(dev)->init_data = eeprom_buf; qdev_init_nofail(dev); } diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 91cf5843b4..cdc851598c 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -95,7 +95,7 @@ config Q35 config MICROVM bool - imply SERIAL_ISA + select SERIAL_ISA # for serial_hds_isa_init() select ISA_BUS select APIC select IOAPIC diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 42014b06de..8054bc4147 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1156,9 +1156,9 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) vmmouse = NULL; } if (vmmouse) { - DeviceState *dev = DEVICE(vmmouse); - qdev_prop_set_ptr(dev, "ps2_mouse", i8042); - qdev_init_nofail(dev); + object_property_set_link(OBJECT(vmmouse), OBJECT(i8042), + "i8042", &error_abort); + qdev_init_nofail(DEVICE(vmmouse)); } port92 = isa_create_simple(isa_bus, TYPE_PORT92); @@ -1198,7 +1198,6 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, * when the HPET wants to take over. Thus we have to disable the latter. */ if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { - /* In order to set property, here not using sysbus_try_create_simple */ hpet = qdev_try_create(NULL, TYPE_HPET); if (hpet) { /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 diff --git a/hw/i386/vmmouse.c b/hw/i386/vmmouse.c index 41ad91ad53..c0c329f817 100644 --- a/hw/i386/vmmouse.c +++ b/hw/i386/vmmouse.c @@ -66,7 +66,7 @@ typedef struct VMMouseState uint16_t status; uint8_t absolute; QEMUPutMouseEntry *entry; - void *ps2_mouse; + ISAKBDState *i8042; } VMMouseState; static uint32_t vmmouse_get_status(VMMouseState *s) @@ -105,7 +105,7 @@ static void vmmouse_mouse_event(void *opaque, int x, int y, int dz, int buttons_ /* need to still generate PS2 events to notify driver to read from queue */ - i8042_isa_mouse_fake_event(s->ps2_mouse); + i8042_isa_mouse_fake_event(s->i8042); } static void vmmouse_remove_handler(VMMouseState *s) @@ -275,7 +275,7 @@ static void vmmouse_realizefn(DeviceState *dev, Error **errp) } static Property vmmouse_properties[] = { - DEFINE_PROP_PTR("ps2_mouse", VMMouseState, ps2_mouse), + DEFINE_PROP_LINK("i8042", VMMouseState, i8042, TYPE_I8042, ISAKBDState *), DEFINE_PROP_END_OF_LIST(), }; @@ -287,8 +287,6 @@ static void vmmouse_class_initfn(ObjectClass *klass, void *data) dc->reset = vmmouse_reset; dc->vmsd = &vmstate_vmmouse; dc->props = vmmouse_properties; - /* Reason: pointer property "ps2_mouse" */ - dc->user_creatable = false; } static const TypeInfo vmmouse_info = { diff --git a/hw/i386/x86-iommu-stub.c b/hw/i386/x86-iommu-stub.c index 03576cdccb..c5ba077f9d 100644 --- a/hw/i386/x86-iommu-stub.c +++ b/hw/i386/x86-iommu-stub.c @@ -32,3 +32,12 @@ X86IOMMUState *x86_iommu_get_default(void) return NULL; } +bool x86_iommu_ir_supported(X86IOMMUState *s) +{ + return false; +} + +IommuType x86_iommu_get_type(void) +{ + abort(); +} diff --git a/hw/i386/x86.c b/hw/i386/x86.c index d8bb5c2a96..9b9a4d5837 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -612,6 +612,7 @@ void x86_load_linux(X86MachineState *x86ms, vmode = strstr(kernel_cmdline, "vga="); if (vmode) { unsigned int video_mode; + const char *end; int ret; /* skip "vga=" */ vmode += 4; @@ -622,10 +623,9 @@ void x86_load_linux(X86MachineState *x86ms, } else if (!strncmp(vmode, "ask", 3)) { video_mode = 0xfffd; } else { - ret = qemu_strtoui(vmode, NULL, 0, &video_mode); - if (ret != 0) { - fprintf(stderr, "qemu: can't parse 'vga' parameter: %s\n", - strerror(-ret)); + ret = qemu_strtoui(vmode, &end, 0, &video_mode); + if (ret != 0 || (*end && *end != ' ')) { + fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); exit(1); } } diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 2f09f780ba..60a4130320 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -482,17 +482,15 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, #define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042) -typedef struct ISAKBDState { +struct ISAKBDState { ISADevice parent_obj; KBDState kbd; MemoryRegion io[2]; -} ISAKBDState; +}; -void i8042_isa_mouse_fake_event(void *opaque) +void i8042_isa_mouse_fake_event(ISAKBDState *isa) { - ISADevice *dev = opaque; - ISAKBDState *isa = I8042(dev); KBDState *s = &isa->kbd; ps2_mouse_fake_event(s->mouse); diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 10a680b53a..a189d6fedd 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -3,6 +3,7 @@ config HEATHROW_PIC config I8259 bool + select ISA_BUS config PL190 bool diff --git a/hw/intc/etraxfs_pic.c b/hw/intc/etraxfs_pic.c index 77f652acec..12988c7aa9 100644 --- a/hw/intc/etraxfs_pic.c +++ b/hw/intc/etraxfs_pic.c @@ -27,8 +27,6 @@ #include "qemu/module.h" #include "hw/irq.h" #include "hw/qdev-properties.h" -//#include "pc.h" -//#include "etraxfs.h" #define D(x) @@ -48,7 +46,6 @@ struct etrax_pic SysBusDevice parent_obj; MemoryRegion mmio; - void *interrupt_vector; qemu_irq parent_irq; qemu_irq parent_nmi; uint32_t regs[R_MAX]; @@ -79,11 +76,7 @@ static void pic_update(struct etrax_pic *fs) } } - if (fs->interrupt_vector) { - /* hack alert: ptr property */ - *(uint32_t*)(fs->interrupt_vector) = vector; - } - qemu_set_irq(fs->parent_irq, !!vector); + qemu_set_irq(fs->parent_irq, vector); } static uint64_t @@ -163,28 +156,11 @@ static void etraxfs_pic_init(Object *obj) sysbus_init_mmio(sbd, &s->mmio); } -static Property etraxfs_pic_properties[] = { - DEFINE_PROP_PTR("interrupt_vector", struct etrax_pic, interrupt_vector), - DEFINE_PROP_END_OF_LIST(), -}; - -static void etraxfs_pic_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->props = etraxfs_pic_properties; - /* - * Note: pointer property "interrupt_vector" may remain null, thus - * no need for dc->user_creatable = false; - */ -} - static const TypeInfo etraxfs_pic_info = { .name = TYPE_ETRAX_FS_PIC, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(struct etrax_pic), .instance_init = etraxfs_pic_init, - .class_init = etraxfs_pic_class_init, }; static void etraxfs_pic_register_types(void) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index bc78e1a14f..794c643af2 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -25,6 +25,7 @@ */ #include "qemu/osdep.h" +#include "hw/irq.h" #include "hw/sysbus.h" #include "cpu.h" @@ -58,10 +59,8 @@ typedef struct IRQMP { MemoryRegion iomem; - void *set_pil_in; - void *set_pil_in_opaque; - IRQMPState *state; + qemu_irq irq; } IRQMP; struct IRQMPState { @@ -82,7 +81,6 @@ static void grlib_irqmp_check_irqs(IRQMPState *state) uint32_t pend = 0; uint32_t level0 = 0; uint32_t level1 = 0; - set_pil_in_fn set_pil_in; assert(state != NULL); assert(state->parent != NULL); @@ -97,14 +95,8 @@ static void grlib_irqmp_check_irqs(IRQMPState *state) trace_grlib_irqmp_check_irqs(state->pending, state->force[0], state->mask[0], level1, level0); - set_pil_in = (set_pil_in_fn)state->parent->set_pil_in; - /* Trigger level1 interrupt first and level0 if there is no level1 */ - if (level1 != 0) { - set_pil_in(state->parent->set_pil_in_opaque, level1); - } else { - set_pil_in(state->parent->set_pil_in_opaque, level0); - } + qemu_set_irq(state->parent->irq, level1 ?: level0); } static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask) @@ -335,6 +327,7 @@ static void grlib_irqmp_init(Object *obj) IRQMP *irqmp = GRLIB_IRQMP(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); + qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1); memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp, "irqmp", IRQMP_REG_SIZE); @@ -343,31 +336,11 @@ static void grlib_irqmp_init(Object *obj) sysbus_init_mmio(dev, &irqmp->iomem); } -static void grlib_irqmp_realize(DeviceState *dev, Error **errp) -{ - IRQMP *irqmp = GRLIB_IRQMP(dev); - - /* Check parameters */ - if (irqmp->set_pil_in == NULL) { - error_setg(errp, "set_pil_in cannot be NULL."); - } -} - -static Property grlib_irqmp_properties[] = { - DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in), - DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque), - DEFINE_PROP_END_OF_LIST(), -}; - static void grlib_irqmp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = grlib_irqmp_reset; - dc->props = grlib_irqmp_properties; - /* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */ - dc->user_creatable = false; - dc->realize = grlib_irqmp_realize; } static const TypeInfo grlib_irqmp_info = { diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 854b709ca0..73bb1c2af4 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -38,10 +38,6 @@ struct omap_intr_handler_bank_s { unsigned char priority[32]; }; -#define TYPE_OMAP_INTC "common-omap-intc" -#define OMAP_INTC(obj) \ - OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC) - struct omap_intr_handler_s { SysBusDevice parent_obj; @@ -391,9 +387,18 @@ static void omap_intc_realize(DeviceState *dev, Error **errp) } } +void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk) +{ + intc->iclk = clk; +} + +void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk) +{ + intc->fclk = clk; +} + static Property omap_intc_properties[] = { DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100), - DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk), DEFINE_PROP_END_OF_LIST(), }; @@ -647,8 +652,6 @@ static void omap2_intc_realize(DeviceState *dev, Error **errp) static Property omap2_intc_properties[] = { DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s, revision, 0x21), - DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk), - DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index a0a69b98a7..715fca61ae 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -472,12 +472,8 @@ static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) { int pir = ppc_cpu_pir(cpu); - PnvChip *chip; - PnvXive *xive; - - chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); - assert(chip); - xive = &PNV9_CHIP(chip)->xive; + XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; + PnvXive *xive = PNV_XIVE(xptr); if (!pnv_xive_is_cpu_enabled(xive, cpu)) { xive_error(xive, "IC: CPU %x is not enabled", pir); @@ -1816,10 +1812,17 @@ static void pnv_xive_init(Object *obj) static void pnv_xive_realize(DeviceState *dev, Error **errp) { PnvXive *xive = PNV_XIVE(dev); + PnvXiveClass *pxc = PNV_XIVE_GET_CLASS(dev); XiveSource *xsrc = &xive->ipi_source; XiveENDSource *end_xsrc = &xive->end_source; Error *local_err = NULL; + pxc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + assert(xive->chip); /* @@ -1947,10 +1950,12 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); + PnvXiveClass *pxc = PNV_XIVE_CLASS(klass); xdc->dt_xscom = pnv_xive_dt_xscom; dc->desc = "PowerNV XIVE Interrupt Controller"; + device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize); dc->realize = pnv_xive_realize; dc->props = pnv_xive_properties; @@ -1971,6 +1976,7 @@ static const TypeInfo pnv_xive_info = { .instance_init = pnv_xive_init, .instance_size = sizeof(PnvXive), .class_init = pnv_xive_class_init, + .class_size = sizeof(PnvXiveClass), .interfaces = (InterfaceInfo[]) { { TYPE_PNV_XSCOM_INTERFACE }, { } diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 57305c56d7..7663123878 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -286,10 +286,17 @@ static void spapr_xive_instance_init(Object *obj) static void spapr_xive_realize(DeviceState *dev, Error **errp) { SpaprXive *xive = SPAPR_XIVE(dev); + SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive); XiveSource *xsrc = &xive->source; XiveENDSource *end_xsrc = &xive->end_source; Error *local_err = NULL; + sxc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + if (!xive->nr_irqs) { error_setg(errp, "Number of interrupt needs to be greater 0"); return; @@ -594,7 +601,7 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, Object *obj; SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); - obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp); if (!obj) { return -1; } @@ -760,10 +767,12 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); + SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass); dc->desc = "sPAPR XIVE Interrupt Controller"; dc->props = spapr_xive_properties; - dc->realize = spapr_xive_realize; + device_class_set_parent_realize(dc, spapr_xive_realize, + &sxc->parent_realize); dc->vmsd = &vmstate_spapr_xive; xrc->get_eas = spapr_xive_get_eas; @@ -794,6 +803,7 @@ static const TypeInfo spapr_xive_info = { .instance_init = spapr_xive_instance_init, .instance_size = sizeof(SpaprXive), .class_init = spapr_xive_class_init, + .class_size = sizeof(SpaprXiveClass), .interfaces = (InterfaceInfo[]) { { TYPE_SPAPR_INTC }, { } diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 32b2809210..edb7ee0e74 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -75,7 +75,7 @@ static void kvm_cpu_disable_all(void) void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp) { - SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive; + SpaprXive *xive = SPAPR_XIVE(tctx->xptr); uint64_t state[2]; int ret; @@ -97,7 +97,7 @@ void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp) void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp) { - SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive; + SpaprXive *xive = SPAPR_XIVE(tctx->xptr); uint64_t state[2] = { 0 }; int ret; @@ -152,8 +152,7 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp) void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) { - MachineState *ms = MACHINE(qdev_get_machine()); - SpaprXive *xive = SPAPR_MACHINE(ms)->xive; + SpaprXive *xive = SPAPR_XIVE(tctx->xptr); unsigned long vcpu_id; int ret; @@ -179,7 +178,7 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) vcpu_id, strerror(errno)); if (errno == ENOSPC) { error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n", - ms->smp.max_cpus); + MACHINE(qdev_get_machine())->smp.max_cpus); } error_propagate(errp, local_err); return; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index d4c6e21703..bc8019c4c9 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -654,6 +654,7 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp) Error *local_err = NULL; assert(tctx->cs); + assert(tctx->xptr); cpu = POWERPC_CPU(tctx->cs); env = &cpu->env; @@ -727,6 +728,8 @@ static const VMStateDescription vmstate_xive_tctx = { static Property xive_tctx_properties[] = { DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), + DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, + XivePresenter *), DEFINE_PROP_END_OF_LIST(), }; @@ -752,7 +755,7 @@ static const TypeInfo xive_tctx_info = { .class_init = xive_tctx_class_init, }; -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) +Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) { Error *local_err = NULL; Object *obj; @@ -761,6 +764,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); object_property_set_link(obj, cpu, "cpu", &error_abort); + object_property_set_link(obj, OBJECT(xptr), "presenter", &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; @@ -1378,6 +1382,13 @@ static int xive_router_get_block_id(XiveRouter *xrtr) return xrc->get_block_id(xrtr); } +static void xive_router_realize(DeviceState *dev, Error **errp) +{ + XiveRouter *xrtr = XIVE_ROUTER(dev); + + assert(xrtr->xfb); +} + /* * Encode the HW CAM line in the block group mode format : * @@ -1470,12 +1481,11 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, * * The parameters represent what is sent on the PowerBus */ -static bool xive_presenter_notify(uint8_t format, +static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) { - XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine()); XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; int count; @@ -1607,7 +1617,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, return; } - found = xive_presenter_notify(format, nvt_blk, nvt_idx, + found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, xive_get_field32(END_W7_F0_IGNORE, end.w7), priority, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); @@ -1714,12 +1724,21 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn) xive_get_field64(EAS_END_DATA, eas.w)); } +static Property xive_router_properties[] = { + DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, + TYPE_XIVE_FABRIC, XiveFabric *), + DEFINE_PROP_END_OF_LIST(), +}; + static void xive_router_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); dc->desc = "XIVE Router Engine"; + dc->props = xive_router_properties; + /* Parent is SysBusDeviceClass. No need to call its realize hook */ + dc->realize = xive_router_realize; xnc->notify = xive_router_notify; } @@ -1727,6 +1746,7 @@ static const TypeInfo xive_router_info = { .name = TYPE_XIVE_ROUTER, .parent = TYPE_SYS_BUS_DEVICE, .abstract = true, + .instance_size = sizeof(XiveRouter), .class_size = sizeof(XiveRouterClass), .class_init = xive_router_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index 87da9ff99c..16a4117ab0 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -87,10 +87,6 @@ typedef struct IPMIBmcExtern { bool send_reset; } IPMIBmcExtern; -static int can_receive(void *opaque); -static void receive(void *opaque, const uint8_t *buf, int size); -static void chr_event(void *opaque, int event); - static unsigned char ipmb_checksum(const unsigned char *data, int size, unsigned char start) { @@ -383,7 +379,7 @@ static void receive(void *opaque, const uint8_t *buf, int size) handle_hw_op(ibe, hw_op); } -static void chr_event(void *opaque, int event) +static void chr_event(void *opaque, QEMUChrEvent event) { IPMIBmcExtern *ibe = opaque; IPMIInterface *s = ibe->parent.intf; @@ -439,6 +435,12 @@ static void chr_event(void *opaque, int event) k->handle_rsp(s, ibe->outbuf[0], ibe->inbuf + 1, 3); } break; + + case CHR_EVENT_BREAK: + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; } } diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 0e5a08f993..12491ecde6 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -266,7 +266,8 @@ static void q800_init(MachineState *machine) qdev_set_nic_properties(dev, &nd_table[0]); qdev_prop_set_uint8(dev, "it_shift", 2); qdev_prop_set_bit(dev, "big_endian", true); - qdev_prop_set_ptr(dev, "dma_mr", get_system_memory()); + object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()), + "dma_mr", &error_abort); qdev_init_nofail(dev); sysbus = SYS_BUS_DEVICE(dev); sysbus_mmio_map(sysbus, 0, SONIC_BASE); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index ca7d813a52..0df3a7755a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -50,7 +50,7 @@ typedef struct { MachineState *mach; MIPSCPSState cps; - SerialState *uart; + SerialMM *uart; CharBackend lcd_display; char lcd_content[8]; @@ -98,7 +98,7 @@ enum boston_plat_reg { PLAT_SYS_CTL = 0x48, }; -static void boston_lcd_event(void *opaque, int event) +static void boston_lcd_event(void *opaque, QEMUChrEvent event) { BostonState *s = opaque; if (event == CHR_EVENT_OPENED && !s->lcd_inited) { diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 1660f86908..c49868d5da 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -106,7 +106,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", &err); if (saar_present) { - qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR); + s->itu.saar = &env->CP0_SAAR; } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err != NULL) { diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 291fd6c1b8..66fd4d867d 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -290,7 +290,8 @@ static void mips_jazz_init(MachineState *machine, dev = qdev_create(NULL, "dp8393x"); qdev_set_nic_properties(dev, nd); qdev_prop_set_uint8(dev, "it_shift", 2); - qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr); + object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr), + "dma_mr", &error_abort); qdev_init_nofail(dev); sysbus = SYS_BUS_DEVICE(dev); sysbus_mmio_map(sysbus, 0, 0x80001000); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 783cd99848..5aaeaa8d53 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -83,7 +83,7 @@ typedef struct { uint32_t i2csel; CharBackend display; char display_text[9]; - SerialState *uart; + SerialMM *uart; bool display_inited; } MaltaFPGAState; @@ -545,7 +545,7 @@ static void malta_fpga_reset(void *opaque) snprintf(s->display_text, 9, " "); } -static void malta_fgpa_display_event(void *opaque, int event) +static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) { MaltaFPGAState *s = opaque; diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index 282bbecb24..84c03dd035 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -40,6 +40,7 @@ #include "hw/loader.h" #include "elf.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "exec/address-spaces.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" @@ -219,9 +220,16 @@ mips_mipssim_init(MachineState *machine) * A single 16450 sits at offset 0x3f8. It is attached to * MIPS CPU INT2, which is interrupt 4. */ - if (serial_hd(0)) - serial_init(0x3f8, env->irq[4], 115200, serial_hd(0), - get_system_io()); + if (serial_hd(0)) { + DeviceState *dev = qdev_create(NULL, TYPE_SERIAL_IO); + + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + qdev_set_legacy_instance_id(dev, 0x3f8, 2); + qdev_init_nofail(dev); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); + sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); + } if (nd_table[0].used) /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index cecf0be59e..10b85bf751 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -244,6 +244,9 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = s->b; break; case VIA_REG_A: + qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake"); + /* fall through */ + case VIA_REG_ANH: val = s->a; break; case VIA_REG_DIRB: @@ -297,9 +300,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = s->ier | 0x80; break; default: - case VIA_REG_ANH: - val = s->anh; - break; + g_assert_not_reached(); } if (addr != VIA_REG_IFR || val != 0) { @@ -322,6 +323,9 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) mdc->portB_write(s); break; case VIA_REG_A: + qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake"); + /* fall through */ + case VIA_REG_ANH: s->a = (s->a & ~s->dira) | (val & s->dira); mdc->portA_write(s); break; @@ -395,9 +399,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; default: - case VIA_REG_ANH: - s->anh = val; - break; + g_assert_not_reached(); } } @@ -439,7 +441,6 @@ const VMStateDescription vmstate_mos6522 = { VMSTATE_UINT8(pcr, MOS6522State), VMSTATE_UINT8(ifr, MOS6522State), VMSTATE_UINT8(ier, MOS6522State), - VMSTATE_UINT8(anh, MOS6522State), VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, vmstate_mos6522_timer, MOS6522Timer), VMSTATE_END_OF_LIST() @@ -460,7 +461,6 @@ static void mos6522_reset(DeviceState *dev) s->ifr = 0; s->ier = 0; /* s->ier = T1_INT | SR_INT; */ - s->anh = 0; s->timers[0].frequency = s->frequency; s->timers[0].latch = 0xffff; diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 3856417d42..af6a11baf3 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -14,6 +14,7 @@ config EEPRO100_PCI bool default y if PCI_DEVICES depends on PCI + select NMC93XX_EEPROM config PCNET_PCI bool @@ -28,6 +29,7 @@ config TULIP bool default y if PCI_DEVICES depends on PCI + select NMC93XX_EEPROM config E1000_PCI bool diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 3d991af163..cdc2631c0c 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -175,7 +175,7 @@ typedef struct dp8393xState { int loopback_packet; /* Memory access */ - void *dma_mr; + MemoryRegion *dma_mr; AddressSpace as; } dp8393xState; @@ -948,7 +948,8 @@ static const VMStateDescription vmstate_dp8393x = { static Property dp8393x_properties[] = { DEFINE_NIC_PROPERTIES(dp8393xState, conf), - DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), + DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), DEFINE_PROP_END_OF_LIST(), @@ -963,8 +964,6 @@ static void dp8393x_class_init(ObjectClass *klass, void *data) dc->reset = dp8393x_reset; dc->vmsd = &vmstate_dp8393x; dc->props = dp8393x_properties; - /* Reason: dma_mr property can't be set */ - dc->user_creatable = false; } static const TypeInfo dp8393x_info = { diff --git a/hw/net/etraxfs_eth.c b/hw/net/etraxfs_eth.c index 4cfbf1135a..f30d963487 100644 --- a/hw/net/etraxfs_eth.c +++ b/hw/net/etraxfs_eth.c @@ -338,14 +338,8 @@ typedef struct ETRAXFSEthState uint8_t macaddr[2][6]; uint32_t regs[FS_ETH_MAX_REGS]; - union { - void *vdma_out; - struct etraxfs_dma_client *dma_out; - }; - union { - void *vdma_in; - struct etraxfs_dma_client *dma_in; - }; + struct etraxfs_dma_client *dma_out; + struct etraxfs_dma_client *dma_in; /* MDIO bus. */ struct qemu_mdio mdio_bus; @@ -635,8 +629,6 @@ static void etraxfs_eth_realize(DeviceState *dev, Error **errp) static Property etraxfs_eth_properties[] = { DEFINE_PROP_UINT32("phyaddr", ETRAXFSEthState, phyaddr, 1), - DEFINE_PROP_PTR("dma_out", ETRAXFSEthState, vdma_out), - DEFINE_PROP_PTR("dma_in", ETRAXFSEthState, vdma_in), DEFINE_NIC_PROPERTIES(ETRAXFSEthState, conf), DEFINE_PROP_END_OF_LIST(), }; @@ -648,10 +640,40 @@ static void etraxfs_eth_class_init(ObjectClass *klass, void *data) dc->realize = etraxfs_eth_realize; dc->reset = etraxfs_eth_reset; dc->props = etraxfs_eth_properties; - /* Reason: pointer properties "dma_out", "dma_in" */ + /* Reason: dma_out, dma_in are not user settable */ dc->user_creatable = false; } + +/* Instantiate an ETRAXFS Ethernet MAC. */ +DeviceState * +etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr, + struct etraxfs_dma_client *dma_out, + struct etraxfs_dma_client *dma_in) +{ + DeviceState *dev; + qemu_check_nic_model(nd, "fseth"); + + dev = qdev_create(NULL, "etraxfs-eth"); + qdev_set_nic_properties(dev, nd); + qdev_prop_set_uint32(dev, "phyaddr", phyaddr); + + /* + * TODO: QOM design, define a QOM interface for "I am an etraxfs + * DMA client" (which replaces the current 'struct + * etraxfs_dma_client' ad-hoc interface), implement it on the + * ethernet device, and then have QOM link properties on the DMA + * controller device so that you can pass the interface + * implementations to it. + */ + ETRAX_FS_ETH(dev)->dma_out = dma_out; + ETRAX_FS_ETH(dev)->dma_in = dma_in; + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + + return dev; +} + static const TypeInfo etraxfs_eth_info = { .name = TYPE_ETRAX_FS_ETH, .parent = TYPE_SYS_BUS_DEVICE, diff --git a/hw/net/lance.c b/hw/net/lance.c index 6631e2a4e0..4d96299041 100644 --- a/hw/net/lance.c +++ b/hw/net/lance.c @@ -138,7 +138,8 @@ static void lance_instance_init(Object *obj) } static Property lance_properties[] = { - DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque), + DEFINE_PROP_LINK("dma", SysBusPCNetState, state.dma_opaque, + TYPE_DEVICE, DeviceState *), DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), DEFINE_PROP_END_OF_LIST(), }; @@ -153,8 +154,6 @@ static void lance_class_init(ObjectClass *klass, void *data) dc->reset = lance_reset; dc->vmsd = &vmstate_lance; dc->props = lance_properties; - /* Reason: pointer property "dma" */ - dc->user_creatable = false; } static const TypeInfo lance_info = { diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c index 4723c30c79..d067d21e2c 100644 --- a/hw/net/pcnet-pci.c +++ b/hw/net/pcnet-pci.c @@ -231,7 +231,7 @@ static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp) s->irq = pci_allocate_irq(pci_dev); s->phys_mem_read = pci_physical_memory_read; s->phys_mem_write = pci_physical_memory_write; - s->dma_opaque = pci_dev; + s->dma_opaque = DEVICE(pci_dev); pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); } diff --git a/hw/net/pcnet.h b/hw/net/pcnet.h index 28d19a5c6f..f49b213c57 100644 --- a/hw/net/pcnet.h +++ b/hw/net/pcnet.h @@ -50,7 +50,7 @@ struct PCNetState_st { uint8_t *buf, int len, int do_bswap); void (*phys_mem_write)(void *dma_opaque, hwaddr addr, uint8_t *buf, int len, int do_bswap); - void *dma_opaque; + DeviceState *dma_opaque; int tx_busy; int looptest; }; diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig index ebaa749ce9..e872fcb194 100644 --- a/hw/nvram/Kconfig +++ b/hw/nvram/Kconfig @@ -7,3 +7,11 @@ config AT24C config MAC_NVRAM bool + select CHRP_NVRAM + +# NMC93XX uses the NS uWire interface (similar to SPI but less configurable) +config NMC93XX_EEPROM + bool + +config CHRP_NVRAM + bool diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs index 26f7b4ca35..090df63fcd 100644 --- a/hw/nvram/Makefile.objs +++ b/hw/nvram/Makefile.objs @@ -1,8 +1,8 @@ common-obj-$(CONFIG_DS1225Y) += ds1225y.o -common-obj-y += eeprom93xx.o +common-obj-$(CONFIG_NMC93XX_EEPROM) += eeprom93xx.o common-obj-$(CONFIG_AT24C) += eeprom_at24c.o common-obj-y += fw_cfg.o -common-obj-y += chrp_nvram.o +common-obj-$(CONFIG_CHRP_NVRAM) += chrp_nvram.o common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o obj-$(CONFIG_PSERIES) += spapr_nvram.o obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index f927ec9c74..e27efe9a24 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -10,6 +10,8 @@ config PSERIES select XICS_SPAPR select XIVE_SPAPR select MSI_NONBROKEN + select FDT_PPC + select CHRP_NVRAM config SPAPR_RNG bool @@ -26,6 +28,7 @@ config POWERNV select MC146818RTC select XICS select XIVE + select FDT_PPC config PPC405 bool @@ -42,6 +45,7 @@ config PPC440 select PCI_EXPRESS select PPC4XX select SERIAL + select FDT_PPC config PPC4XX bool @@ -50,6 +54,7 @@ config PPC4XX config SAM460EX bool + select PPC405 select PFLASH_CFI01 select IDE_SII3112 select M41T80 @@ -59,6 +64,7 @@ config SAM460EX select SMBUS_EEPROM select USB_EHCI_SYSBUS select USB_OHCI + select FDT_PPC config PREP bool @@ -71,6 +77,7 @@ config PREP select M48T59 select PC87312 select RS6000_MC + select FW_CFG_PPC config RS6000_MC bool @@ -84,6 +91,7 @@ config MAC_OLDWORLD select GRACKLE_PCI select HEATHROW_PIC select MACIO + select FW_CFG_PPC config MAC_NEWWORLD bool @@ -95,6 +103,7 @@ config MAC_NEWWORLD select MACIO_GPIO select MAC_PMU select UNIN_PCI + select FW_CFG_PPC config E500 bool @@ -105,13 +114,17 @@ config E500 select PLATFORM_BUS select PPCE500_PCI select SERIAL + select MPC_I2C + select FDT_PPC config VIRTEX bool + select PPC4XX select PFLASH_CFI01 select SERIAL select XILINX select XILINX_ETHLITE + select FDT_PPC config XIVE bool @@ -127,3 +140,10 @@ config XIVE_KVM bool default y depends on XIVE_SPAPR && KVM + +# Only used by 64-bit targets +config FW_CFG_PPC + bool + +config FDT_PPC + bool diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index 101e9fc591..a4bac57be6 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -1,5 +1,7 @@ # shared objects -obj-y += ppc.o ppc_booke.o fdt.o fw_cfg.o +obj-y += ppc.o ppc_booke.o +obj-$(CONFIG_FDT_PPC) += fdt.o +obj-$(CONFIG_FW_CFG_PPC) += fw_cfg.o # IBM pSeries (sPAPR) obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o @@ -7,14 +9,11 @@ obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o +obj-$(call land,$(CONFIG_PSERIES),$(CONFIG_LINUX)) += spapr_pci_vfio.o spapr_pci_nvlink2.o # IBM PowerNV obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o obj-$(CONFIG_POWERNV) += pnv_homer.o pnv_pnor.o - -ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) -obj-y += spapr_pci_vfio.o spapr_pci_nvlink2.o -endif obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o # PowerPC 4xx boards obj-$(CONFIG_PPC405) += ppc405_boards.o ppc405_uc.o diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f77e7ca84e..e2735bb8dd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -561,7 +561,7 @@ static void *pnv_dt_create(MachineState *machine) static void pnv_powerdown_notify(Notifier *n, void *opaque) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); if (pnv->bmc) { pnv_bmc_powerdown(pnv->bmc); @@ -768,6 +768,18 @@ static void pnv_init(MachineState *machine) exit(1); } + pnv->num_chips = + machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); + /* + * TODO: should we decide on how many chips we can create based + * on #cores and Venice vs. Murano vs. Naples chip type etc..., + */ + if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { + error_report("invalid number of chips: '%d'", pnv->num_chips); + error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); + exit(1); + } + pnv->chips = g_new0(PnvChip *, pnv->num_chips); for (i = 0; i < pnv->num_chips; i++) { char chip_name[32]; @@ -790,12 +802,25 @@ static void pnv_init(MachineState *machine) &error_fatal); object_property_set_int(chip, machine->smp.cores, "nr-cores", &error_fatal); + object_property_set_int(chip, machine->smp.threads, + "nr-threads", &error_fatal); + /* + * The POWER8 machine use the XICS interrupt interface. + * Propagate the XICS fabric to the chip and its controllers. + */ + if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { + object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); + } + if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { + object_property_set_link(chip, OBJECT(pnv), "xive-fabric", + &error_abort); + } object_property_set_bool(chip, true, "realized", &error_fatal); } g_free(chip_typename); /* Create the machine BMC simulator */ - pnv->bmc = pnv_bmc_create(); + pnv->bmc = pnv_bmc_create(pnv->pnor); /* Instantiate ISA bus on chip 0 */ pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); @@ -831,12 +856,12 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { + Pnv8Chip *chip8 = PNV8_CHIP(chip); Error *local_err = NULL; Object *obj; PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); - obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), - &local_err); + obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -900,7 +925,8 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, * controller object is initialized afterwards. Hopefully, it's * only used at runtime. */ - obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), + &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -990,10 +1016,14 @@ static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 = PNV8_CHIP(obj); + object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, + (Object **)&chip8->xics, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG, + &error_abort); + object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), TYPE_PNV8_PSI, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip8->psi), "xics", - OBJECT(qdev_get_machine()), &error_abort); object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), TYPE_PNV8_LPC, &error_abort, NULL); @@ -1011,7 +1041,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); int i, j; char *name; - XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); name = g_strdup_printf("icp-%x", chip->chip_id); memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); @@ -1027,7 +1056,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { uint32_t pir = pcc->core_pir(chip, core_hwid) + j; - PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); + PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); memory_region_add_subregion(&chip8->icp_mmio, pir << 12, &icp->mmio); @@ -1043,6 +1072,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) Pnv8Psi *psi8 = &chip8->psi; Error *local_err = NULL; + assert(chip8->xics); + /* XSCOM bridge is first */ pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); if (local_err) { @@ -1060,6 +1091,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* Processor Service Interface (PSI) Host Bridge */ object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), "bar", &error_fatal); + object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), + ICS_PROP_XICS, &error_abort); object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); @@ -1201,6 +1234,8 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), TYPE_PNV_XIVE, &error_abort, NULL); + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), + "xive-fabric", &error_abort); object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), TYPE_PNV9_PSI, &error_abort, NULL); @@ -1494,7 +1529,6 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { - MachineState *ms = MACHINE(qdev_get_machine()); Error *error = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); const char *typename = pnv_chip_core_typename(chip); @@ -1530,8 +1564,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), &error_abort); chip->cores[i] = pnv_core; - object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", - &error_fatal); + object_property_set_int(OBJECT(pnv_core), chip->nr_threads, + "nr-threads", &error_fatal); object_property_set_int(OBJECT(pnv_core), core_hwid, CPU_CORE_PROP_CORE_ID, &error_fatal); object_property_set_int(OBJECT(pnv_core), @@ -1570,6 +1604,7 @@ static Property pnv_chip_properties[] = { DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), + DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -1682,67 +1717,6 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, return total_count; } -PnvChip *pnv_get_chip(uint32_t chip_id) -{ - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - int i; - - for (i = 0; i < pnv->num_chips; i++) { - PnvChip *chip = pnv->chips[i]; - if (chip->chip_id == chip_id) { - return chip; - } - } - return NULL; -} - -static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); -} - -static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - PnvMachineState *pnv = PNV_MACHINE(obj); - uint32_t num_chips; - Error *local_err = NULL; - - visit_type_uint32(v, name, &num_chips, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - /* - * TODO: should we decide on how many chips we can create based - * on #cores and Venice vs. Murano vs. Naples chip type etc..., - */ - if (!is_power_of_2(num_chips) || num_chips > 4) { - error_setg(errp, "invalid number of chips: '%d'", num_chips); - return; - } - - pnv->num_chips = num_chips; -} - -static void pnv_machine_instance_init(Object *obj) -{ - PnvMachineState *pnv = PNV_MACHINE(obj); - pnv->num_chips = 1; -} - -static void pnv_machine_class_props_init(ObjectClass *oc) -{ - object_class_property_add(oc, "num-chips", "uint32", - pnv_get_num_chips, pnv_set_num_chips, - NULL, NULL, NULL); - object_class_property_set_description(oc, "num-chips", - "Specifies the number of processor chips", - NULL); -} - static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1812,8 +1786,6 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) */ mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; ispc->print_info = pnv_pic_print_info; - - pnv_machine_class_props_init(oc); } #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ @@ -1866,7 +1838,6 @@ static const TypeInfo types[] = { .parent = TYPE_MACHINE, .abstract = true, .instance_size = sizeof(PnvMachineState), - .instance_init = pnv_machine_instance_init, .class_init = pnv_machine_class_init, .class_size = sizeof(PnvMachineClass), .interfaces = (InterfaceInfo[]) { diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index 07fa1e1c7e..8863354c1c 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -143,8 +143,8 @@ static uint16_t bytes_to_blocks(uint32_t bytes) static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len, RspBuffer *rsp) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - PnvPnor *pnor = pnv->pnor; + PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor", + &error_abort)); uint32_t pnor_size = pnor->size; uint32_t pnor_addr = PNOR_SPI_OFFSET; bool readonly = false; @@ -217,11 +217,13 @@ static const IPMINetfn hiomap_netfn = { * Instantiate the machine BMC. PowerNV uses the QEMU internal * simulator but it could also be external. */ -IPMIBmc *pnv_bmc_create(void) +IPMIBmc *pnv_bmc_create(PnvPnor *pnor) { Object *obj; obj = object_new(TYPE_IPMI_BMC_SIMULATOR); + object_ref(OBJECT(pnor)); + object_property_add_const_link(obj, "pnor", OBJECT(pnor), &error_abort); object_property_set_bool(obj, true, "realized", &error_fatal); /* Install the HIOMAP protocol handlers to access the PNOR */ diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c index bfb1e92b03..b061106d1c 100644 --- a/hw/ppc/pnv_pnor.c +++ b/hw/ppc/pnv_pnor.c @@ -33,6 +33,7 @@ static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size) static void pnv_pnor_update(PnvPnor *s, int offset, int size) { int offset_end; + int ret; if (s->blk) { return; @@ -42,8 +43,11 @@ static void pnv_pnor_update(PnvPnor *s, int offset, int size) offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); - blk_pwrite(s->blk, offset, s->storage + offset, - offset_end - offset, 0); + ret = blk_pwrite(s->blk, offset, s->storage + offset, + offset_end - offset, 0); + if (ret < 0) { + error_report("Could not update PNOR: %s", strerror(-ret)); + } } static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data, @@ -107,7 +111,7 @@ static void pnv_pnor_realize(DeviceState *dev, Error **errp) } static Property pnv_pnor_properties[] = { - DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20), + DEFINE_PROP_INT64("size", PnvPnor, size, 128 << 20), DEFINE_PROP_DRIVE("drive", PnvPnor, blk), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 75e20d9da0..1d8da31738 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -455,7 +455,7 @@ static const MemoryRegionOps pnv_psi_xscom_ops = { } }; -static void pnv_psi_reset(void *dev) +static void pnv_psi_reset(DeviceState *dev) { PnvPsi *psi = PNV_PSI(dev); @@ -464,12 +464,29 @@ static void pnv_psi_reset(void *dev) psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; } +static void pnv_psi_reset_handler(void *dev) +{ + device_reset(DEVICE(dev)); +} + +static void pnv_psi_realize(DeviceState *dev, Error **errp) +{ + PnvPsi *psi = PNV_PSI(dev); + + /* Default BAR for MMIO region */ + pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); + + qemu_register_reset(pnv_psi_reset_handler, dev); +} + static void pnv_psi_power8_instance_init(Object *obj) { Pnv8Psi *psi8 = PNV8_PSI(obj); object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics), TYPE_ICS, &error_abort, NULL); + object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), + ICS_PROP_XICS, &error_abort); } static const uint8_t irq_to_xivr[] = { @@ -485,19 +502,10 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) { PnvPsi *psi = PNV_PSI(dev); ICSState *ics = &PNV8_PSI(psi)->ics; - Object *obj; Error *err = NULL; unsigned int i; - obj = object_property_get_link(OBJECT(dev), "xics", &err); - if (!obj) { - error_setg(errp, "%s: required link 'xics' not found: %s", - __func__, error_get_pretty(err)); - return; - } - /* Create PSI interrupt control source */ - object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort); object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); if (err) { error_propagate(errp, err); @@ -523,9 +531,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, "psihb", PNV_PSIHB_SIZE); - /* Default BAR for MMIO region */ - pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); - /* Default sources in XIVR */ for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { uint8_t xivr = irq_to_xivr[i]; @@ -533,7 +538,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) ((uint64_t) i << PSIHB_XIVR_SRC_SH); } - qemu_register_reset(pnv_psi_reset, dev); + pnv_psi_realize(dev, errp); } static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) @@ -816,7 +821,7 @@ static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state) qemu_set_irq(psi->qirqs[irq], state); } -static void pnv_psi_power9_reset(void *dev) +static void pnv_psi_power9_reset(DeviceState *dev) { Pnv9Psi *psi = PNV9_PSI(dev); @@ -868,9 +873,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, "psihb", PNV9_PSIHB_SIZE); - pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); - - qemu_register_reset(pnv_psi_power9_reset, dev); + pnv_psi_realize(dev, errp); } static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) @@ -882,6 +885,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller POWER9"; dc->realize = pnv_psi_power9_realize; + dc->reset = pnv_psi_power9_reset; ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; @@ -934,6 +938,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller"; dc->props = pnv_psi_properties; + dc->reset = pnv_psi_reset; } static const TypeInfo pnv_psi_info = { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 4d95c0f8a8..b782641b23 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -71,12 +71,12 @@ static int bamboo_load_device_tree(hwaddr addr, filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); if (!filename) { - goto out; + return -1; } fdt = load_device_tree(filename, &fdt_size); g_free(filename); if (fdt == NULL) { - goto out; + return -1; } /* Manipulate device tree in memory. */ @@ -117,10 +117,6 @@ static int bamboo_load_device_tree(hwaddr addr, rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); g_free(fdt); return 0; - -out: - - return ret; } /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f11422fc41..30a5fbd3be 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -878,7 +878,7 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, g_assert(smc->dr_lmb_enabled); ret = spapr_populate_drconf_memory(spapr, fdt); if (ret) { - goto out; + return ret; } } @@ -889,11 +889,8 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, return offset; } } - ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, - "ibm,architecture-vec-5"); - -out: - return ret; + return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, + "ibm,architecture-vec-5"); } static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) @@ -1597,6 +1594,7 @@ static void spapr_machine_reset(MachineState *machine) void *fdt; int rc; + kvmppc_svm_off(&error_fatal); spapr_caps_apply(spapr); first_ppc_cpu = POWERPC_CPU(first_cpu); @@ -4197,19 +4195,19 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj, kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } +/* + * This is a XIVE only operation + */ static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { SpaprMachineState *spapr = SPAPR_MACHINE(xfb); - XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); + XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); int count; - /* This is a XIVE only operation */ - assert(spapr->active_intc == SPAPR_INTC(spapr->xive)); - count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, priority, logic_serv, match); if (count < 0) { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 373505d28b..1f630f296b 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -332,6 +332,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) * priority */ qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); + object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric", + &error_abort); qdev_init_nofail(dev); spapr->xive = SPAPR_XIVE(dev); diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c index 4f7b11dc37..ca87a5cf9f 100644 --- a/hw/riscv/riscv_htif.c +++ b/hw/riscv/riscv_htif.c @@ -96,7 +96,7 @@ static void htif_recv(void *opaque, const uint8_t *buf, int size) * Called by the char dev to supply special events to the HTIF console. * Not used for HTIF. */ -static void htif_event(void *opaque, int event) +static void htif_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index a403ae90f5..9350482662 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -162,7 +162,7 @@ static int uart_can_rx(void *opaque) return s->rx_fifo_len < sizeof(s->rx_fifo); } -static void uart_event(void *opaque, int event) +static void uart_event(void *opaque, QEMUChrEvent event) { } diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig index 45daa8d655..3dc2dd6888 100644 --- a/hw/rtc/Kconfig +++ b/hw/rtc/Kconfig @@ -17,6 +17,7 @@ config TWL92230 depends on I2C config MC146818RTC + depends on ISA_BUS bool config SUN4V_RTC diff --git a/hw/scsi/Kconfig b/hw/scsi/Kconfig index b3ba540c17..77d397c949 100644 --- a/hw/scsi/Kconfig +++ b/hw/scsi/Kconfig @@ -34,6 +34,7 @@ config ESP_PCI default y if PCI_DEVICES depends on PCI select ESP + select NMC93XX_EEPROM config SPAPR_VSCSI bool diff --git a/hw/semihosting/console.c b/hw/semihosting/console.c index b4b17c8afb..6346bd7f50 100644 --- a/hw/semihosting/console.c +++ b/hw/semihosting/console.c @@ -20,8 +20,15 @@ #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" #include "exec/gdbstub.h" +#include "exec/exec-all.h" #include "qemu/log.h" #include "chardev/char.h" +#include <pthread.h> +#include "chardev/char-fe.h" +#include "sysemu/sysemu.h" +#include "qemu/main-loop.h" +#include "qapi/error.h" +#include "qemu/fifo8.h" int qemu_semihosting_log_out(const char *s, int len) { @@ -98,3 +105,75 @@ void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) __func__, addr); } } + +#define FIFO_SIZE 1024 + +/* Access to this structure is protected by the BQL */ +typedef struct SemihostingConsole { + CharBackend backend; + GSList *sleeping_cpus; + bool got; + Fifo8 fifo; +} SemihostingConsole; + +static SemihostingConsole console; + +static int console_can_read(void *opaque) +{ + SemihostingConsole *c = opaque; + int ret; + g_assert(qemu_mutex_iothread_locked()); + ret = (int) fifo8_num_free(&c->fifo); + return ret; +} + +static void console_wake_up(gpointer data, gpointer user_data) +{ + CPUState *cs = (CPUState *) data; + /* cpu_handle_halt won't know we have work so just unbung here */ + cs->halted = 0; + qemu_cpu_kick(cs); +} + +static void console_read(void *opaque, const uint8_t *buf, int size) +{ + SemihostingConsole *c = opaque; + g_assert(qemu_mutex_iothread_locked()); + while (size-- && !fifo8_is_full(&c->fifo)) { + fifo8_push(&c->fifo, *buf++); + } + g_slist_foreach(c->sleeping_cpus, console_wake_up, NULL); + c->sleeping_cpus = NULL; +} + +target_ulong qemu_semihosting_console_inc(CPUArchState *env) +{ + uint8_t ch; + SemihostingConsole *c = &console; + g_assert(qemu_mutex_iothread_locked()); + g_assert(current_cpu); + if (fifo8_is_empty(&c->fifo)) { + c->sleeping_cpus = g_slist_prepend(c->sleeping_cpus, current_cpu); + current_cpu->halted = 1; + current_cpu->exception_index = EXCP_HALTED; + cpu_loop_exit(current_cpu); + /* never returns */ + } + ch = fifo8_pop(&c->fifo); + return (target_ulong) ch; +} + +void qemu_semihosting_console_init(void) +{ + Chardev *chr = semihosting_get_chardev(); + + if (chr) { + fifo8_create(&console.fifo, FIFO_SIZE); + qemu_chr_fe_init(&console.backend, chr, &error_abort); + qemu_chr_fe_set_handlers(&console.backend, + console_can_read, + console_read, + NULL, NULL, &console, + NULL, true); + } +} diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index ee0840f380..72bb5285cc 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -272,7 +272,7 @@ static void r2d_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); qdev_prop_set_uint32(dev, "base", 0x10000000); - qdev_prop_set_ptr(dev, "chr-state", serial_hd(2)); + qdev_prop_set_chr(dev, "chardev", serial_hd(2)); qdev_init_nofail(dev); sysbus_mmio_map(busdev, 0, 0x10000000); sysbus_mmio_map(busdev, 1, 0x13e00000); diff --git a/hw/sparc/Kconfig b/hw/sparc/Kconfig index 2a83a8010e..22aff2f5b7 100644 --- a/hw/sparc/Kconfig +++ b/hw/sparc/Kconfig @@ -12,6 +12,7 @@ config SUN4M select LANCE select M48T59 select STP2000 + select CHRP_NVRAM config LEON3 bool diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index c5f1b1ee72..8038887ff7 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -143,9 +143,14 @@ void leon3_irq_ack(void *irq_manager, int intno) grlib_irqmp_ack((DeviceState *)irq_manager, intno); } -static void leon3_set_pil_in(void *opaque, uint32_t pil_in) +/* + * This device assumes that the incoming 'level' value on the + * qemu_irq is the interrupt number, not just a simple 0/1 level. + */ +static void leon3_set_pil_in(void *opaque, int n, int level) { - CPUSPARCState *env = (CPUSPARCState *)opaque; + CPUSPARCState *env = opaque; + uint32_t pil_in = level; CPUState *cs; assert(env != NULL); @@ -225,8 +230,10 @@ static void leon3_generic_hw_init(MachineState *machine) /* Allocate IRQ manager */ dev = qdev_create(NULL, TYPE_GRLIB_IRQMP); - qdev_prop_set_ptr(dev, "set_pil_in", leon3_set_pil_in); - qdev_prop_set_ptr(dev, "set_pil_in_opaque", env); + qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, + env, "pil", 1); + qdev_connect_gpio_out_named(dev, "grlib-irq", 0, + qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET); env->irq_manager = dev; diff --git a/hw/sparc64/Kconfig b/hw/sparc64/Kconfig index f9f8b0f73a..980a201bb7 100644 --- a/hw/sparc64/Kconfig +++ b/hw/sparc64/Kconfig @@ -12,6 +12,7 @@ config SUN4U select IDE_CMD646 select PCKBD select SIMBA + select CHRP_NVRAM config NIAGARA bool diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index a990f9fe35..59b3f44d69 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -15,6 +15,7 @@ config HPET config I8254 bool + depends on ISA_BUS config ALTERA_TIMER bool diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs index 0ab20f9d73..0052d49ce1 100644 --- a/hw/usb/Makefile.objs +++ b/hw/usb/Makefile.objs @@ -39,9 +39,11 @@ common-obj-$(CONFIG_USB_STORAGE_MTP) += dev-mtp.o endif # usb redirection +ifeq ($(CONFIG_USB),y) common-obj-$(CONFIG_USB_REDIR) += redirect.o quirks.o redirect.o-cflags = $(USB_REDIR_CFLAGS) redirect.o-libs = $(USB_REDIR_LIBS) +endif # usb pass-through ifeq ($(CONFIG_USB_LIBUSB)$(CONFIG_USB),yy) diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index 267ed9a8a0..3d40b700db 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -307,7 +307,7 @@ static void ccid_card_vscard_read(void *opaque, const uint8_t *buf, int size) } } -static void ccid_card_vscard_event(void *opaque, int event) +static void ccid_card_vscard_event(void *opaque, QEMUChrEvent event) { PassthruState *card = opaque; @@ -318,6 +318,11 @@ static void ccid_card_vscard_event(void *opaque, int event) case CHR_EVENT_OPENED: DPRINTF(card, D_INFO, "%s: CHR_EVENT_OPENED\n", __func__); break; + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + case CHR_EVENT_CLOSED: + /* Ignore */ + break; } } diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c index 45cc74128a..9646fe77da 100644 --- a/hw/usb/dev-serial.c +++ b/hw/usb/dev-serial.c @@ -461,7 +461,7 @@ static void usb_serial_read(void *opaque, const uint8_t *buf, int size) s->recv_used += size; } -static void usb_serial_event(void *opaque, int event) +static void usb_serial_event(void *opaque, QEMUChrEvent event) { USBSerialState *s = opaque; @@ -479,6 +479,10 @@ static void usb_serial_event(void *opaque, int event) usb_device_detach(&s->dev); } break; + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; } } diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index e0f5ca6f81..0068aa8a19 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1354,7 +1354,7 @@ static void usbredir_chardev_read(void *opaque, const uint8_t *buf, int size) usbredirparser_do_write(dev->parser); } -static void usbredir_chardev_event(void *opaque, int event) +static void usbredir_chardev_event(void *opaque, QEMUChrEvent event) { USBRedirDevice *dev = opaque; @@ -1370,6 +1370,11 @@ static void usbredir_chardev_event(void *opaque, int event) DPRINTF("chardev close\n"); qemu_bh_schedule(dev->chardev_close_bh); break; + case CHR_EVENT_BREAK: + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; } } |