diff options
Diffstat (limited to 'hw')
48 files changed, 2107 insertions, 12445 deletions
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 095597f791..f3ade9a28e 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -1,7 +1,7 @@ common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o pcihp.o common-obj-$(CONFIG_ACPI_X86_ICH) += ich9.o tco.o -common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o -common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o +common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o cpu_hotplug_acpi_table.o +common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o memory_hotplug_acpi_table.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o common-obj-$(CONFIG_ACPI) += acpi_interface.o common-obj-$(CONFIG_ACPI) += bios-linker-loader.o diff --git a/hw/acpi/cpu_hotplug_acpi_table.c b/hw/acpi/cpu_hotplug_acpi_table.c new file mode 100644 index 0000000000..13b210ea89 --- /dev/null +++ b/hw/acpi/cpu_hotplug_acpi_table.c @@ -0,0 +1,135 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "hw/acpi/cpu_hotplug.h" + +void build_cpu_hotplug_aml(Aml *ctx) +{ + Aml *method; + Aml *if_ctx; + Aml *else_ctx; + Aml *sb_scope = aml_scope("_SB"); + uint8_t madt_tmpl[8] = {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}; + Aml *cpu_id = aml_arg(0); + Aml *cpu_on = aml_local(0); + Aml *madt = aml_local(1); + Aml *cpus_map = aml_name(CPU_ON_BITMAP); + Aml *zero = aml_int(0); + Aml *one = aml_int(1); + + /* + * _MAT method - creates an madt apic buffer + * cpu_id = Arg0 = Processor ID = Local APIC ID + * cpu_on = Local0 = CPON flag for this cpu + * madt = Local1 = Buffer (in madt apic form) to return + */ + method = aml_method(CPU_MAT_METHOD, 1, AML_NOTSERIALIZED); + aml_append(method, + aml_store(aml_derefof(aml_index(cpus_map, cpu_id)), cpu_on)); + aml_append(method, + aml_store(aml_buffer(sizeof(madt_tmpl), madt_tmpl), madt)); + /* Update the processor id, lapic id, and enable/disable status */ + aml_append(method, aml_store(cpu_id, aml_index(madt, aml_int(2)))); + aml_append(method, aml_store(cpu_id, aml_index(madt, aml_int(3)))); + aml_append(method, aml_store(cpu_on, aml_index(madt, aml_int(4)))); + aml_append(method, aml_return(madt)); + aml_append(sb_scope, method); + + /* + * _STA method - return ON status of cpu + * cpu_id = Arg0 = Processor ID = Local APIC ID + * cpu_on = Local0 = CPON flag for this cpu + */ + method = aml_method(CPU_STATUS_METHOD, 1, AML_NOTSERIALIZED); + aml_append(method, + aml_store(aml_derefof(aml_index(cpus_map, cpu_id)), cpu_on)); + if_ctx = aml_if(cpu_on); + { + aml_append(if_ctx, aml_return(aml_int(0xF))); + } + aml_append(method, if_ctx); + else_ctx = aml_else(); + { + aml_append(else_ctx, aml_return(zero)); + } + aml_append(method, else_ctx); + aml_append(sb_scope, method); + + method = aml_method(CPU_EJECT_METHOD, 2, AML_NOTSERIALIZED); + aml_append(method, aml_sleep(200)); + aml_append(sb_scope, method); + + method = aml_method(CPU_SCAN_METHOD, 0, AML_NOTSERIALIZED); + { + Aml *while_ctx, *if_ctx2, *else_ctx2; + Aml *bus_check_evt = aml_int(1); + Aml *remove_evt = aml_int(3); + Aml *status_map = aml_local(5); /* Local5 = active cpu bitmap */ + Aml *byte = aml_local(2); /* Local2 = last read byte from bitmap */ + Aml *idx = aml_local(0); /* Processor ID / APIC ID iterator */ + Aml *is_cpu_on = aml_local(1); /* Local1 = CPON flag for cpu */ + Aml *status = aml_local(3); /* Local3 = active state for cpu */ + + aml_append(method, aml_store(aml_name(CPU_STATUS_MAP), status_map)); + aml_append(method, aml_store(zero, byte)); + aml_append(method, aml_store(zero, idx)); + + /* While (idx < SizeOf(CPON)) */ + while_ctx = aml_while(aml_lless(idx, aml_sizeof(cpus_map))); + aml_append(while_ctx, + aml_store(aml_derefof(aml_index(cpus_map, idx)), is_cpu_on)); + + if_ctx = aml_if(aml_and(idx, aml_int(0x07), NULL)); + { + /* Shift down previously read bitmap byte */ + aml_append(if_ctx, aml_shiftright(byte, one, byte)); + } + aml_append(while_ctx, if_ctx); + + else_ctx = aml_else(); + { + /* Read next byte from cpu bitmap */ + aml_append(else_ctx, aml_store(aml_derefof(aml_index(status_map, + aml_shiftright(idx, aml_int(3), NULL))), byte)); + } + aml_append(while_ctx, else_ctx); + + aml_append(while_ctx, aml_store(aml_and(byte, one, NULL), status)); + if_ctx = aml_if(aml_lnot(aml_equal(is_cpu_on, status))); + { + /* State change - update CPON with new state */ + aml_append(if_ctx, aml_store(status, aml_index(cpus_map, idx))); + if_ctx2 = aml_if(aml_equal(status, one)); + { + aml_append(if_ctx2, + aml_call2(AML_NOTIFY_METHOD, idx, bus_check_evt)); + } + aml_append(if_ctx, if_ctx2); + else_ctx2 = aml_else(); + { + aml_append(else_ctx2, + aml_call2(AML_NOTIFY_METHOD, idx, remove_evt)); + } + } + aml_append(if_ctx, else_ctx2); + aml_append(while_ctx, if_ctx); + + aml_append(while_ctx, aml_increment(idx)); /* go to next cpu */ + aml_append(method, while_ctx); + } + aml_append(sb_scope, method); + + aml_append(ctx, sb_scope); +} diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c index 298e8682af..65cbc80414 100644 --- a/hw/acpi/memory_hotplug.c +++ b/hw/acpi/memory_hotplug.c @@ -250,7 +250,6 @@ void acpi_memory_plug_cb(ACPIREGS *ar, qemu_irq irq, MemHotplugState *mem_st, /* do ACPI magic */ acpi_send_gpe_event(ar, irq, ACPI_MEMORY_HOTPLUG_STATUS); } - return; } void acpi_memory_unplug_request_cb(ACPIREGS *ar, qemu_irq irq, diff --git a/hw/acpi/memory_hotplug_acpi_table.c b/hw/acpi/memory_hotplug_acpi_table.c new file mode 100644 index 0000000000..080d9add5b --- /dev/null +++ b/hw/acpi/memory_hotplug_acpi_table.c @@ -0,0 +1,262 @@ +/* + * Memory hotplug AML code of DSDT ACPI table + * + * Copyright (C) 2015 Red Hat Inc + * + * Author: Igor Mammedov <imammedo@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include <stdbool.h> +#include "hw/acpi/memory_hotplug.h" +#include "include/hw/acpi/pc-hotplug.h" +#include "hw/boards.h" + +void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem, + uint16_t io_base, uint16_t io_len) +{ + Aml *ifctx; + Aml *method; + Aml *pci_scope; + Aml *mem_ctrl_dev; + + /* scope for memory hotplug controller device node */ + pci_scope = aml_scope("_SB.PCI0"); + mem_ctrl_dev = aml_device(MEMORY_HOTPLUG_DEVICE); + { + Aml *one = aml_int(1); + Aml *zero = aml_int(0); + Aml *ret_val = aml_local(0); + Aml *slot_arg0 = aml_arg(0); + Aml *slots_nr = aml_name(MEMORY_SLOTS_NUMBER); + Aml *ctrl_lock = aml_name(MEMORY_SLOT_LOCK); + Aml *slot_selector = aml_name(MEMORY_SLOT_SLECTOR); + + aml_append(mem_ctrl_dev, aml_name_decl("_HID", aml_string("PNP0A06"))); + aml_append(mem_ctrl_dev, + aml_name_decl("_UID", aml_string("Memory hotplug resources"))); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + ifctx = aml_if(aml_equal(slots_nr, zero)); + { + aml_append(ifctx, aml_return(zero)); + } + aml_append(method, ifctx); + /* present, functioning, decoding, not shown in UI */ + aml_append(method, aml_return(aml_int(0xB))); + aml_append(mem_ctrl_dev, method); + + aml_append(mem_ctrl_dev, aml_mutex(MEMORY_SLOT_LOCK, 0)); + + method = aml_method(MEMORY_SLOT_SCAN_METHOD, 0, AML_NOTSERIALIZED); + { + Aml *else_ctx; + Aml *while_ctx; + Aml *idx = aml_local(0); + Aml *eject_req = aml_int(3); + Aml *dev_chk = aml_int(1); + + ifctx = aml_if(aml_equal(slots_nr, zero)); + { + aml_append(ifctx, aml_return(zero)); + } + aml_append(method, ifctx); + + aml_append(method, aml_store(zero, idx)); + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + /* build AML that: + * loops over all slots and Notifies DIMMs with + * Device Check or Eject Request notifications if + * slot has corresponding status bit set and clears + * slot status. + */ + while_ctx = aml_while(aml_lless(idx, slots_nr)); + { + Aml *ins_evt = aml_name(MEMORY_SLOT_INSERT_EVENT); + Aml *rm_evt = aml_name(MEMORY_SLOT_REMOVE_EVENT); + + aml_append(while_ctx, aml_store(idx, slot_selector)); + ifctx = aml_if(aml_equal(ins_evt, one)); + { + aml_append(ifctx, + aml_call2(MEMORY_SLOT_NOTIFY_METHOD, + idx, dev_chk)); + aml_append(ifctx, aml_store(one, ins_evt)); + } + aml_append(while_ctx, ifctx); + + else_ctx = aml_else(); + ifctx = aml_if(aml_equal(rm_evt, one)); + { + aml_append(ifctx, + aml_call2(MEMORY_SLOT_NOTIFY_METHOD, + idx, eject_req)); + aml_append(ifctx, aml_store(one, rm_evt)); + } + aml_append(else_ctx, ifctx); + aml_append(while_ctx, else_ctx); + + aml_append(while_ctx, aml_add(idx, one, idx)); + } + aml_append(method, while_ctx); + aml_append(method, aml_release(ctrl_lock)); + aml_append(method, aml_return(one)); + } + aml_append(mem_ctrl_dev, method); + + method = aml_method(MEMORY_SLOT_STATUS_METHOD, 1, AML_NOTSERIALIZED); + { + Aml *slot_enabled = aml_name(MEMORY_SLOT_ENABLED); + + aml_append(method, aml_store(zero, ret_val)); + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + aml_append(method, + aml_store(aml_to_integer(slot_arg0), slot_selector)); + + ifctx = aml_if(aml_equal(slot_enabled, one)); + { + aml_append(ifctx, aml_store(aml_int(0xF), ret_val)); + } + aml_append(method, ifctx); + + aml_append(method, aml_release(ctrl_lock)); + aml_append(method, aml_return(ret_val)); + } + aml_append(mem_ctrl_dev, method); + + method = aml_method(MEMORY_SLOT_CRS_METHOD, 1, AML_SERIALIZED); + { + Aml *mr64 = aml_name("MR64"); + Aml *mr32 = aml_name("MR32"); + Aml *crs_tmpl = aml_resource_template(); + Aml *minl = aml_name("MINL"); + Aml *minh = aml_name("MINH"); + Aml *maxl = aml_name("MAXL"); + Aml *maxh = aml_name("MAXH"); + Aml *lenl = aml_name("LENL"); + Aml *lenh = aml_name("LENH"); + + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + aml_append(method, aml_store(aml_to_integer(slot_arg0), + slot_selector)); + + aml_append(crs_tmpl, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, + 0, 0x0, 0xFFFFFFFFFFFFFFFEULL, 0, + 0xFFFFFFFFFFFFFFFFULL)); + aml_append(method, aml_name_decl("MR64", crs_tmpl)); + aml_append(method, + aml_create_dword_field(mr64, aml_int(14), "MINL")); + aml_append(method, + aml_create_dword_field(mr64, aml_int(18), "MINH")); + aml_append(method, + aml_create_dword_field(mr64, aml_int(38), "LENL")); + aml_append(method, + aml_create_dword_field(mr64, aml_int(42), "LENH")); + aml_append(method, + aml_create_dword_field(mr64, aml_int(22), "MAXL")); + aml_append(method, + aml_create_dword_field(mr64, aml_int(26), "MAXH")); + + aml_append(method, + aml_store(aml_name(MEMORY_SLOT_ADDR_HIGH), minh)); + aml_append(method, + aml_store(aml_name(MEMORY_SLOT_ADDR_LOW), minl)); + aml_append(method, + aml_store(aml_name(MEMORY_SLOT_SIZE_HIGH), lenh)); + aml_append(method, + aml_store(aml_name(MEMORY_SLOT_SIZE_LOW), lenl)); + + /* 64-bit math: MAX = MIN + LEN - 1 */ + aml_append(method, aml_add(minl, lenl, maxl)); + aml_append(method, aml_add(minh, lenh, maxh)); + ifctx = aml_if(aml_lless(maxl, minl)); + { + aml_append(ifctx, aml_add(maxh, one, maxh)); + } + aml_append(method, ifctx); + ifctx = aml_if(aml_lless(maxl, one)); + { + aml_append(ifctx, aml_subtract(maxh, one, maxh)); + } + aml_append(method, ifctx); + aml_append(method, aml_subtract(maxl, one, maxl)); + + /* return 32-bit _CRS if addr/size is in low mem */ + /* TODO: remove it since all hotplugged DIMMs are in high mem */ + ifctx = aml_if(aml_equal(maxh, zero)); + { + crs_tmpl = aml_resource_template(); + aml_append(crs_tmpl, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_CACHEABLE, + AML_READ_WRITE, + 0, 0x0, 0xFFFFFFFE, 0, + 0xFFFFFFFF)); + aml_append(ifctx, aml_name_decl("MR32", crs_tmpl)); + aml_append(ifctx, + aml_create_dword_field(mr32, aml_int(10), "MIN")); + aml_append(ifctx, + aml_create_dword_field(mr32, aml_int(14), "MAX")); + aml_append(ifctx, + aml_create_dword_field(mr32, aml_int(22), "LEN")); + aml_append(ifctx, aml_store(minl, aml_name("MIN"))); + aml_append(ifctx, aml_store(maxl, aml_name("MAX"))); + aml_append(ifctx, aml_store(lenl, aml_name("LEN"))); + + aml_append(ifctx, aml_release(ctrl_lock)); + aml_append(ifctx, aml_return(mr32)); + } + aml_append(method, ifctx); + + aml_append(method, aml_release(ctrl_lock)); + aml_append(method, aml_return(mr64)); + } + aml_append(mem_ctrl_dev, method); + + method = aml_method(MEMORY_SLOT_PROXIMITY_METHOD, 1, + AML_NOTSERIALIZED); + { + Aml *proximity = aml_name(MEMORY_SLOT_PROXIMITY); + + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + aml_append(method, aml_store(aml_to_integer(slot_arg0), + slot_selector)); + aml_append(method, aml_store(proximity, ret_val)); + aml_append(method, aml_release(ctrl_lock)); + aml_append(method, aml_return(ret_val)); + } + aml_append(mem_ctrl_dev, method); + + method = aml_method(MEMORY_SLOT_OST_METHOD, 4, AML_NOTSERIALIZED); + { + Aml *ost_evt = aml_name(MEMORY_SLOT_OST_EVENT); + Aml *ost_status = aml_name(MEMORY_SLOT_OST_STATUS); + + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + aml_append(method, aml_store(aml_to_integer(slot_arg0), + slot_selector)); + aml_append(method, aml_store(aml_arg(1), ost_evt)); + aml_append(method, aml_store(aml_arg(2), ost_status)); + aml_append(method, aml_release(ctrl_lock)); + } + aml_append(mem_ctrl_dev, method); + + method = aml_method(MEMORY_SLOT_EJECT_METHOD, 2, AML_NOTSERIALIZED); + { + Aml *eject = aml_name(MEMORY_SLOT_EJECT); + + aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); + aml_append(method, aml_store(aml_to_integer(slot_arg0), + slot_selector)); + aml_append(method, aml_store(one, eject)); + aml_append(method, aml_release(ctrl_lock)); + } + aml_append(mem_ctrl_dev, method); + } + aml_append(pci_scope, mem_ctrl_dev); + aml_append(ctx, pci_scope); +} diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 9534418824..df1b176b8f 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -353,16 +353,18 @@ static void nvdimm_build_nfit(GSList *device_list, GArray *table_offsets, GArray *table_data, GArray *linker) { GArray *structures = nvdimm_build_device_structure(device_list); - void *header; + unsigned int header; acpi_add_table(table_offsets, table_data); /* NFIT header. */ - header = acpi_data_push(table_data, sizeof(NvdimmNfitHeader)); + header = table_data->len; + acpi_data_push(table_data, sizeof(NvdimmNfitHeader)); /* NVDIMM device structures. */ g_array_append_vals(table_data, structures->data, structures->len); - build_header(linker, table_data, header, "NFIT", + build_header(linker, table_data, + (void *)(table_data->data + header), "NFIT", sizeof(NvdimmNfitHeader) + structures->len, 1, NULL); g_array_free(structures, true); } diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index c57f293ccd..a2529b2242 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -195,7 +195,7 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_INTERNAL_SNAPSHOT, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_INTERNAL_SNAPSHOT_DELETE, s->blocker); - blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_MIRROR, s->blocker); + blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_MIRROR_SOURCE, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_STREAM, s->blocker); blk_op_unblock(conf->conf.blk, BLOCK_OP_TYPE_REPLACE, s->blocker); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index b3ad467754..4e3173d81a 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -1134,7 +1134,6 @@ post_realize_fail: fail: error_propagate(errp, local_err); - return; } static bool device_get_hotpluggable(Object *obj, Error **errp) diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c index 12b1707cb2..1ea49b7389 100644 --- a/hw/display/jazz_led.c +++ b/hw/display/jazz_led.c @@ -233,8 +233,10 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata) /* TODO: draw the segments */ snprintf(buf, 2, "%02hhx\n", s->segments); - console_write_ch(chardata++, 0x00200100 | buf[0]); - console_write_ch(chardata++, 0x00200100 | buf[1]); + console_write_ch(chardata++, ATTR2CHTYPE(buf[0], QEMU_COLOR_BLUE, + QEMU_COLOR_BLACK, 1)); + console_write_ch(chardata++, ATTR2CHTYPE(buf[1], QEMU_COLOR_BLUE, + QEMU_COLOR_BLACK, 1)); dpy_text_update(s->con, 0, 0, 2, 1); } diff --git a/hw/display/vga.c b/hw/display/vga.c index 9f6839488b..84ce0af562 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -1979,7 +1979,8 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) width = (s->last_width - size) / 2; dst = chardata + s->last_width + width; for (i = 0; i < size; i ++) - console_write_ch(dst ++, 0x00200100 | msg_buffer[i]); + console_write_ch(dst ++, ATTR2CHTYPE(msg_buffer[i], QEMU_COLOR_BLUE, + QEMU_COLOR_BLACK, 1)); dpy_text_update(s->con, 0, 0, s->last_width, height); } diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs index c250deb848..b52d5b8756 100644 --- a/hw/i386/Makefile.objs +++ b/hw/i386/Makefile.objs @@ -8,33 +8,3 @@ obj-$(CONFIG_XEN) += ../xenpv/ xen/ obj-y += kvmvapic.o obj-y += acpi-build.o obj-y += pci-assign-load-rom.o - -gen-hex-y += hw/i386/acpi-dsdt.hex -gen-hex-y += hw/i386/q35-acpi-dsdt.hex - -hw/i386/acpi-build.o: hw/i386/acpi-build.c \ - $(gen-hex-y) - --include $(gen-hex-y:.hex=.d) - -iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \ - ; then echo "$(2)"; else echo "$(3)"; fi ;) - -ifdef IASL -#IASL Present. Generate hex files from .dsl -hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.dsl $(SRC_PATH)/scripts/acpi_extract_preprocess.py $(SRC_PATH)/scripts/acpi_extract.py - $(call quiet-command, $(CPP) -x c -P $(QEMU_DGFLAGS) $(QEMU_INCLUDES) $< -o $*.dsl.i.orig, " CPP $(TARGET_DIR)$*.dsl.i.orig") - $(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract_preprocess.py $*.dsl.i.orig > $*.dsl.i, " ACPI_PREPROCESS $(TARGET_DIR)$*.dsl.i") - $(call quiet-command, $(IASL) $(call iasl-option,$(IASL),-Pn,) -vs -l -tc -p $* $*.dsl.i $(if $(V), , > /dev/null) 2>&1 ," IASL $(TARGET_DIR)$*.dsl.i") - $(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract.py $*.lst > $*.off, " ACPI_EXTRACT $(TARGET_DIR)$*.off") - $(call quiet-command, cat $*.off > $@, " CAT $(TARGET_DIR)$@") -else -#IASL Not present. Restore pre-generated hex files. -hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.hex.generated - $(call quiet-command, cp -f $< $@, " CP $(TARGET_DIR)$@") -endif - -.PHONY: cleanhex -cleanhex: - rm -f hw/i386/*hex -clean: cleanhex diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4cc1440f77..78758e24aa 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -43,6 +43,7 @@ #include "sysemu/tpm.h" #include "hw/acpi/tpm.h" #include "sysemu/tpm_backend.h" +#include "hw/timer/mc146818rtc_regs.h" /* Supported chipsets: */ #include "hw/acpi/piix4.h" @@ -51,9 +52,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci-host/q35.h" #include "hw/i386/intel_iommu.h" - -#include "hw/i386/q35-acpi-dsdt.hex" -#include "hw/i386/acpi-dsdt.hex" +#include "hw/timer/hpet.h" #include "hw/acpi/aml-build.h" @@ -107,6 +106,7 @@ typedef struct AcpiPmInfo { } AcpiPmInfo; typedef struct AcpiMiscInfo { + bool is_piix4; bool has_hpet; TPMVersion tpm_version; const unsigned char *dsdt_code; @@ -122,22 +122,6 @@ typedef struct AcpiBuildPciBusHotplugState { bool pcihp_bridge_en; } AcpiBuildPciBusHotplugState; -static void acpi_get_dsdt(AcpiMiscInfo *info) -{ - Object *piix = piix4_pm_find(); - Object *lpc = ich9_lpc_find(); - assert(!!piix != !!lpc); - - if (piix) { - info->dsdt_code = AcpiDsdtAmlCode; - info->dsdt_size = sizeof AcpiDsdtAmlCode; - } - if (lpc) { - info->dsdt_code = Q35AcpiDsdtAmlCode; - info->dsdt_size = sizeof Q35AcpiDsdtAmlCode; - } -} - static int acpi_add_cpu_info(Object *o, void *opaque) { @@ -236,6 +220,17 @@ static void acpi_get_pm_info(AcpiPmInfo *pm) static void acpi_get_misc_info(AcpiMiscInfo *info) { + Object *piix = piix4_pm_find(); + Object *lpc = ich9_lpc_find(); + assert(!!piix != !!lpc); + + if (piix) { + info->is_piix4 = true; + } + if (lpc) { + info->is_piix4 = false; + } + info->has_hpet = hpet_find(); info->tpm_version = tpm_get_version(); info->pvpanic_port = pvpanic_port(); @@ -335,6 +330,7 @@ static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm) if (max_cpus > 8) { fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL); } + fadt->century = RTC_CENTURY; } @@ -617,6 +613,23 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, qobject_decref(bsel); } +/** + * build_prt_entry: + * @link_name: link name for PCI route entry + * + * build AML package containing a PCI route entry for @link_name + */ +static Aml *build_prt_entry(const char *link_name) +{ + Aml *a_zero = aml_int(0); + Aml *pkg = aml_package(4); + aml_append(pkg, a_zero); + aml_append(pkg, a_zero); + aml_append(pkg, aml_name("%s", link_name)); + aml_append(pkg, a_zero); + return pkg; +} + /* * initialize_route - Initialize the interrupt routing rule * through a specific LINK: @@ -627,12 +640,8 @@ static Aml *initialize_route(Aml *route, const char *link_name, Aml *lnk_idx, int idx) { Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); - Aml *pkg = aml_package(4); + Aml *pkg = build_prt_entry(link_name); - aml_append(pkg, aml_int(0)); - aml_append(pkg, aml_int(0)); - aml_append(pkg, aml_name("%s", link_name)); - aml_append(pkg, aml_int(0)); aml_append(if_ctx, aml_store(pkg, route)); return if_ctx; @@ -648,7 +657,7 @@ static Aml *initialize_route(Aml *route, const char *link_name, * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". * */ -static Aml *build_prt(void) +static Aml *build_prt(bool is_pci0_prt) { Aml *method, *while_ctx, *pin, *res; @@ -675,7 +684,29 @@ static Aml *build_prt(void) /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); - aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); + if (is_pci0_prt) { + Aml *if_device_1, *if_pin_4, *else_pin_4; + + /* device 1 is the power-management device, needs SCI */ + if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); + { + if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); + { + aml_append(if_pin_4, + aml_store(build_prt_entry("LNKS"), route)); + } + aml_append(if_device_1, if_pin_4); + else_pin_4 = aml_else(); + { + aml_append(else_pin_4, + aml_store(build_prt_entry("LNKA"), route)); + } + aml_append(if_device_1, else_pin_4); + } + aml_append(while_ctx, if_device_1); + } else { + aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); + } aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); @@ -929,6 +960,981 @@ static Aml *build_crs(PCIHostState *host, return crs; } +static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus, + AcpiCpuInfo *cpu, AcpiPmInfo *pm) +{ + int i; + Aml *dev; + Aml *crs; + Aml *pkg; + Aml *field; + Aml *ifctx; + Aml *method; + + /* The current AML generator can cover the APIC ID range [0..255], + * inclusive, for VCPU hotplug. */ + QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); + g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); + + /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ + dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); + aml_append(dev, + aml_name_decl("_UID", aml_string("CPU Hotplug resources")) + ); + /* device present, functioning, decoding, not shown in UI */ + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); + crs = aml_resource_template(); + aml_append(crs, + aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, + pm->cpu_hp_io_len) + ); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(sb_scope, dev); + /* declare CPU hotplug MMIO region and PRS field to access it */ + aml_append(sb_scope, aml_operation_region( + "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); + field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRS", 256)); + aml_append(sb_scope, field); + + /* build Processor object for each processor */ + for (i = 0; i < acpi_cpus; i++) { + dev = aml_processor(i, 0, 0, "CP%.02X", i); + + method = aml_method("_MAT", 0, AML_NOTSERIALIZED); + aml_append(method, + aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i)))); + aml_append(dev, method); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, + aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i)))); + aml_append(dev, method); + + method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); + aml_append(method, + aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0))) + ); + aml_append(dev, method); + + aml_append(sb_scope, dev); + } + + /* build this code: + * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} + */ + /* Arg0 = Processor ID = APIC ID */ + method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); + for (i = 0; i < acpi_cpus; i++) { + ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); + aml_append(ifctx, + aml_notify(aml_name("CP%.02X", i), aml_arg(1)) + ); + aml_append(method, ifctx); + } + aml_append(sb_scope, method); + + /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" + * + * Note: The ability to create variable-sized packages was first + * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages + * ith up to 255 elements. Windows guests up to win2k8 fail when + * VarPackageOp is used. + */ + pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : + aml_varpackage(acpi_cpus); + + for (i = 0; i < acpi_cpus; i++) { + uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; + aml_append(pkg, aml_int(b)); + } + aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg)); +} + +static void build_memory_devices(Aml *sb_scope, int nr_mem, + uint16_t io_base, uint16_t io_len) +{ + int i; + Aml *scope; + Aml *crs; + Aml *field; + Aml *dev; + Aml *method; + Aml *ifctx; + + /* build memory devices */ + assert(nr_mem <= ACPI_MAX_RAM_SLOTS); + scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE); + aml_append(scope, + aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem)) + ); + + crs = aml_resource_template(); + aml_append(crs, + aml_io(AML_DECODE16, io_base, io_base, 0, io_len) + ); + aml_append(scope, aml_name_decl("_CRS", crs)); + + aml_append(scope, aml_operation_region( + MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO, + io_base, io_len) + ); + + field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, + AML_NOLOCK, AML_PRESERVE); + aml_append(field, /* read only */ + aml_named_field(MEMORY_SLOT_ADDR_LOW, 32)); + aml_append(field, /* read only */ + aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32)); + aml_append(field, /* read only */ + aml_named_field(MEMORY_SLOT_SIZE_LOW, 32)); + aml_append(field, /* read only */ + aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32)); + aml_append(field, /* read only */ + aml_named_field(MEMORY_SLOT_PROXIMITY, 32)); + aml_append(scope, field); + + field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC, + AML_NOLOCK, AML_WRITE_AS_ZEROS); + aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); + aml_append(field, /* 1 if enabled, read only */ + aml_named_field(MEMORY_SLOT_ENABLED, 1)); + aml_append(field, + /*(read) 1 if has a insert event. (write) 1 to clear event */ + aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1)); + aml_append(field, + /* (read) 1 if has a remove event. (write) 1 to clear event */ + aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1)); + aml_append(field, + /* initiates device eject, write only */ + aml_named_field(MEMORY_SLOT_EJECT, 1)); + aml_append(scope, field); + + field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC, + AML_NOLOCK, AML_PRESERVE); + aml_append(field, /* DIMM selector, write only */ + aml_named_field(MEMORY_SLOT_SLECTOR, 32)); + aml_append(field, /* _OST event code, write only */ + aml_named_field(MEMORY_SLOT_OST_EVENT, 32)); + aml_append(field, /* _OST status code, write only */ + aml_named_field(MEMORY_SLOT_OST_STATUS, 32)); + aml_append(scope, field); + aml_append(sb_scope, scope); + + for (i = 0; i < nr_mem; i++) { + #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "." + const char *s; + + dev = aml_device("MP%02X", i); + aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); + + method = aml_method("_CRS", 0, AML_NOTSERIALIZED); + s = BASEPATH MEMORY_SLOT_CRS_METHOD; + aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); + aml_append(dev, method); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + s = BASEPATH MEMORY_SLOT_STATUS_METHOD; + aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); + aml_append(dev, method); + + method = aml_method("_PXM", 0, AML_NOTSERIALIZED); + s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD; + aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); + aml_append(dev, method); + + method = aml_method("_OST", 3, AML_NOTSERIALIZED); + s = BASEPATH MEMORY_SLOT_OST_METHOD; + + aml_append(method, aml_return(aml_call4( + s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) + ))); + aml_append(dev, method); + + method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); + s = BASEPATH MEMORY_SLOT_EJECT_METHOD; + aml_append(method, aml_return(aml_call2( + s, aml_name("_UID"), aml_arg(0)))); + aml_append(dev, method); + + aml_append(sb_scope, dev); + } + + /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { + * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } + */ + method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED); + for (i = 0; i < nr_mem; i++) { + ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); + aml_append(ifctx, + aml_notify(aml_name("MP%.02X", i), aml_arg(1)) + ); + aml_append(method, ifctx); + } + aml_append(sb_scope, method); +} + +static void build_hpet_aml(Aml *table) +{ + Aml *crs; + Aml *field; + Aml *method; + Aml *if_ctx; + Aml *scope = aml_scope("_SB"); + Aml *dev = aml_device("HPET"); + Aml *zero = aml_int(0); + Aml *id = aml_local(0); + Aml *period = aml_local(1); + + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); + aml_append(dev, aml_name_decl("_UID", zero)); + + aml_append(dev, + aml_operation_region("HPTM", AML_SYSTEM_MEMORY, HPET_BASE, HPET_LEN)); + field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); + aml_append(field, aml_named_field("VEND", 32)); + aml_append(field, aml_named_field("PRD", 32)); + aml_append(dev, field); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_store(aml_name("VEND"), id)); + aml_append(method, aml_store(aml_name("PRD"), period)); + aml_append(method, aml_shiftright(id, aml_int(16), id)); + if_ctx = aml_if(aml_lor(aml_equal(id, zero), + aml_equal(id, aml_int(0xffff)))); + { + aml_append(if_ctx, aml_return(zero)); + } + aml_append(method, if_ctx); + + if_ctx = aml_if(aml_lor(aml_equal(period, zero), + aml_lgreater(period, aml_int(100000000)))); + { + aml_append(if_ctx, aml_return(zero)); + } + aml_append(method, if_ctx); + + aml_append(method, aml_return(aml_int(0x0F))); + aml_append(dev, method); + + crs = aml_resource_template(); + aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + aml_append(table, scope); +} + +static Aml *build_fdc_device_aml(void) +{ + Aml *dev; + Aml *crs; + Aml *method; + Aml *if_ctx; + Aml *else_ctx; + Aml *zero = aml_int(0); + Aml *is_present = aml_local(0); + + dev = aml_device("FDC0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_store(aml_name("FDEN"), is_present)); + if_ctx = aml_if(aml_equal(is_present, zero)); + { + aml_append(if_ctx, aml_return(aml_int(0x00))); + } + aml_append(method, if_ctx); + else_ctx = aml_else(); + { + aml_append(else_ctx, aml_return(aml_int(0x0f))); + } + aml_append(method, else_ctx); + aml_append(dev, method); + + crs = aml_resource_template(); + aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); + aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); + aml_append(crs, aml_irq_no_flags(6)); + aml_append(crs, + aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + return dev; +} + +static Aml *build_rtc_device_aml(void) +{ + Aml *dev; + Aml *crs; + + dev = aml_device("RTC"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); + crs = aml_resource_template(); + aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); + aml_append(crs, aml_irq_no_flags(8)); + aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + return dev; +} + +static Aml *build_kbd_device_aml(void) +{ + Aml *dev; + Aml *crs; + Aml *method; + + dev = aml_device("KBD"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0f))); + aml_append(dev, method); + + crs = aml_resource_template(); + aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); + aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); + aml_append(crs, aml_irq_no_flags(1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + return dev; +} + +static Aml *build_mouse_device_aml(void) +{ + Aml *dev; + Aml *crs; + Aml *method; + + dev = aml_device("MOU"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0f))); + aml_append(dev, method); + + crs = aml_resource_template(); + aml_append(crs, aml_irq_no_flags(12)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + return dev; +} + +static Aml *build_lpt_device_aml(void) +{ + Aml *dev; + Aml *crs; + Aml *method; + Aml *if_ctx; + Aml *else_ctx; + Aml *zero = aml_int(0); + Aml *is_present = aml_local(0); + + dev = aml_device("LPT"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_store(aml_name("LPEN"), is_present)); + if_ctx = aml_if(aml_equal(is_present, zero)); + { + aml_append(if_ctx, aml_return(aml_int(0x00))); + } + aml_append(method, if_ctx); + else_ctx = aml_else(); + { + aml_append(else_ctx, aml_return(aml_int(0x0f))); + } + aml_append(method, else_ctx); + aml_append(dev, method); + + crs = aml_resource_template(); + aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); + aml_append(crs, aml_irq_no_flags(7)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + return dev; +} + +static Aml *build_com_device_aml(uint8_t uid) +{ + Aml *dev; + Aml *crs; + Aml *method; + Aml *if_ctx; + Aml *else_ctx; + Aml *zero = aml_int(0); + Aml *is_present = aml_local(0); + const char *enabled_field = "CAEN"; + uint8_t irq = 4; + uint16_t io_port = 0x03F8; + + assert(uid == 1 || uid == 2); + if (uid == 2) { + enabled_field = "CBEN"; + irq = 3; + io_port = 0x02F8; + } + + dev = aml_device("COM%d", uid); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); + if_ctx = aml_if(aml_equal(is_present, zero)); + { + aml_append(if_ctx, aml_return(aml_int(0x00))); + } + aml_append(method, if_ctx); + else_ctx = aml_else(); + { + aml_append(else_ctx, aml_return(aml_int(0x0f))); + } + aml_append(method, else_ctx); + aml_append(dev, method); + + crs = aml_resource_template(); + aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); + aml_append(crs, aml_irq_no_flags(irq)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + return dev; +} + +static void build_isa_devices_aml(Aml *table) +{ + Aml *scope = aml_scope("_SB.PCI0.ISA"); + + aml_append(scope, build_rtc_device_aml()); + aml_append(scope, build_kbd_device_aml()); + aml_append(scope, build_mouse_device_aml()); + aml_append(scope, build_fdc_device_aml()); + aml_append(scope, build_lpt_device_aml()); + aml_append(scope, build_com_device_aml(1)); + aml_append(scope, build_com_device_aml(2)); + + aml_append(table, scope); +} + +static void build_dbg_aml(Aml *table) +{ + Aml *field; + Aml *method; + Aml *while_ctx; + Aml *scope = aml_scope("\\"); + Aml *buf = aml_local(0); + Aml *len = aml_local(1); + Aml *idx = aml_local(2); + + aml_append(scope, + aml_operation_region("DBG", AML_SYSTEM_IO, 0x0402, 0x01)); + field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("DBGB", 8)); + aml_append(scope, field); + + method = aml_method("DBUG", 1, AML_NOTSERIALIZED); + + aml_append(method, aml_to_hexstring(aml_arg(0), buf)); + aml_append(method, aml_to_buffer(buf, buf)); + aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); + aml_append(method, aml_store(aml_int(0), idx)); + + while_ctx = aml_while(aml_lless(idx, len)); + aml_append(while_ctx, + aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); + aml_append(while_ctx, aml_increment(idx)); + aml_append(method, while_ctx); + + aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); + aml_append(scope, method); + + aml_append(table, scope); +} + +static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) +{ + Aml *dev; + Aml *crs; + Aml *method; + uint32_t irqs[] = {5, 10, 11}; + + dev = aml_device("%s", name); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); + + crs = aml_resource_template(); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_SHARED, irqs, ARRAY_SIZE(irqs))); + aml_append(dev, aml_name_decl("_PRS", crs)); + + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_call1("IQST", reg))); + aml_append(dev, method); + + method = aml_method("_DIS", 0, AML_NOTSERIALIZED); + aml_append(method, aml_or(reg, aml_int(0x80), reg)); + aml_append(dev, method); + + method = aml_method("_CRS", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_call1("IQCR", reg))); + aml_append(dev, method); + + method = aml_method("_SRS", 1, AML_NOTSERIALIZED); + aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); + aml_append(method, aml_store(aml_name("PRRI"), reg)); + aml_append(dev, method); + + return dev; + } + +static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) +{ + Aml *dev; + Aml *crs; + Aml *method; + uint32_t irqs; + + dev = aml_device("%s", name); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); + aml_append(dev, aml_name_decl("_UID", aml_int(uid))); + + crs = aml_resource_template(); + irqs = gsi; + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_SHARED, &irqs, 1)); + aml_append(dev, aml_name_decl("_PRS", crs)); + + aml_append(dev, aml_name_decl("_CRS", crs)); + + method = aml_method("_SRS", 1, AML_NOTSERIALIZED); + aml_append(dev, method); + + return dev; +} + +/* _CRS method - get current settings */ +static Aml *build_iqcr_method(bool is_piix4) +{ + Aml *if_ctx; + uint32_t irqs; + Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); + Aml *crs = aml_resource_template(); + + irqs = 0; + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, + AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); + aml_append(method, aml_name_decl("PRR0", crs)); + + aml_append(method, + aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); + + if (is_piix4) { + if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); + aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); + aml_append(method, if_ctx); + } else { + aml_append(method, + aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), + aml_name("PRRI"))); + } + + aml_append(method, aml_return(aml_name("PRR0"))); + return method; +} + +/* _STA method - get status */ +static Aml *build_irq_status_method(void) +{ + Aml *if_ctx; + Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); + + if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); + aml_append(if_ctx, aml_return(aml_int(0x09))); + aml_append(method, if_ctx); + aml_append(method, aml_return(aml_int(0x0B))); + return method; +} + +static void build_piix4_pci0_int(Aml *table) +{ + Aml *dev; + Aml *crs; + Aml *field; + Aml *method; + uint32_t irqs; + Aml *sb_scope = aml_scope("_SB"); + Aml *pci0_scope = aml_scope("PCI0"); + + aml_append(pci0_scope, build_prt(true)); + aml_append(sb_scope, pci0_scope); + + field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQ0", 8)); + aml_append(field, aml_named_field("PRQ1", 8)); + aml_append(field, aml_named_field("PRQ2", 8)); + aml_append(field, aml_named_field("PRQ3", 8)); + aml_append(sb_scope, field); + + aml_append(sb_scope, build_irq_status_method()); + aml_append(sb_scope, build_iqcr_method(true)); + + aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); + aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); + aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); + aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); + + dev = aml_device("LNKS"); + { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); + aml_append(dev, aml_name_decl("_UID", aml_int(4))); + + crs = aml_resource_template(); + irqs = 9; + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, + AML_ACTIVE_HIGH, AML_SHARED, + &irqs, 1)); + aml_append(dev, aml_name_decl("_PRS", crs)); + + /* The SCI cannot be disabled and is always attached to GSI 9, + * so these are no-ops. We only need this link to override the + * polarity to active high and match the content of the MADT. + */ + method = aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0b))); + aml_append(dev, method); + + method = aml_method("_DIS", 0, AML_NOTSERIALIZED); + aml_append(dev, method); + + method = aml_method("_CRS", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_name("_PRS"))); + aml_append(dev, method); + + method = aml_method("_SRS", 1, AML_NOTSERIALIZED); + aml_append(dev, method); + } + aml_append(sb_scope, dev); + + aml_append(table, sb_scope); +} + +static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) +{ + int i; + int head; + Aml *pkg; + char base = name[3] < 'E' ? 'A' : 'E'; + char *s = g_strdup(name); + Aml *a_nr = aml_int((nr << 16) | 0xffff); + + assert(strlen(s) == 4); + + head = name[3] - base; + for (i = 0; i < 4; i++) { + if (head + i > 3) { + head = i * -1; + } + s[3] = base + head + i; + pkg = aml_package(4); + aml_append(pkg, a_nr); + aml_append(pkg, aml_int(i)); + aml_append(pkg, aml_name("%s", s)); + aml_append(pkg, aml_int(0)); + aml_append(ctx, pkg); + } + g_free(s); +} + +static Aml *build_q35_routing_table(const char *str) +{ + int i; + Aml *pkg; + char *name = g_strdup_printf("%s ", str); + + pkg = aml_package(128); + for (i = 0; i < 0x18; i++) { + name[3] = 'E' + (i & 0x3); + append_q35_prt_entry(pkg, i, name); + } + + name[3] = 'E'; + append_q35_prt_entry(pkg, 0x18, name); + + /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ + for (i = 0x0019; i < 0x1e; i++) { + name[3] = 'A'; + append_q35_prt_entry(pkg, i, name); + } + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + name[3] = 'E'; + append_q35_prt_entry(pkg, 0x1e, name); + name[3] = 'A'; + append_q35_prt_entry(pkg, 0x1f, name); + + g_free(name); + return pkg; +} + +static void build_q35_pci0_int(Aml *table) +{ + Aml *field; + Aml *method; + Aml *sb_scope = aml_scope("_SB"); + Aml *pci0_scope = aml_scope("PCI0"); + + /* Zero => PIC mode, One => APIC Mode */ + aml_append(table, aml_name_decl("PICF", aml_int(0))); + method = aml_method("_PIC", 1, AML_NOTSERIALIZED); + { + aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); + } + aml_append(table, method); + + aml_append(pci0_scope, + aml_name_decl("PRTP", build_q35_routing_table("LNK"))); + aml_append(pci0_scope, + aml_name_decl("PRTA", build_q35_routing_table("GSI"))); + + method = aml_method("_PRT", 0, AML_NOTSERIALIZED); + { + Aml *if_ctx; + Aml *else_ctx; + + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ + if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); + aml_append(if_ctx, aml_return(aml_name("PRTP"))); + aml_append(method, if_ctx); + else_ctx = aml_else(); + aml_append(else_ctx, aml_return(aml_name("PRTA"))); + aml_append(method, else_ctx); + } + aml_append(pci0_scope, method); + aml_append(sb_scope, pci0_scope); + + field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQA", 8)); + aml_append(field, aml_named_field("PRQB", 8)); + aml_append(field, aml_named_field("PRQC", 8)); + aml_append(field, aml_named_field("PRQD", 8)); + aml_append(field, aml_reserved_field(0x20)); + aml_append(field, aml_named_field("PRQE", 8)); + aml_append(field, aml_named_field("PRQF", 8)); + aml_append(field, aml_named_field("PRQG", 8)); + aml_append(field, aml_named_field("PRQH", 8)); + aml_append(sb_scope, field); + + aml_append(sb_scope, build_irq_status_method()); + aml_append(sb_scope, build_iqcr_method(false)); + + aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); + aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); + aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); + aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); + aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); + aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); + aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); + aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); + + /* + * TODO: UID probably shouldn't be the same for GSIx devices + * but that's how it was in original ASL so keep it for now + */ + aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10)); + aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11)); + aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12)); + aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13)); + aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14)); + aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15)); + aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16)); + aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17)); + + aml_append(table, sb_scope); +} + +static void build_q35_isa_bridge(Aml *table) +{ + Aml *dev; + Aml *scope; + Aml *field; + + scope = aml_scope("_SB.PCI0"); + dev = aml_device("ISA"); + aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); + + /* ICH9 PCI to ISA irq remapping */ + aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, + 0x60, 0x0C)); + + aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, + 0x80, 0x02)); + field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("COMA", 3)); + aml_append(field, aml_reserved_field(1)); + aml_append(field, aml_named_field("COMB", 3)); + aml_append(field, aml_reserved_field(1)); + aml_append(field, aml_named_field("LPTD", 2)); + aml_append(field, aml_reserved_field(2)); + aml_append(field, aml_named_field("FDCD", 2)); + aml_append(dev, field); + + aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, + 0x82, 0x02)); + /* enable bits */ + field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("CAEN", 1)); + aml_append(field, aml_named_field("CBEN", 1)); + aml_append(field, aml_named_field("LPEN", 1)); + aml_append(field, aml_named_field("FDEN", 1)); + aml_append(dev, field); + + aml_append(scope, dev); + aml_append(table, scope); +} + +static void build_piix4_pm(Aml *table) +{ + Aml *dev; + Aml *scope; + + scope = aml_scope("_SB.PCI0"); + dev = aml_device("PX13"); + aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); + + aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, + 0x00, 0xff)); + aml_append(scope, dev); + aml_append(table, scope); +} + +static void build_piix4_isa_bridge(Aml *table) +{ + Aml *dev; + Aml *scope; + Aml *field; + + scope = aml_scope("_SB.PCI0"); + dev = aml_device("ISA"); + aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); + + /* PIIX PCI to ISA irq remapping */ + aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, + 0x60, 0x04)); + /* enable bits */ + field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + /* Offset(0x5f),, 7, */ + aml_append(field, aml_reserved_field(0x2f8)); + aml_append(field, aml_reserved_field(7)); + aml_append(field, aml_named_field("LPEN", 1)); + /* Offset(0x67),, 3, */ + aml_append(field, aml_reserved_field(0x38)); + aml_append(field, aml_reserved_field(3)); + aml_append(field, aml_named_field("CAEN", 1)); + aml_append(field, aml_reserved_field(3)); + aml_append(field, aml_named_field("CBEN", 1)); + aml_append(dev, field); + aml_append(dev, aml_name_decl("FDEN", aml_int(1))); + + aml_append(scope, dev); + aml_append(table, scope); +} + +static void build_piix4_pci_hotplug(Aml *table) +{ + Aml *scope; + Aml *field; + Aml *method; + + scope = aml_scope("_SB.PCI0"); + + aml_append(scope, + aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x08)); + field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); + aml_append(field, aml_named_field("PCIU", 32)); + aml_append(field, aml_named_field("PCID", 32)); + aml_append(scope, field); + + aml_append(scope, + aml_operation_region("SEJ", AML_SYSTEM_IO, 0xae08, 0x04)); + field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); + aml_append(field, aml_named_field("B0EJ", 32)); + aml_append(scope, field); + + aml_append(scope, + aml_operation_region("BNMR", AML_SYSTEM_IO, 0xae10, 0x04)); + field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); + aml_append(field, aml_named_field("BNUM", 32)); + aml_append(scope, field); + + aml_append(scope, aml_mutex("BLCK", 0)); + + method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); + aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); + aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); + aml_append(method, + aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); + aml_append(method, aml_release(aml_name("BLCK"))); + aml_append(method, aml_return(aml_int(0))); + aml_append(scope, method); + + aml_append(table, scope); +} + +static Aml *build_q35_osc_method(void) +{ + Aml *if_ctx; + Aml *if_ctx2; + Aml *else_ctx; + Aml *method; + Aml *a_cwd1 = aml_name("CDW1"); + Aml *a_ctrl = aml_name("CTRL"); + + method = aml_method("_OSC", 4, AML_NOTSERIALIZED); + aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); + + if_ctx = aml_if(aml_equal( + aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); + + aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); + aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); + + /* + * Always allow native PME, AER (no dependencies) + * Never allow SHPC (no SHPC controller in this system) + */ + aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl)); + + if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); + /* Unknown revision */ + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); + aml_append(if_ctx, if_ctx2); + + if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); + /* Capabilities bits were masked */ + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); + aml_append(if_ctx, if_ctx2); + + /* Update DWORD3 in the buffer */ + aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); + aml_append(method, if_ctx); + + else_ctx = aml_else(); + /* Unrecognized UUID */ + aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); + aml_append(method, else_ctx); + + aml_append(method, aml_return(aml_arg(3))); + return method; +} + static void build_ssdt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, @@ -936,8 +1942,7 @@ build_ssdt(GArray *table_data, GArray *linker, { MachineState *machine = MACHINE(qdev_get_machine()); uint32_t nr_mem = machine->ram_slots; - unsigned acpi_cpus = guest_info->apic_id_limit; - Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; + Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field; PCIBus *bus = NULL; GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free); GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); @@ -946,10 +1951,6 @@ build_ssdt(GArray *table_data, GArray *linker, int i; ssdt = init_aml_allocator(); - /* The current AML generator can cover the APIC ID range [0..255], - * inclusive, for VCPU hotplug. */ - QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256); - g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT); /* Reserve space for header */ acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader)); @@ -979,7 +1980,7 @@ build_ssdt(GArray *table_data, GArray *linker, aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); } - aml_append(dev, build_prt()); + aml_append(dev, build_prt(false)); crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), io_ranges, mem_ranges); aml_append(dev, aml_name_decl("_CRS", crs)); @@ -1155,192 +2156,10 @@ build_ssdt(GArray *table_data, GArray *linker, sb_scope = aml_scope("\\_SB"); { - /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */ - dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE)); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); - aml_append(dev, - aml_name_decl("_UID", aml_string("CPU Hotplug resources")) - ); - /* device present, functioning, decoding, not shown in UI */ - aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); - crs = aml_resource_template(); - aml_append(crs, - aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1, - pm->cpu_hp_io_len) - ); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(sb_scope, dev); - /* declare CPU hotplug MMIO region and PRS field to access it */ - aml_append(sb_scope, aml_operation_region( - "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len)); - field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); - aml_append(field, aml_named_field("PRS", 256)); - aml_append(sb_scope, field); + build_processor_devices(sb_scope, guest_info->apic_id_limit, cpu, pm); - /* build Processor object for each processor */ - for (i = 0; i < acpi_cpus; i++) { - dev = aml_processor(i, 0, 0, "CP%.02X", i); - - method = aml_method("_MAT", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_call1("CPMA", aml_int(i)))); - aml_append(dev, method); - - method = aml_method("_STA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_call1("CPST", aml_int(i)))); - aml_append(dev, method); - - method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); - aml_append(method, - aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0))) - ); - aml_append(dev, method); - - aml_append(sb_scope, dev); - } - - /* build this code: - * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...} - */ - /* Arg0 = Processor ID = APIC ID */ - method = aml_method("NTFY", 2, AML_NOTSERIALIZED); - for (i = 0; i < acpi_cpus; i++) { - ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); - aml_append(ifctx, - aml_notify(aml_name("CP%.02X", i), aml_arg(1)) - ); - aml_append(method, ifctx); - } - aml_append(sb_scope, method); - - /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" - * - * Note: The ability to create variable-sized packages was first - * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages - * ith up to 255 elements. Windows guests up to win2k8 fail when - * VarPackageOp is used. - */ - pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) : - aml_varpackage(acpi_cpus); - - for (i = 0; i < acpi_cpus; i++) { - uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00; - aml_append(pkg, aml_int(b)); - } - aml_append(sb_scope, aml_name_decl("CPON", pkg)); - - /* build memory devices */ - assert(nr_mem <= ACPI_MAX_RAM_SLOTS); - scope = aml_scope("\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE)); - aml_append(scope, - aml_name_decl(stringify(MEMORY_SLOTS_NUMBER), aml_int(nr_mem)) - ); - - crs = aml_resource_template(); - aml_append(crs, - aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0, - pm->mem_hp_io_len) - ); - aml_append(scope, aml_name_decl("_CRS", crs)); - - aml_append(scope, aml_operation_region( - stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO, - pm->mem_hp_io_base, pm->mem_hp_io_len) - ); - - field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, - AML_NOLOCK, AML_PRESERVE); - aml_append(field, /* read only */ - aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32)); - aml_append(field, /* read only */ - aml_named_field(stringify(MEMORY_SLOT_ADDR_HIGH), 32)); - aml_append(field, /* read only */ - aml_named_field(stringify(MEMORY_SLOT_SIZE_LOW), 32)); - aml_append(field, /* read only */ - aml_named_field(stringify(MEMORY_SLOT_SIZE_HIGH), 32)); - aml_append(field, /* read only */ - aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32)); - aml_append(scope, field); - - field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC, - AML_NOLOCK, AML_WRITE_AS_ZEROS); - aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */)); - aml_append(field, /* 1 if enabled, read only */ - aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1)); - aml_append(field, - /*(read) 1 if has a insert event. (write) 1 to clear event */ - aml_named_field(stringify(MEMORY_SLOT_INSERT_EVENT), 1)); - aml_append(field, - /* (read) 1 if has a remove event. (write) 1 to clear event */ - aml_named_field(stringify(MEMORY_SLOT_REMOVE_EVENT), 1)); - aml_append(field, - /* initiates device eject, write only */ - aml_named_field(stringify(MEMORY_SLOT_EJECT), 1)); - aml_append(scope, field); - - field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC, - AML_NOLOCK, AML_PRESERVE); - aml_append(field, /* DIMM selector, write only */ - aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32)); - aml_append(field, /* _OST event code, write only */ - aml_named_field(stringify(MEMORY_SLOT_OST_EVENT), 32)); - aml_append(field, /* _OST status code, write only */ - aml_named_field(stringify(MEMORY_SLOT_OST_STATUS), 32)); - aml_append(scope, field); - - aml_append(sb_scope, scope); - - for (i = 0; i < nr_mem; i++) { - #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "." - const char *s; - - dev = aml_device("MP%02X", i); - aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i))); - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80"))); - - method = aml_method("_CRS", 0, AML_NOTSERIALIZED); - s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD); - aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); - aml_append(dev, method); - - method = aml_method("_STA", 0, AML_NOTSERIALIZED); - s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD); - aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); - aml_append(dev, method); - - method = aml_method("_PXM", 0, AML_NOTSERIALIZED); - s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD); - aml_append(method, aml_return(aml_call1(s, aml_name("_UID")))); - aml_append(dev, method); - - method = aml_method("_OST", 3, AML_NOTSERIALIZED); - s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD); - aml_append(method, aml_return(aml_call4( - s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2) - ))); - aml_append(dev, method); - - method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); - s = BASEPATH stringify(MEMORY_SLOT_EJECT_METHOD); - aml_append(method, aml_return(aml_call2( - s, aml_name("_UID"), aml_arg(0)))); - aml_append(dev, method); - - aml_append(sb_scope, dev); - } - - /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) { - * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... } - */ - method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2, - AML_NOTSERIALIZED); - for (i = 0; i < nr_mem; i++) { - ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i))); - aml_append(ifctx, - aml_notify(aml_name("MP%.02X", i), aml_arg(1)) - ); - aml_append(method, ifctx); - } - aml_append(sb_scope, method); + build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base, + pm->mem_hp_io_len); { Object *pci_host; @@ -1605,18 +2424,113 @@ build_dmar_q35(GArray *table_data, GArray *linker) } static void -build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) +build_dsdt(GArray *table_data, GArray *linker, + AcpiPmInfo *pm, AcpiMiscInfo *misc) { - AcpiTableHeader *dsdt; + Aml *dsdt, *sb_scope, *scope, *dev, *method, *field; + MachineState *machine = MACHINE(qdev_get_machine()); + uint32_t nr_mem = machine->ram_slots; + + dsdt = init_aml_allocator(); - assert(misc->dsdt_code && misc->dsdt_size); + /* Reserve space for header */ + acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); + + build_dbg_aml(dsdt); + if (misc->is_piix4) { + sb_scope = aml_scope("_SB"); + dev = aml_device("PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(sb_scope, dev); + aml_append(dsdt, sb_scope); + + build_hpet_aml(dsdt); + build_piix4_pm(dsdt); + build_piix4_isa_bridge(dsdt); + build_isa_devices_aml(dsdt); + build_piix4_pci_hotplug(dsdt); + build_piix4_pci0_int(dsdt); + } else { + sb_scope = aml_scope("_SB"); + aml_append(sb_scope, + aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x0c)); + aml_append(sb_scope, + aml_operation_region("PCSB", AML_SYSTEM_IO, 0xae0c, 0x01)); + field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); + aml_append(field, aml_named_field("PCIB", 8)); + aml_append(sb_scope, field); + aml_append(dsdt, sb_scope); + + sb_scope = aml_scope("_SB"); + dev = aml_device("PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_q35_osc_method()); + aml_append(sb_scope, dev); + aml_append(dsdt, sb_scope); + + build_hpet_aml(dsdt); + build_q35_isa_bridge(dsdt); + build_isa_devices_aml(dsdt); + build_q35_pci0_int(dsdt); + } - dsdt = acpi_data_push(table_data, misc->dsdt_size); - memcpy(dsdt, misc->dsdt_code, misc->dsdt_size); + build_cpu_hotplug_aml(dsdt); + build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base, + pm->mem_hp_io_len); - memset(dsdt, 0, sizeof *dsdt); - build_header(linker, table_data, dsdt, "DSDT", - misc->dsdt_size, 1, NULL); + scope = aml_scope("_GPE"); + { + aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); + + aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED)); + + if (misc->is_piix4) { + method = aml_method("_E01", 0, AML_NOTSERIALIZED); + aml_append(method, + aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); + aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); + aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); + aml_append(scope, method); + } else { + aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED)); + } + + method = aml_method("_E02", 0, AML_NOTSERIALIZED); + aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD)); + aml_append(scope, method); + + method = aml_method("_E03", 0, AML_NOTSERIALIZED); + aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH)); + aml_append(scope, method); + + aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED)); + aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED)); + } + aml_append(dsdt, scope); + + /* copy AML table into ACPI tables blob and patch header there */ + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); + build_header(linker, table_data, + (void *)(table_data->data + table_data->len - dsdt->buf->len), + "DSDT", dsdt->buf->len, 1, NULL); + free_aml_allocator(); } static GArray * @@ -1710,7 +2624,6 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) acpi_get_cpu_info(&cpu); acpi_get_pm_info(&pm); - acpi_get_dsdt(&misc); acpi_get_misc_info(&misc); acpi_get_pci_info(&pci); @@ -1732,7 +2645,7 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) /* DSDT is pointed to by FADT */ dsdt = tables_blob->len; - build_dsdt(tables_blob, tables->linker, &misc); + build_dsdt(tables_blob, tables->linker, &pm, &misc); /* Count the size of the DSDT and SSDT, we will need it for legacy * sizing of ACPI tables. diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl b/hw/i386/acpi-dsdt-cpu-hotplug.dsl deleted file mode 100644 index 1aff74627f..0000000000 --- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/**************************************************************** - * CPU hotplug - ****************************************************************/ - -Scope(\_SB) { - /* Objects filled in by run-time generated SSDT */ - External(NTFY, MethodObj) - External(CPON, PkgObj) - External(PRS, FieldUnitObj) - - /* Methods called by run-time generated SSDT Processor objects */ - Method(CPMA, 1, NotSerialized) { - // _MAT method - create an madt apic buffer - // Arg0 = Processor ID = Local APIC ID - // Local0 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Arg0)), Local0) - // Local1 = Buffer (in madt apic form) to return - Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) - // Update the processor id, lapic id, and enable/disable status - Store(Arg0, Index(Local1, 2)) - Store(Arg0, Index(Local1, 3)) - Store(Local0, Index(Local1, 4)) - Return (Local1) - } - Method(CPST, 1, NotSerialized) { - // _STA method - return ON status of cpu - // Arg0 = Processor ID = Local APIC ID - // Local0 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Arg0)), Local0) - If (Local0) { - Return (0xF) - } Else { - Return (0x0) - } - } - Method(CPEJ, 2, NotSerialized) { - // _EJ0 method - eject callback - Sleep(200) - } - -#define CPU_STATUS_LEN ACPI_GPE_PROC_LEN - Method(PRSC, 0) { - // Local5 = active cpu bitmap - Store(PRS, Local5) - // Local2 = last read byte from bitmap - Store(Zero, Local2) - // Local0 = Processor ID / APIC ID iterator - Store(Zero, Local0) - While (LLess(Local0, SizeOf(CPON))) { - // Local1 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Local0)), Local1) - If (And(Local0, 0x07)) { - // Shift down previously read bitmap byte - ShiftRight(Local2, 1, Local2) - } Else { - // Read next byte from cpu bitmap - Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2) - } - // Local3 = active state for this cpu - Store(And(Local2, 1), Local3) - - If (LNotEqual(Local1, Local3)) { - // State change - update CPON with new state - Store(Local3, Index(CPON, Local0)) - // Do CPU notify - If (LEqual(Local3, 1)) { - NTFY(Local0, 1) - } Else { - NTFY(Local0, 3) - } - } - Increment(Local0) - } - } -} diff --git a/hw/i386/acpi-dsdt-dbug.dsl b/hw/i386/acpi-dsdt-dbug.dsl deleted file mode 100644 index 86230f75a0..0000000000 --- a/hw/i386/acpi-dsdt-dbug.dsl +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/**************************************************************** - * Debugging - ****************************************************************/ - -Scope(\) { - /* Debug Output */ - OperationRegion(DBG, SystemIO, 0x0402, 0x01) - Field(DBG, ByteAcc, NoLock, Preserve) { - DBGB, 8, - } - - /* Debug method - use this method to send output to the QEMU - * BIOS debug port. This method handles strings, integers, - * and buffers. For example: DBUG("abc") DBUG(0x123) */ - Method(DBUG, 1) { - ToHexString(Arg0, Local0) - ToBuffer(Local0, Local0) - Subtract(SizeOf(Local0), 1, Local1) - Store(Zero, Local2) - While (LLess(Local2, Local1)) { - Store(DerefOf(Index(Local0, Local2)), DBGB) - Increment(Local2) - } - Store(0x0A, DBGB) - } -} diff --git a/hw/i386/acpi-dsdt-hpet.dsl b/hw/i386/acpi-dsdt-hpet.dsl deleted file mode 100644 index 44961b87a1..0000000000 --- a/hw/i386/acpi-dsdt-hpet.dsl +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/**************************************************************** - * HPET - ****************************************************************/ - -Scope(\_SB) { - Device(HPET) { - Name(_HID, EISAID("PNP0103")) - Name(_UID, 0) - OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400) - Field(HPTM, DWordAcc, Lock, Preserve) { - VEND, 32, - PRD, 32, - } - Method(_STA, 0, NotSerialized) { - Store(VEND, Local0) - Store(PRD, Local1) - ShiftRight(Local0, 16, Local0) - If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) { - Return (0x0) - } - If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) { - Return (0x0) - } - Return (0x0F) - } - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, - 0xFED00000, // Address Base - 0x00000400, // Address Length - ) - }) - } -} diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl deleted file mode 100644 index 89caa1649d..0000000000 --- a/hw/i386/acpi-dsdt-isa.dsl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/* Common legacy ISA style devices. */ -Scope(\_SB.PCI0.ISA) { - - Device(RTC) { - Name(_HID, EisaId("PNP0B00")) - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0070, 0x0070, 0x10, 0x02) - IRQNoFlags() { 8 } - IO(Decode16, 0x0072, 0x0072, 0x02, 0x06) - }) - } - - Device(KBD) { - Name(_HID, EisaId("PNP0303")) - Method(_STA, 0, NotSerialized) { - Return (0x0f) - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO(Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags() { 1 } - }) - } - - Device(MOU) { - Name(_HID, EisaId("PNP0F13")) - Method(_STA, 0, NotSerialized) { - Return (0x0f) - } - Name(_CRS, ResourceTemplate() { - IRQNoFlags() { 12 } - }) - } - - Device(FDC0) { - Name(_HID, EisaId("PNP0700")) - Method(_STA, 0, NotSerialized) { - Store(FDEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04) - IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01) - IRQNoFlags() { 6 } - DMA(Compatibility, NotBusMaster, Transfer8) { 2 } - }) - } - - Device(LPT) { - Name(_HID, EisaId("PNP0400")) - Method(_STA, 0, NotSerialized) { - Store(LPEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0378, 0x0378, 0x08, 0x08) - IRQNoFlags() { 7 } - }) - } - - Device(COM1) { - Name(_HID, EisaId("PNP0501")) - Name(_UID, 0x01) - Method(_STA, 0, NotSerialized) { - Store(CAEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08) - IRQNoFlags() { 4 } - }) - } - - Device(COM2) { - Name(_HID, EisaId("PNP0501")) - Name(_UID, 0x02) - Method(_STA, 0, NotSerialized) { - Store(CBEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x02F8, 0x02F8, 0x00, 0x08) - IRQNoFlags() { 3 } - }) - } -} diff --git a/hw/i386/acpi-dsdt-mem-hotplug.dsl b/hw/i386/acpi-dsdt-mem-hotplug.dsl deleted file mode 100644 index c2bb6a1602..0000000000 --- a/hw/i386/acpi-dsdt-mem-hotplug.dsl +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - - External(MEMORY_SLOT_NOTIFY_METHOD, MethodObj) - - Scope(\_SB.PCI0) { - Device(MEMORY_HOTPLUG_DEVICE) { - Name(_HID, "PNP0A06") - Name(_UID, "Memory hotplug resources") - External(MEMORY_SLOTS_NUMBER, IntObj) - - /* Memory hotplug IO registers */ - External(MEMORY_SLOT_ADDR_LOW, FieldUnitObj) // read only - External(MEMORY_SLOT_ADDR_HIGH, FieldUnitObj) // read only - External(MEMORY_SLOT_SIZE_LOW, FieldUnitObj) // read only - External(MEMORY_SLOT_SIZE_HIGH, FieldUnitObj) // read only - External(MEMORY_SLOT_PROXIMITY, FieldUnitObj) // read only - External(MEMORY_SLOT_ENABLED, FieldUnitObj) // 1 if enabled, read only - External(MEMORY_SLOT_INSERT_EVENT, FieldUnitObj) // (read) 1 if has a insert event. (write) 1 to clear event - External(MEMORY_SLOT_REMOVE_EVENT, FieldUnitObj) // (read) 1 if has a remove event. (write) 1 to clear event - External(MEMORY_SLOT_EJECT, FieldUnitObj) // initiates device eject, write only - External(MEMORY_SLOT_SLECTOR, FieldUnitObj) // DIMM selector, write only - External(MEMORY_SLOT_OST_EVENT, FieldUnitObj) // _OST event code, write only - External(MEMORY_SLOT_OST_STATUS, FieldUnitObj) // _OST status code, write only - - Method(_STA, 0) { - If (LEqual(MEMORY_SLOTS_NUMBER, Zero)) { - Return(0x0) - } - /* present, functioning, decoding, not shown in UI */ - Return(0xB) - } - - Mutex (MEMORY_SLOT_LOCK, 0) - - Method(MEMORY_SLOT_SCAN_METHOD, 0) { - If (LEqual(MEMORY_SLOTS_NUMBER, Zero)) { - Return(Zero) - } - - Store(Zero, Local0) // Mem devs iterrator - Acquire(MEMORY_SLOT_LOCK, 0xFFFF) - while (LLess(Local0, MEMORY_SLOTS_NUMBER)) { - Store(Local0, MEMORY_SLOT_SLECTOR) // select Local0 DIMM - If (LEqual(MEMORY_SLOT_INSERT_EVENT, One)) { // Memory device needs check - MEMORY_SLOT_NOTIFY_METHOD(Local0, 1) - Store(1, MEMORY_SLOT_INSERT_EVENT) - } Elseif (LEqual(MEMORY_SLOT_REMOVE_EVENT, One)) { // Ejection request - MEMORY_SLOT_NOTIFY_METHOD(Local0, 3) - Store(1, MEMORY_SLOT_REMOVE_EVENT) - } - Add(Local0, One, Local0) // goto next DIMM - } - Release(MEMORY_SLOT_LOCK) - Return(One) - } - - Method(MEMORY_SLOT_STATUS_METHOD, 1) { - Store(Zero, Local0) - - Acquire(MEMORY_SLOT_LOCK, 0xFFFF) - Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM - - If (LEqual(MEMORY_SLOT_ENABLED, One)) { - Store(0xF, Local0) - } - - Release(MEMORY_SLOT_LOCK) - Return(Local0) - } - - Method(MEMORY_SLOT_CRS_METHOD, 1, Serialized) { - Acquire(MEMORY_SLOT_LOCK, 0xFFFF) - Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM - - Name(MR64, ResourceTemplate() { - QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x0000000000000000, // Address Space Granularity - 0x0000000000000000, // Address Range Minimum - 0xFFFFFFFFFFFFFFFE, // Address Range Maximum - 0x0000000000000000, // Address Translation Offset - 0xFFFFFFFFFFFFFFFF, // Address Length - ,, MW64, AddressRangeMemory, TypeStatic) - }) - - CreateDWordField(MR64, 14, MINL) - CreateDWordField(MR64, 18, MINH) - CreateDWordField(MR64, 38, LENL) - CreateDWordField(MR64, 42, LENH) - CreateDWordField(MR64, 22, MAXL) - CreateDWordField(MR64, 26, MAXH) - - Store(MEMORY_SLOT_ADDR_HIGH, MINH) - Store(MEMORY_SLOT_ADDR_LOW, MINL) - Store(MEMORY_SLOT_SIZE_HIGH, LENH) - Store(MEMORY_SLOT_SIZE_LOW, LENL) - - // 64-bit math: MAX = MIN + LEN - 1 - Add(MINL, LENL, MAXL) - Add(MINH, LENH, MAXH) - If (LLess(MAXL, MINL)) { - Add(MAXH, One, MAXH) - } - If (LLess(MAXL, One)) { - Subtract(MAXH, One, MAXH) - } - Subtract(MAXL, One, MAXL) - - If (LEqual(MAXH, Zero)){ - Name(MR32, ResourceTemplate() { - DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x00000000, // Address Range Minimum - 0xFFFFFFFE, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0xFFFFFFFF, // Address Length - ,, MW32, AddressRangeMemory, TypeStatic) - }) - CreateDWordField(MR32, MW32._MIN, MIN) - CreateDWordField(MR32, MW32._MAX, MAX) - CreateDWordField(MR32, MW32._LEN, LEN) - Store(MINL, MIN) - Store(MAXL, MAX) - Store(LENL, LEN) - - Release(MEMORY_SLOT_LOCK) - Return(MR32) - } - - Release(MEMORY_SLOT_LOCK) - Return(MR64) - } - - Method(MEMORY_SLOT_PROXIMITY_METHOD, 1) { - Acquire(MEMORY_SLOT_LOCK, 0xFFFF) - Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM - Store(MEMORY_SLOT_PROXIMITY, Local0) - Release(MEMORY_SLOT_LOCK) - Return(Local0) - } - - Method(MEMORY_SLOT_OST_METHOD, 4) { - Acquire(MEMORY_SLOT_LOCK, 0xFFFF) - Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM - Store(Arg1, MEMORY_SLOT_OST_EVENT) - Store(Arg2, MEMORY_SLOT_OST_STATUS) - Release(MEMORY_SLOT_LOCK) - } - - Method(MEMORY_SLOT_EJECT_METHOD, 2) { - Acquire(MEMORY_SLOT_LOCK, 0xFFFF) - Store(ToInteger(Arg0), MEMORY_SLOT_SLECTOR) // select DIMM - Store(1, MEMORY_SLOT_EJECT) - Release(MEMORY_SLOT_LOCK) - } - } // Device() - } // Scope() diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl deleted file mode 100644 index 8dba096dd8..0000000000 --- a/hw/i386/acpi-dsdt.dsl +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Bochs/QEMU ACPI DSDT ASL definition - * - * Copyright (c) 2006 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License version 2 as published by the Free Software Foundation. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -ACPI_EXTRACT_ALL_CODE AcpiDsdtAmlCode - -DefinitionBlock ( - "acpi-dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision - "BXPC", // OEMID - "BXDSDT", // TABLE ID - 0x1 // OEM Revision - ) -{ - -#include "acpi-dsdt-dbug.dsl" - - Scope(\_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) -//#define PX13 S0B_ -// External(PX13, DeviceObj) - } - } - -#include "acpi-dsdt-hpet.dsl" - -/**************************************************************** - * PIIX4 PM - ****************************************************************/ - - Scope(\_SB.PCI0) { - Device(PX13) { - Name(_ADR, 0x00010003) - OperationRegion(P13C, PCI_Config, 0x00, 0xff) - } - } - - -/**************************************************************** - * PIIX3 ISA bridge - ****************************************************************/ - - Scope(\_SB.PCI0) { - - External(ISA, DeviceObj) - - Device(ISA) { - Name(_ADR, 0x00010000) - - /* PIIX PCI to ISA irq remapping */ - OperationRegion(P40C, PCI_Config, 0x60, 0x04) - - /* enable bits */ - Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) { - Offset(0x5f), - , 7, - LPEN, 1, // LPT - Offset(0x67), - , 3, - CAEN, 1, // COM1 - , 3, - CBEN, 1, // COM2 - } - Name(FDEN, 1) - } - } - -#include "acpi-dsdt-isa.dsl" - - -/**************************************************************** - * PCI hotplug - ****************************************************************/ - - Scope(\_SB.PCI0) { - OperationRegion(PCST, SystemIO, 0xae00, 0x08) - Field(PCST, DWordAcc, NoLock, WriteAsZeros) { - PCIU, 32, - PCID, 32, - } - - OperationRegion(SEJ, SystemIO, 0xae08, 0x04) - Field(SEJ, DWordAcc, NoLock, WriteAsZeros) { - B0EJ, 32, - } - - OperationRegion(BNMR, SystemIO, 0xae10, 0x04) - Field(BNMR, DWordAcc, NoLock, WriteAsZeros) { - BNUM, 32, - } - - /* Lock to protect access to fields above. */ - Mutex(BLCK, 0) - - /* Methods called by bulk generated PCI devices below */ - - /* Methods called by hotplug devices */ - Method(PCEJ, 2, NotSerialized) { - // _EJ0 method - eject callback - Acquire(BLCK, 0xFFFF) - Store(Arg0, BNUM) - Store(ShiftLeft(1, Arg1), B0EJ) - Release(BLCK) - Return (0x0) - } - - /* Hotplug notification method supplied by SSDT */ - External(\_SB.PCI0.PCNT, MethodObj) - } - - -/**************************************************************** - * PCI IRQs - ****************************************************************/ - - Scope(\_SB) { - Scope(PCI0) { - Method (_PRT, 0) { - Store(Package(128) {}, Local0) - Store(Zero, Local1) - While(LLess(Local1, 128)) { - // slot = pin >> 2 - Store(ShiftRight(Local1, 2), Local2) - - // lnk = (slot + pin) & 3 - Store(And(Add(Local1, Local2), 3), Local3) - If (LEqual(Local3, 0)) { - Store(Package(4) { Zero, Zero, LNKD, Zero }, Local4) - } - If (LEqual(Local3, 1)) { - // device 1 is the power-management device, needs SCI - If (LEqual(Local1, 4)) { - Store(Package(4) { Zero, Zero, LNKS, Zero }, Local4) - } Else { - Store(Package(4) { Zero, Zero, LNKA, Zero }, Local4) - } - } - If (LEqual(Local3, 2)) { - Store(Package(4) { Zero, Zero, LNKB, Zero }, Local4) - } - If (LEqual(Local3, 3)) { - Store(Package(4) { Zero, Zero, LNKC, Zero }, Local4) - } - - // Complete the interrupt routing entry: - // Package(4) { 0x[slot]FFFF, [pin], [link], 0) } - - Store(Or(ShiftLeft(Local2, 16), 0xFFFF), Index(Local4, 0)) - Store(And(Local1, 3), Index(Local4, 1)) - Store(Local4, Index(Local0, Local1)) - - Increment(Local1) - } - - Return(Local0) - } - } - - Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) { - PRQ0, 8, - PRQ1, 8, - PRQ2, 8, - PRQ3, 8 - } - - Method(IQST, 1, NotSerialized) { - // _STA method - get status - If (And(0x80, Arg0)) { - Return (0x09) - } - Return (0x0B) - } - Method(IQCR, 1, Serialized) { - // _CRS method - get current settings - Name(PRR0, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 0 } - }) - CreateDWordField(PRR0, 0x05, PRRI) - If (LLess(Arg0, 0x80)) { - Store(Arg0, PRRI) - } - Return (PRR0) - } - -#define define_link(link, uid, reg) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - 5, 10, 11 \ - } \ - }) \ - Method(_STA, 0, NotSerialized) { \ - Return (IQST(reg)) \ - } \ - Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ - } \ - Method(_CRS, 0, NotSerialized) { \ - Return (IQCR(reg)) \ - } \ - Method(_SRS, 1, NotSerialized) { \ - CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ - } \ - } - - define_link(LNKA, 0, PRQ0) - define_link(LNKB, 1, PRQ1) - define_link(LNKC, 2, PRQ2) - define_link(LNKD, 3, PRQ3) - - Device(LNKS) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Name(_PRS, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 9 } - }) - - // The SCI cannot be disabled and is always attached to GSI 9, - // so these are no-ops. We only need this link to override the - // polarity to active high and match the content of the MADT. - Method(_STA, 0, NotSerialized) { Return (0x0b) } - Method(_DIS, 0, NotSerialized) { } - Method(_CRS, 0, NotSerialized) { Return (_PRS) } - Method(_SRS, 1, NotSerialized) { } - } - } - -#include "hw/acpi/pc-hotplug.h" -#define CPU_STATUS_BASE PIIX4_CPU_HOTPLUG_IO_BASE -#include "acpi-dsdt-cpu-hotplug.dsl" -#include "acpi-dsdt-mem-hotplug.dsl" - - -/**************************************************************** - * General purpose events - ****************************************************************/ - Scope(\_GPE) { - Name(_HID, "ACPI0006") - - Method(_L00) { - } - Method(_E01) { - // PCI hotplug event - Acquire(\_SB.PCI0.BLCK, 0xFFFF) - \_SB.PCI0.PCNT() - Release(\_SB.PCI0.BLCK) - } - Method(_E02) { - // CPU hotplug event - \_SB.PRSC() - } - Method(_E03) { - // Memory hotplug event - \_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD() - } - Method(_L04) { - } - Method(_L05) { - } - Method(_L06) { - } - Method(_L07) { - } - Method(_L08) { - } - Method(_L09) { - } - Method(_L0A) { - } - Method(_L0B) { - } - Method(_L0C) { - } - Method(_L0D) { - } - Method(_L0E) { - } - Method(_L0F) { - } - } -} diff --git a/hw/i386/acpi-dsdt.hex.generated b/hw/i386/acpi-dsdt.hex.generated deleted file mode 100644 index ecaa4a5480..0000000000 --- a/hw/i386/acpi-dsdt.hex.generated +++ /dev/null @@ -1,2972 +0,0 @@ -static unsigned char AcpiDsdtAmlCode[] = { -0x44, -0x53, -0x44, -0x54, -0x9a, -0xb, -0x0, -0x0, -0x1, -0xf8, -0x42, -0x58, -0x50, -0x43, -0x0, -0x0, -0x42, -0x58, -0x44, -0x53, -0x44, -0x54, -0x0, -0x0, -0x1, -0x0, -0x0, -0x0, -0x49, -0x4e, -0x54, -0x4c, -0x7, -0x11, -0x14, -0x20, -0x10, -0x49, -0x4, -0x5c, -0x0, -0x5b, -0x80, -0x44, -0x42, -0x47, -0x5f, -0x1, -0xb, -0x2, -0x4, -0x1, -0x5b, -0x81, -0xb, -0x44, -0x42, -0x47, -0x5f, -0x1, -0x44, -0x42, -0x47, -0x42, -0x8, -0x14, -0x2c, -0x44, -0x42, -0x55, -0x47, -0x1, -0x98, -0x68, -0x60, -0x96, -0x60, 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0; i < ARRAY_SIZE(fdc_container_path); i++) { + container = container_get(qdev_get_machine(), fdc_container_path[i]); + object_child_foreach(container, check_fdc, &state); + } + + if (state.multiple) { + error_report("warning: multiple floppy disk controllers with " + "iobase=0x3f0 have been found;\n" + "the one being picked for CMOS setup might not reflect " + "your intent"); + } + + return state.floppy; +} + static void pc_cmos_init_late(void *opaque) { pc_cmos_init_late_arg *arg = opaque; @@ -368,8 +393,6 @@ static void pc_cmos_init_late(void *opaque) int8_t heads, sectors; int val; int i, trans; - Object *container; - CheckFdcState state = { 0 }; val = 0; if (ide_get_geometry(arg->idebus[0], 0, @@ -399,22 +422,7 @@ static void pc_cmos_init_late(void *opaque) } rtc_set_memory(s, 0x39, val); - /* - * Locate the FDC at IO address 0x3f0, and configure the CMOS registers - * accordingly. - */ - for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { - container = container_get(qdev_get_machine(), fdc_container_path[i]); - object_child_foreach(container, check_fdc, &state); - } - - if (state.multiple) { - error_report("warning: multiple floppy disk controllers with " - "iobase=0x3f0 have been found;\n" - "the one being picked for CMOS setup might not reflect " - "your intent"); - } - pc_cmos_init_floppy(s, state.floppy); + pc_cmos_init_floppy(s, pc_find_fdc0()); qemu_unregister_reset(pc_cmos_init_late, opaque); } diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl deleted file mode 100644 index 7be7b37b87..0000000000 --- a/hw/i386/q35-acpi-dsdt.dsl +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Bochs/QEMU ACPI DSDT ASL definition - * - * Copyright (c) 2006 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License version 2 as published by the Free Software Foundation. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -/* - * Copyright (c) 2010 Isaku Yamahata - * yamahata at valinux co jp - * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. - */ - - -ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode - -DefinitionBlock ( - "q35-acpi-dsdt.aml",// Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision - "BXPC", // OEMID - "BXDSDT", // TABLE ID - 0x2 // OEM Revision - ) -{ - -#include "acpi-dsdt-dbug.dsl" - - Scope(\_SB) { - OperationRegion(PCST, SystemIO, 0xae00, 0x0c) - OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) - Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { - PCIB, 8, - } - } - - -/**************************************************************** - * PCI Bus definition - ****************************************************************/ - Scope(\_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A08")) - Name(_CID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - - External(ISA, DeviceObj) - - // _OSC: based on sample of ACPI3.0b spec - Name(SUPP, 0) // PCI _OSC Support Field value - Name(CTRL, 0) // PCI _OSC Control Field value - Method(_OSC, 4) { - // Create DWORD-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 0, CDW1) - - // Check for proper UUID - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWORD-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 4, CDW2) - CreateDWordField(Arg3, 8, CDW3) - - // Save Capabilities DWORD2 & 3 - Store(CDW2, SUPP) - Store(CDW3, CTRL) - - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL, 0x1D, CTRL) - -#if 0 // For now, nothing to do - If (Not(And(CDW1, 1))) { // Query flag clear? - // Disable GPEs for features granted native control. - If (And(CTRL, 0x01)) { // Hot plug control granted? - Store(0, HPCE) // clear the hot plug SCI enable bit - Store(1, HPCS) // clear the hot plug SCI status bit - } - If (And(CTRL, 0x04)) { // PME control granted? - Store(0, PMCE) // clear the PME SCI enable bit - Store(1, PMCS) // clear the PME SCI status bit - } - If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? - // Set status to not restore PCI Express cap structure - // upon resume from S3 - Store(1, S3CR) - } - } -#endif - If (LNotEqual(Arg1, One)) { - // Unknown revision - Or(CDW1, 0x08, CDW1) - } - If (LNotEqual(CDW3, CTRL)) { - // Capabilities bits were masked - Or(CDW1, 0x10, CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL, CDW3) - } Else { - Or(CDW1, 4, CDW1) // Unrecognized UUID - } - Return (Arg3) - } - } - } - -#include "acpi-dsdt-hpet.dsl" - - -/**************************************************************** - * LPC ISA bridge - ****************************************************************/ - - Scope(\_SB.PCI0) { - /* PCI D31:f0 LPC ISA bridge */ - Device(ISA) { - Name (_ADR, 0x001F0000) // _ADR: Address - - /* ICH9 PCI to ISA irq remapping */ - OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) - - OperationRegion(LPCD, PCI_Config, 0x80, 0x2) - Field(LPCD, AnyAcc, NoLock, Preserve) { - COMA, 3, - , 1, - COMB, 3, - - Offset(0x01), - LPTD, 2, - , 2, - FDCD, 2 - } - OperationRegion(LPCE, PCI_Config, 0x82, 0x2) - Field(LPCE, AnyAcc, NoLock, Preserve) { - CAEN, 1, - CBEN, 1, - LPEN, 1, - FDEN, 1 - } - } - } - -#include "acpi-dsdt-isa.dsl" - - -/**************************************************************** - * PCI IRQs - ****************************************************************/ - - /* Zero => PIC mode, One => APIC Mode */ - Name(\PICF, Zero) - Method(\_PIC, 1, NotSerialized) { - Store(Arg0, \PICF) - } - - Scope(\_SB) { - Scope(PCI0) { -#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \ - Package() { nr##ffff, 0, lnk0, 0 }, \ - Package() { nr##ffff, 1, lnk1, 0 }, \ - Package() { nr##ffff, 2, lnk2, 0 }, \ - Package() { nr##ffff, 3, lnk3, 0 } - -#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD) -#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA) -#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB) -#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC) - -#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH) -#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE) -#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) -#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG) - - Name(PRTP, package() { - prt_slot_lnkE(0x0000), - prt_slot_lnkF(0x0001), - prt_slot_lnkG(0x0002), - prt_slot_lnkH(0x0003), - prt_slot_lnkE(0x0004), - prt_slot_lnkF(0x0005), - prt_slot_lnkG(0x0006), - prt_slot_lnkH(0x0007), - prt_slot_lnkE(0x0008), - prt_slot_lnkF(0x0009), - prt_slot_lnkG(0x000a), - prt_slot_lnkH(0x000b), - prt_slot_lnkE(0x000c), - prt_slot_lnkF(0x000d), - prt_slot_lnkG(0x000e), - prt_slot_lnkH(0x000f), - prt_slot_lnkE(0x0010), - prt_slot_lnkF(0x0011), - prt_slot_lnkG(0x0012), - prt_slot_lnkH(0x0013), - prt_slot_lnkE(0x0014), - prt_slot_lnkF(0x0015), - prt_slot_lnkG(0x0016), - prt_slot_lnkH(0x0017), - prt_slot_lnkE(0x0018), - - /* INTA -> PIRQA for slot 25 - 31 - see the default value of D<N>IR */ - prt_slot_lnkA(0x0019), - prt_slot_lnkA(0x001a), - prt_slot_lnkA(0x001b), - prt_slot_lnkA(0x001c), - prt_slot_lnkA(0x001d), - - /* PCIe->PCI bridge. use PIRQ[E-H] */ - prt_slot_lnkE(0x001e), - - prt_slot_lnkA(0x001f) - }) - -#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ - Package() { nr##ffff, 0, gsi0, 0 }, \ - Package() { nr##ffff, 1, gsi1, 0 }, \ - Package() { nr##ffff, 2, gsi2, 0 }, \ - Package() { nr##ffff, 3, gsi3, 0 } - -#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) -#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA) -#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB) -#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC) - -#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH) -#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE) -#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) -#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG) - - Name(PRTA, package() { - prt_slot_gsiE(0x0000), - prt_slot_gsiF(0x0001), - prt_slot_gsiG(0x0002), - prt_slot_gsiH(0x0003), - prt_slot_gsiE(0x0004), - prt_slot_gsiF(0x0005), - prt_slot_gsiG(0x0006), - prt_slot_gsiH(0x0007), - prt_slot_gsiE(0x0008), - prt_slot_gsiF(0x0009), - prt_slot_gsiG(0x000a), - prt_slot_gsiH(0x000b), - prt_slot_gsiE(0x000c), - prt_slot_gsiF(0x000d), - prt_slot_gsiG(0x000e), - prt_slot_gsiH(0x000f), - prt_slot_gsiE(0x0010), - prt_slot_gsiF(0x0011), - prt_slot_gsiG(0x0012), - prt_slot_gsiH(0x0013), - prt_slot_gsiE(0x0014), - prt_slot_gsiF(0x0015), - prt_slot_gsiG(0x0016), - prt_slot_gsiH(0x0017), - prt_slot_gsiE(0x0018), - - /* INTA -> PIRQA for slot 25 - 31, but 30 - see the default value of D<N>IR */ - prt_slot_gsiA(0x0019), - prt_slot_gsiA(0x001a), - prt_slot_gsiA(0x001b), - prt_slot_gsiA(0x001c), - prt_slot_gsiA(0x001d), - - /* PCIe->PCI bridge. use PIRQ[E-H] */ - prt_slot_gsiE(0x001e), - - prt_slot_gsiA(0x001f) - }) - - Method(_PRT, 0, NotSerialized) { - /* PCI IRQ routing table, example from ACPI 2.0a specification, - section 6.2.8.1 */ - /* Note: we provide the same info as the PCI routing - table of the Bochs BIOS */ - If (LEqual(\PICF, Zero)) { - Return (PRTP) - } Else { - Return (PRTA) - } - } - } - - Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { - PRQA, 8, - PRQB, 8, - PRQC, 8, - PRQD, 8, - - Offset(0x08), - PRQE, 8, - PRQF, 8, - PRQG, 8, - PRQH, 8 - } - - Method(IQST, 1, NotSerialized) { - // _STA method - get status - If (And(0x80, Arg0)) { - Return (0x09) - } - Return (0x0B) - } - Method(IQCR, 1, Serialized) { - // _CRS method - get current settings - Name(PRR0, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 0 } - }) - CreateDWordField(PRR0, 0x05, PRRI) - Store(And(Arg0, 0x0F), PRRI) - Return (PRR0) - } - -#define define_link(link, uid, reg) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - 5, 10, 11 \ - } \ - }) \ - Method(_STA, 0, NotSerialized) { \ - Return (IQST(reg)) \ - } \ - Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ - } \ - Method(_CRS, 0, NotSerialized) { \ - Return (IQCR(reg)) \ - } \ - Method(_SRS, 1, NotSerialized) { \ - CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ - } \ - } - - define_link(LNKA, 0, PRQA) - define_link(LNKB, 1, PRQB) - define_link(LNKC, 2, PRQC) - define_link(LNKD, 3, PRQD) - define_link(LNKE, 4, PRQE) - define_link(LNKF, 5, PRQF) - define_link(LNKG, 6, PRQG) - define_link(LNKH, 7, PRQH) - -#define define_gsi_link(link, uid, gsi) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - gsi \ - } \ - }) \ - Name(_CRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - gsi \ - } \ - }) \ - Method(_SRS, 1, NotSerialized) { \ - } \ - } - - define_gsi_link(GSIA, 0, 0x10) - define_gsi_link(GSIB, 0, 0x11) - define_gsi_link(GSIC, 0, 0x12) - define_gsi_link(GSID, 0, 0x13) - define_gsi_link(GSIE, 0, 0x14) - define_gsi_link(GSIF, 0, 0x15) - define_gsi_link(GSIG, 0, 0x16) - define_gsi_link(GSIH, 0, 0x17) - } - -#include "hw/acpi/pc-hotplug.h" -#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE -#include "acpi-dsdt-cpu-hotplug.dsl" -#include "acpi-dsdt-mem-hotplug.dsl" - - -/**************************************************************** - * General purpose events - ****************************************************************/ - Scope(\_GPE) { - Name(_HID, "ACPI0006") - - Method(_L00) { - } - Method(_L01) { - } - Method(_E02) { - // CPU hotplug event - \_SB.PRSC() - } - Method(_E03) { - // Memory hotplug event - \_SB.PCI0.MEMORY_HOTPLUG_DEVICE.MEMORY_SLOT_SCAN_METHOD() - } - Method(_L04) { - } - Method(_L05) { - } - Method(_L06) { - } - Method(_L07) { - } - Method(_L08) { - } - Method(_L09) { - } - Method(_L0A) { - } - Method(_L0B) { - } - Method(_L0C) { - } - Method(_L0D) { - } - Method(_L0E) { - } - Method(_L0F) { - } - } -} diff --git a/hw/i386/q35-acpi-dsdt.hex.generated b/hw/i386/q35-acpi-dsdt.hex.generated deleted file mode 100644 index ed9a2cc8e0..0000000000 --- a/hw/i386/q35-acpi-dsdt.hex.generated +++ /dev/null @@ -1,7610 +0,0 @@ -static unsigned char Q35AcpiDsdtAmlCode[] = { -0x44, -0x53, -0x44, -0x54, -0xb8, -0x1d, -0x0, -0x0, -0x1, -0x35, -0x42, -0x58, -0x50, -0x43, -0x0, -0x0, -0x42, -0x58, -0x44, -0x53, -0x44, -0x54, -0x0, -0x0, -0x2, -0x0, -0x0, -0x0, -0x49, -0x4e, -0x54, -0x4c, -0x7, -0x11, -0x14, -0x20, -0x10, -0x49, -0x4, -0x5c, -0x0, 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-0x5f, -0x4c, -0x30, -0x42, -0x0, -0x14, -0x6, -0x5f, -0x4c, -0x30, -0x43, -0x0, -0x14, -0x6, -0x5f, -0x4c, -0x30, -0x44, -0x0, -0x14, -0x6, -0x5f, -0x4c, -0x30, -0x45, -0x0, -0x14, -0x6, -0x5f, -0x4c, -0x30, -0x46, -0x0 -}; diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c index 65f8dd457b..272ab90c7a 100644 --- a/hw/ide/atapi.c +++ b/hw/ide/atapi.c @@ -824,7 +824,6 @@ static void cmd_inquiry(IDEState *s, uint8_t *buf) out: buf[size_idx] = idx - preamble_len; ide_atapi_cmd_reply(s, idx, max_len); - return; } static void cmd_get_configuration(IDEState *s, uint8_t *buf) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 3ee962f830..97712619cd 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -292,8 +292,6 @@ done: block_acct_done(blk_get_stats(s->blk), &s->acct); } io->dma_end(opaque); - - return; } static void pmac_ide_transfer_cb(void *opaque, int ret) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 462060f093..edfb30f697 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -81,6 +81,7 @@ petalogix_ml605_init(MachineState *machine) /* init CPUs */ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); + object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort); /* Use FPU but don't use floating point conversion and square * root instructions */ diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 33811561bb..1c84b75288 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -66,6 +66,7 @@ petalogix_s3adsp1800_init(MachineState *machine) MemoryRegion *sysmem = get_system_memory(); cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); + object_property_set_str(OBJECT(cpu), "7.10.d", "version", &error_abort); object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index f76a9fd36b..c1f3c9c3e9 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1193,7 +1193,7 @@ static int gt64120_init(SysBusDevice *dev) return 0; } -static int gt64120_pci_init(PCIDevice *d) +static void gt64120_pci_realize(PCIDevice *d, Error **errp) { /* FIXME: Malta specific hw assumptions ahead */ pci_set_word(d->config + PCI_COMMAND, 0); @@ -1207,8 +1207,6 @@ static int gt64120_pci_init(PCIDevice *d) pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000); pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001); pci_set_byte(d->config + 0x3d, 0x01); - - return 0; } static void gt64120_pci_class_init(ObjectClass *klass, void *data) @@ -1216,7 +1214,7 @@ static void gt64120_pci_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - k->init = gt64120_pci_init; + k->realize = gt64120_pci_realize; k->vendor_id = PCI_VENDOR_ID_MARVELL; k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X; k->revision = 0x10; diff --git a/hw/misc/edu.c b/hw/misc/edu.c index fe50b42af7..43d5b18f2a 100644 --- a/hw/misc/edu.c +++ b/hw/misc/edu.c @@ -327,7 +327,7 @@ static void *edu_fact_thread(void *opaque) return NULL; } -static int pci_edu_init(PCIDevice *pdev) +static void pci_edu_realize(PCIDevice *pdev, Error **errp) { EduState *edu = DO_UPCAST(EduState, pdev, pdev); uint8_t *pci_conf = pdev->config; @@ -344,8 +344,6 @@ static int pci_edu_init(PCIDevice *pdev) memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, "edu-mmio", 1 << 20); pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); - - return 0; } static void pci_edu_uninit(PCIDevice *pdev) @@ -385,7 +383,7 @@ static void edu_class_init(ObjectClass *class, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(class); - k->init = pci_edu_init; + k->realize = pci_edu_realize; k->exit = pci_edu_uninit; k->vendor_id = PCI_VENDOR_ID_QEMU; k->device_id = 0x11e8; diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index f73f0c2b17..df585de10f 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -29,6 +29,7 @@ #include "sysemu/char.h" #include "sysemu/hostmem.h" #include "qapi/visitor.h" +#include "exec/ram_addr.h" #include "hw/misc/ivshmem.h" @@ -422,6 +423,7 @@ static int create_shared_memory_BAR(IVShmemState *s, int fd, uint8_t attr, memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2", s->ivshmem_size, ptr); + qemu_set_ram_fd(s->ivshmem.ram_addr, fd); vmstate_register_ram(&s->ivshmem, DEVICE(s)); memory_region_add_subregion(&s->bar, 0, &s->ivshmem); @@ -682,6 +684,7 @@ static void ivshmem_read(void *opaque, const uint8_t *buf, int size) } memory_region_init_ram_ptr(&s->ivshmem, OBJECT(s), "ivshmem.bar2", s->ivshmem_size, map_ptr); + qemu_set_ram_fd(s->ivshmem.ram_addr, incoming_fd); vmstate_register_ram(&s->ivshmem, DEVICE(s)); IVSHMEM_DPRINTF("guest h/w addr = %p, size = %" PRIu64 "\n", @@ -689,7 +692,6 @@ static void ivshmem_read(void *opaque, const uint8_t *buf, int size) memory_region_add_subregion(&s->bar, 0, &s->ivshmem); - close(incoming_fd); return; } @@ -991,7 +993,6 @@ static void pci_ivshmem_realize(PCIDevice *dev, Error **errp) } create_shared_memory_BAR(s, fd, attr, errp); - close(fd); } } @@ -1010,11 +1011,15 @@ static void pci_ivshmem_exit(PCIDevice *dev) if (memory_region_is_mapped(&s->ivshmem)) { if (!s->hostmem) { void *addr = memory_region_get_ram_ptr(&s->ivshmem); + int fd; if (munmap(addr, s->ivshmem_size) == -1) { error_report("Failed to munmap shared memory %s", strerror(errno)); } + + if ((fd = qemu_get_ram_fd(s->ivshmem.ram_addr)) != -1) + close(fd); } vmstate_unregister_ram(&s->ivshmem, DEVICE(dev)); diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c index 010f9efccd..a3dffff2ad 100644 --- a/hw/net/ne2000.c +++ b/hw/net/ne2000.c @@ -467,8 +467,9 @@ static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, uint32_t val) { addr &= ~1; /* XXX: check exact behaviour if not even */ - if (addr < 32 || - (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { + if (addr < 32 + || (addr >= NE2000_PMEM_START + && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) { stl_le_p(s->mem + addr, val); } } @@ -497,8 +498,9 @@ static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) { addr &= ~1; /* XXX: check exact behaviour if not even */ - if (addr < 32 || - (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) { + if (addr < 32 + || (addr >= NE2000_PMEM_START + && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) { return ldl_le_p(s->mem + addr); } else { return 0xffffffff; diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index c57f1a661a..2e77e5086a 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -232,6 +232,9 @@ static int tx_consume(Rocker *r, DescInfo *info) frag_addr = rocker_tlv_get_le64(tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR]); frag_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]); + if (iovcnt >= ROCKER_TX_FRAGS_MAX) { + goto err_too_many_frags; + } iov[iovcnt].iov_len = frag_len; iov[iovcnt].iov_base = g_malloc(frag_len); if (!iov[iovcnt].iov_base) { @@ -244,10 +247,7 @@ static int tx_consume(Rocker *r, DescInfo *info) err = -ROCKER_ENXIO; goto err_bad_io; } - - if (++iovcnt > ROCKER_TX_FRAGS_MAX) { - goto err_too_many_frags; - } + iovcnt++; } if (iovcnt) { diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c index 68e43f3d48..d192d573b4 100644 --- a/hw/net/rtl8139.c +++ b/hw/net/rtl8139.c @@ -74,7 +74,6 @@ ( ( input ) & ( size - 1 ) ) #define ETHER_TYPE_LEN 2 -#define ETH_HLEN (ETH_ALEN * 2 + ETHER_TYPE_LEN) #define ETH_MTU 1500 #define VLAN_TCI_LEN 2 diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h index 1099df669d..c2c2f900fa 100644 --- a/hw/net/vmware_utils.h +++ b/hw/net/vmware_utils.h @@ -18,10 +18,7 @@ #define VMWARE_UTILS_H #include "qemu/range.h" - -#ifndef VMW_SHPRN -#define VMW_SHPRN(fmt, ...) do {} while (0) -#endif +#include "vmxnet_debug.h" /* * Shared memory access functions with byte swap support diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 37373e5d3d..67abad3598 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -36,12 +36,28 @@ #define VMXNET3_MSIX_BAR_SIZE 0x2000 #define MIN_BUF_SIZE 60 +/* Compatability flags for migration */ +#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 +#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ + (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) +#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 +#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ + (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) + +#define VMXNET3_EXP_EP_OFFSET (0x48) +#define VMXNET3_MSI_OFFSET(s) \ + ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) +#define VMXNET3_MSIX_OFFSET(s) \ + ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) +#define VMXNET3_DSN_OFFSET (0x100) + #define VMXNET3_BAR0_IDX (0) #define VMXNET3_BAR1_IDX (1) #define VMXNET3_MSIX_BAR_IDX (2) #define VMXNET3_OFF_MSIX_TABLE (0x000) -#define VMXNET3_OFF_MSIX_PBA (0x800) +#define VMXNET3_OFF_MSIX_PBA(s) \ + ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) /* Link speed in Mbps should be shifted by 16 */ #define VMXNET3_LINK_SPEED (1000 << 16) @@ -50,7 +66,7 @@ #define VMXNET3_LINK_STATUS_UP 0x1 /* Least significant bit should be set for revision and version */ -#define VMXNET3_DEVICE_VERSION 0x1 +#define VMXNET3_UPT_REVISION 0x1 #define VMXNET3_DEVICE_REVISION 0x1 /* Number of interrupt vectors for non-MSIx modes */ @@ -108,9 +124,19 @@ #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) +typedef struct VMXNET3Class { + PCIDeviceClass parent_class; + DeviceRealize parent_dc_realize; +} VMXNET3Class; + #define TYPE_VMXNET3 "vmxnet3" #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3) +#define VMXNET3_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3) +#define VMXNET3_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3) + /* Cyclic ring abstraction */ typedef struct { hwaddr pa; @@ -138,7 +164,7 @@ static inline void vmxnet3_ring_init(Vmxnet3Ring *ring, } #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ - macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \ + macro("%s#%d: base %" PRIx64 " size %zu cell_size %zu gen %d next %zu", \ (ring_name), (ridx), \ (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) @@ -313,6 +339,9 @@ typedef struct { MACAddr *mcast_list; uint32_t mcast_list_len; uint32_t mcast_list_buff_size; /* needed for live migration. */ + + /* Compatability flags for migration */ + uint32_t compat_flags; } VMXNET3State; /* Interrupt management */ @@ -925,7 +954,7 @@ static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt *pkt, /* Validate packet len: csum_start + scum_offset + length of csum field */ if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { - VMW_PKPRN("packet len:%lu < csum_start(%d) + csum_offset(%d) + 2, " + VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " "cannot calculate checksum", pkt_len, vhdr->csum_start, vhdr->csum_offset); return; @@ -1194,8 +1223,13 @@ static void vmxnet3_reset_mac(VMXNET3State *s) static void vmxnet3_deactivate_device(VMXNET3State *s) { - VMW_CBPRN("Deactivating vmxnet3..."); - s->device_active = false; + if (s->device_active) { + VMW_CBPRN("Deactivating vmxnet3..."); + vmxnet_tx_pkt_reset(s->tx_pkt); + vmxnet_tx_pkt_uninit(s->tx_pkt); + vmxnet_rx_pkt_uninit(s->rx_pkt); + s->device_active = false; + } } static void vmxnet3_reset(VMXNET3State *s) @@ -1204,7 +1238,6 @@ static void vmxnet3_reset(VMXNET3State *s) vmxnet3_deactivate_device(s); vmxnet3_reset_interrupt_states(s); - vmxnet_tx_pkt_reset(s->tx_pkt); s->drv_shmem = 0; s->tx_sop = true; s->skip_current_tx_pkt = false; @@ -1431,6 +1464,12 @@ static void vmxnet3_activate_device(VMXNET3State *s) return; } + /* Verify if device is active */ + if (s->device_active) { + VMW_CFPRN("Vmxnet3 device is active"); + return; + } + vmxnet3_adjust_by_guest_type(s); vmxnet3_update_features(s); vmxnet3_update_pm_state(s); @@ -1627,7 +1666,7 @@ static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) break; case VMXNET3_CMD_QUIESCE_DEV: - VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device"); + VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); vmxnet3_deactivate_device(s); break; @@ -1640,6 +1679,18 @@ static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) "adaptive ring info flags"); break; + case VMXNET3_CMD_GET_DID_LO: + VMW_CBPRN("Set: Get lower part of device ID"); + break; + + case VMXNET3_CMD_GET_DID_HI: + VMW_CBPRN("Set: Get upper part of device ID"); + break; + + case VMXNET3_CMD_GET_DEV_EXTRA_INFO: + VMW_CBPRN("Set: Get device extra info"); + break; + default: VMW_CBPRN("Received unknown command: %" PRIx64, cmd); break; @@ -1652,13 +1703,14 @@ static uint64_t vmxnet3_get_command_status(VMXNET3State *s) switch (s->last_command) { case VMXNET3_CMD_ACTIVATE_DEV: - ret = (s->device_active) ? 0 : -1; + ret = (s->device_active) ? 0 : 1; VMW_CFPRN("Device active: %" PRIx64, ret); break; case VMXNET3_CMD_RESET_DEV: case VMXNET3_CMD_QUIESCE_DEV: case VMXNET3_CMD_GET_QUEUE_STATUS: + case VMXNET3_CMD_GET_DEV_EXTRA_INFO: ret = 0; break; @@ -1683,9 +1735,17 @@ static uint64_t vmxnet3_get_command_status(VMXNET3State *s) ret = VMXNET3_DISABLE_ADAPTIVE_RING; break; + case VMXNET3_CMD_GET_DID_LO: + ret = PCI_DEVICE_ID_VMWARE_VMXNET3; + break; + + case VMXNET3_CMD_GET_DID_HI: + ret = VMXNET3_DEVICE_REVISION; + break; + default: VMW_WRPRN("Received request for unknown command: %x", s->last_command); - ret = -1; + ret = 0; break; } @@ -1741,7 +1801,7 @@ vmxnet3_io_bar1_write(void *opaque, * shared address only after we get the high part */ if (val == 0) { - s->device_active = false; + vmxnet3_deactivate_device(s); } s->temp_shared_guest_driver_memory = val; s->drv_shmem = 0; @@ -1816,7 +1876,7 @@ vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) /* UPT Version Report Selection */ case VMXNET3_REG_UVRS: VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); - ret = VMXNET3_DEVICE_VERSION; + ret = VMXNET3_UPT_REVISION; break; /* Command */ @@ -1974,7 +2034,7 @@ vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; if (bytes_indicated < size) { - VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size); + VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); } } else { VMW_PKPRN("Packet dropped by RX filter"); @@ -2021,9 +2081,7 @@ static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) static void vmxnet3_net_uninit(VMXNET3State *s) { g_free(s->mcast_list); - vmxnet_tx_pkt_reset(s->tx_pkt); - vmxnet_tx_pkt_uninit(s->tx_pkt); - vmxnet_rx_pkt_uninit(s->rx_pkt); + vmxnet3_deactivate_device(s); qemu_del_nic(s->nic); } @@ -2043,7 +2101,7 @@ static void vmxnet3_net_init(VMXNET3State *s) s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; - VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); + VMW_CFPRN("Permanent MAC: " VMXNET_MF, VMXNET_MA(s->perm_mac.a)); s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, object_get_typename(OBJECT(s)), @@ -2101,8 +2159,8 @@ vmxnet3_init_msix(VMXNET3State *s) &s->msix_bar, VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, &s->msix_bar, - VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA, - 0); + VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), + VMXNET3_MSIX_OFFSET(s)); if (0 > res) { VMW_WRPRN("Failed to initialize MSI-X, error %d", res); @@ -2130,7 +2188,6 @@ vmxnet3_cleanup_msix(VMXNET3State *s) } } -#define VMXNET3_MSI_OFFSET (0x50) #define VMXNET3_USE_64BIT (true) #define VMXNET3_PER_VECTOR_MASK (false) @@ -2140,7 +2197,7 @@ vmxnet3_init_msi(VMXNET3State *s) PCIDevice *d = PCI_DEVICE(s); int res; - res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS, + res = msi_init(d, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK); if (0 > res) { VMW_WRPRN("Failed to initialize MSI, error %d", res); @@ -2197,6 +2254,22 @@ static const MemoryRegionOps b1_ops = { }, }; +static uint8_t *vmxnet3_device_serial_num(VMXNET3State *s) +{ + static uint64_t dsn_payload; + uint8_t *dsnp = (uint8_t *)&dsn_payload; + + dsnp[0] = 0xfe; + dsnp[1] = s->conf.macaddr.a[3]; + dsnp[2] = s->conf.macaddr.a[4]; + dsnp[3] = s->conf.macaddr.a[5]; + dsnp[4] = s->conf.macaddr.a[0]; + dsnp[5] = s->conf.macaddr.a[1]; + dsnp[6] = s->conf.macaddr.a[2]; + dsnp[7] = 0xff; + return dsnp; +} + static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) { DeviceState *dev = DEVICE(pci_dev); @@ -2234,6 +2307,17 @@ static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) vmxnet3_net_init(s); + if (pci_is_express(pci_dev)) { + if (pci_bus_is_express(pci_dev->bus)) { + pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); + } + + pcie_add_capability(pci_dev, PCI_EXT_CAP_ID_DSN, 0x1, + VMXNET3_DSN_OFFSET, PCI_EXT_CAP_DSN_SIZEOF); + memcpy(pci_dev->config + VMXNET3_DSN_OFFSET + 4, + vmxnet3_device_serial_num(s), sizeof(uint64_t)); + } + register_savevm(dev, "vmxnet3-msix", -1, 1, vmxnet3_msix_save, vmxnet3_msix_load, s); } @@ -2503,6 +2587,29 @@ static const VMStateInfo int_state_info = { .put = vmxnet3_put_int_state }; +static bool vmxnet3_vmstate_need_pcie_device(void *opaque) +{ + VMXNET3State *s = VMXNET3(opaque); + + return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE); +} + +static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id) +{ + return !vmxnet3_vmstate_need_pcie_device(opaque); +} + +static const VMStateDescription vmstate_vmxnet3_pcie_device = { + .name = "vmxnet3/pcie", + .version_id = 1, + .minimum_version_id = 1, + .needed = vmxnet3_vmstate_need_pcie_device, + .fields = (VMStateField[]) { + VMSTATE_PCIE_DEVICE(parent_obj, VMXNET3State), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_vmxnet3 = { .name = "vmxnet3", .version_id = 1, @@ -2510,7 +2617,9 @@ static const VMStateDescription vmstate_vmxnet3 = { .pre_save = vmxnet3_pre_save, .post_load = vmxnet3_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State), + VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State, + vmxnet3_vmstate_test_pci_device, 0, + vmstate_pci_device, PCIDevice), VMSTATE_BOOL(rx_packets_compound, VMXNET3State), VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), VMSTATE_BOOL(lro_supported, VMXNET3State), @@ -2545,19 +2654,38 @@ static const VMStateDescription vmstate_vmxnet3 = { }, .subsections = (const VMStateDescription*[]) { &vmxstate_vmxnet3_mcast_list, + &vmstate_vmxnet3_pcie_device, NULL } }; static Property vmxnet3_properties[] = { DEFINE_NIC_PROPERTIES(VMXNET3State, conf), + DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, + VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), + DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, + VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), DEFINE_PROP_END_OF_LIST(), }; +static void vmxnet3_realize(DeviceState *qdev, Error **errp) +{ + VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); + PCIDevice *pci_dev = PCI_DEVICE(qdev); + VMXNET3State *s = VMXNET3(qdev); + + if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { + pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; + } + + vc->parent_dc_realize(qdev, errp); +} + static void vmxnet3_class_init(ObjectClass *class, void *data) { DeviceClass *dc = DEVICE_CLASS(class); PCIDeviceClass *c = PCI_DEVICE_CLASS(class); + VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); c->realize = vmxnet3_pci_realize; c->exit = vmxnet3_pci_uninit; @@ -2567,6 +2695,8 @@ static void vmxnet3_class_init(ObjectClass *class, void *data) c->class_id = PCI_CLASS_NETWORK_ETHERNET; c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; + vc->parent_dc_realize = dc->realize; + dc->realize = vmxnet3_realize; dc->desc = "VMWare Paravirtualized Ethernet v3"; dc->reset = vmxnet3_qdev_reset; dc->vmsd = &vmstate_vmxnet3; @@ -2577,6 +2707,7 @@ static void vmxnet3_class_init(ObjectClass *class, void *data) static const TypeInfo vmxnet3_info = { .name = TYPE_VMXNET3, .parent = TYPE_PCI_DEVICE, + .class_size = sizeof(VMXNET3Class), .instance_size = sizeof(VMXNET3State), .class_init = vmxnet3_class_init, .instance_init = vmxnet3_instance_init, diff --git a/hw/net/vmxnet_debug.h b/hw/net/vmxnet_debug.h index 96dae0f916..96495dbb12 100644 --- a/hw/net/vmxnet_debug.h +++ b/hw/net/vmxnet_debug.h @@ -20,94 +20,127 @@ #define VMXNET_DEVICE_NAME "vmxnet3" -/* #define VMXNET_DEBUG_CB */ #define VMXNET_DEBUG_WARNINGS #define VMXNET_DEBUG_ERRORS -/* #define VMXNET_DEBUG_INTERRUPTS */ -/* #define VMXNET_DEBUG_CONFIG */ -/* #define VMXNET_DEBUG_RINGS */ -/* #define VMXNET_DEBUG_PACKETS */ -/* #define VMXNET_DEBUG_SHMEM_ACCESS */ + +#undef VMXNET_DEBUG_CB +#undef VMXNET_DEBUG_INTERRUPTS +#undef VMXNET_DEBUG_CONFIG +#undef VMXNET_DEBUG_RINGS +#undef VMXNET_DEBUG_PACKETS +#undef VMXNET_DEBUG_SHMEM_ACCESS + +#ifdef VMXNET_DEBUG_CB +# define VMXNET_DEBUG_CB_ENABLED 1 +#else +# define VMXNET_DEBUG_CB_ENABLED 0 +#endif + +#ifdef VMXNET_DEBUG_WARNINGS +# define VMXNET_DEBUG_WARNINGS_ENABLED 1 +#else +# define VMXNET_DEBUG_WARNINGS_ENABLED 0 +#endif + +#ifdef VMXNET_DEBUG_ERRORS +# define VMXNET_DEBUG_ERRORS_ENABLED 1 +#else +# define VMXNET_DEBUG_ERRORS_ENABLED 0 +#endif + +#ifdef VMXNET_DEBUG_CONFIG +# define VMXNET_DEBUG_CONFIG_ENABLED 1 +#else +# define VMXNET_DEBUG_CONFIG_ENABLED 0 +#endif + +#ifdef VMXNET_DEBUG_RINGS +# define VMXNET_DEBUG_RINGS_ENABLED 1 +#else +# define VMXNET_DEBUG_RINGS_ENABLED 0 +#endif + +#ifdef VMXNET_DEBUG_PACKETS +# define VMXNET_DEBUG_PACKETS_ENABLED 1 +#else +# define VMXNET_DEBUG_PACKETS_ENABLED 0 +#endif + +#ifdef VMXNET_DEBUG_INTERRUPTS +# define VMXNET_DEBUG_INTERRUPTS_ENABLED 1 +#else +# define VMXNET_DEBUG_INTERRUPTS_ENABLED 0 +#endif #ifdef VMXNET_DEBUG_SHMEM_ACCESS +# define VMXNET_DEBUG_SHMEM_ACCESS_ENABLED 1 +#else +# define VMXNET_DEBUG_SHMEM_ACCESS_ENABLED 0 +#endif + #define VMW_SHPRN(fmt, ...) \ do { \ - printf("[%s][SH][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_SHMEM_ACCESS_ENABLED) { \ + printf("[%s][SH][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_SHPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_CB #define VMW_CBPRN(fmt, ...) \ do { \ - printf("[%s][CB][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_CB_ENABLED) { \ + printf("[%s][CB][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_CBPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_PACKETS #define VMW_PKPRN(fmt, ...) \ do { \ - printf("[%s][PK][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_PACKETS_ENABLED) { \ + printf("[%s][PK][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_PKPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_WARNINGS #define VMW_WRPRN(fmt, ...) \ do { \ - printf("[%s][WR][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_WARNINGS_ENABLED) { \ + printf("[%s][WR][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_WRPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_ERRORS #define VMW_ERPRN(fmt, ...) \ do { \ - printf("[%s][ER][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_ERRORS_ENABLED) { \ + printf("[%s][ER][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_ERPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_INTERRUPTS #define VMW_IRPRN(fmt, ...) \ do { \ - printf("[%s][IR][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_INTERRUPTS_ENABLED) { \ + printf("[%s][IR][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_IRPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_CONFIG #define VMW_CFPRN(fmt, ...) \ do { \ - printf("[%s][CF][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_CONFIG_ENABLED) { \ + printf("[%s][CF][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_CFPRN(fmt, ...) do {} while (0) -#endif -#ifdef VMXNET_DEBUG_RINGS #define VMW_RIPRN(fmt, ...) \ do { \ - printf("[%s][RI][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ - ## __VA_ARGS__); \ + if (VMXNET_DEBUG_RINGS_ENABLED) { \ + printf("[%s][RI][%s]: " fmt "\n", VMXNET_DEVICE_NAME, __func__, \ + ## __VA_ARGS__); \ + } \ } while (0) -#else -#define VMW_RIPRN(fmt, ...) do {} while (0) -#endif #define VMXNET_MF "%02X:%02X:%02X:%02X:%02X:%02X" #define VMXNET_MA(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 4139a2c468..b477679434 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -180,8 +180,6 @@ #define PCI_ADDR(busno,devno,funno,regno) \ ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) -#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" - typedef struct BonitoState BonitoState; typedef struct PCIBonitoState @@ -215,17 +213,20 @@ typedef struct PCIBonitoState } PCIBonitoState; -#define BONITO_PCI_HOST_BRIDGE(obj) \ - OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) - struct BonitoState { PCIHostState parent_obj; - qemu_irq *pic; - PCIBonitoState *pci_dev; }; +#define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" +#define BONITO_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) + +#define TYPE_PCI_BONITO "Bonito" +#define PCI_BONITO(obj) \ + OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO) + static void bonito_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -723,7 +724,7 @@ static int bonito_pcihost_initfn(SysBusDevice *dev) static void bonito_realize(PCIDevice *dev, Error **errp) { - PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); + PCIBonitoState *s = PCI_BONITO(dev); SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); @@ -799,8 +800,8 @@ PCIBus *bonito_init(qemu_irq *pic) qdev_init_nofail(dev); /* set the pcihost pointer before bonito_initfn is called */ - d = pci_create(phb->bus, PCI_DEVFN(0, 0), "Bonito"); - s = DO_UPCAST(PCIBonitoState, dev, d); + d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); + s = PCI_BONITO(d); s->pcihost = pcihost; pcihost->pci_dev = s; qdev_init_nofail(DEVICE(d)); @@ -828,7 +829,7 @@ static void bonito_class_init(ObjectClass *klass, void *data) } static const TypeInfo bonito_info = { - .name = "Bonito", + .name = TYPE_PCI_BONITO, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCIBonitoState), .class_init = bonito_class_init, diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 715208b22a..924f0fa82b 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -761,7 +761,7 @@ static const IGDHostInfo igd_host_bridge_infos[] = { {0xa8, 4}, /* SNB: base of GTT stolen memory */ }; -static int host_pci_config_read(int pos, int len, uint32_t val) +static int host_pci_config_read(int pos, int len, uint32_t *val) { char path[PATH_MAX]; int config_fd; @@ -784,12 +784,14 @@ static int host_pci_config_read(int pos, int len, uint32_t val) ret = -errno; goto out; } + do { - rc = read(config_fd, (uint8_t *)&val, len); + rc = read(config_fd, (uint8_t *)val, len); } while (rc < 0 && (errno == EINTR || errno == EAGAIN)); if (rc != len) { ret = -errno; } + out: close(config_fd); return ret; @@ -805,7 +807,7 @@ static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev) for (i = 0; i < num; i++) { pos = igd_host_bridge_infos[i].offset; len = igd_host_bridge_infos[i].len; - rc = host_pci_config_read(pos, len, val); + rc = host_pci_config_read(pos, len, &val); if (rc) { return -ENODEV; } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6bfb908da7..414e0f9b7a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -375,6 +375,9 @@ static void *spapr_create_fdt_skel(hwaddr initrd_base, qemu_uuid[14], qemu_uuid[15]); _FDT((fdt_property_string(fdt, "vm,uuid", buf))); + if (qemu_uuid_set) { + _FDT((fdt_property_string(fdt, "system-id", buf))); + } g_free(buf); if (qemu_get_vm_name()) { @@ -1914,7 +1917,11 @@ static void ppc_spapr_init(MachineState *machine) } if (machine->usb) { - pci_create_simple(phb->bus, -1, "pci-ohci"); + if (smc->use_ohci_by_default) { + pci_create_simple(phb->bus, -1, "pci-ohci"); + } else { + pci_create_simple(phb->bus, -1, "nec-usb-xhci"); + } if (spapr->has_graphics) { USBBus *usb_bus = usb_bus_find(-1); @@ -2101,6 +2108,13 @@ static void spapr_machine_initfn(Object *obj) NULL); } +static void spapr_machine_finalizefn(Object *obj) +{ + sPAPRMachineState *spapr = SPAPR_MACHINE(obj); + + g_free(spapr->kvm_type); +} + static void ppc_cpu_do_nmi_on_cpu(void *arg) { CPUState *cs = arg; @@ -2262,6 +2276,13 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) NMIClass *nc = NMI_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); + mc->desc = "pSeries Logical Partition (PAPR compliant)"; + + /* + * We set up the default / latest behaviour here. The class_init + * functions for the specific versioned machine types can override + * these details for backwards compatibility + */ mc->init = ppc_spapr_init; mc->reset = ppc_spapr_reset; mc->block_default_type = IF_SCSI; @@ -2277,7 +2298,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) hc->unplug = spapr_machine_device_unplug; mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; - smc->dr_lmb_enabled = false; + smc->dr_lmb_enabled = true; fwc->get_dev_path = spapr_get_fw_dev_path; nc->nmi_monitor_handler = spapr_nmi; } @@ -2288,6 +2309,7 @@ static const TypeInfo spapr_machine_info = { .abstract = true, .instance_size = sizeof(sPAPRMachineState), .instance_init = spapr_machine_initfn, + .instance_finalize = spapr_machine_finalizefn, .class_size = sizeof(sPAPRMachineClass), .class_init = spapr_machine_class_init, .interfaces = (InterfaceInfo[]) { @@ -2298,166 +2320,164 @@ static const TypeInfo spapr_machine_info = { }, }; -#define SPAPR_COMPAT_2_4 \ - HW_COMPAT_2_4 - -#define SPAPR_COMPAT_2_3 \ - SPAPR_COMPAT_2_4 \ - HW_COMPAT_2_3 \ - {\ - .driver = "spapr-pci-host-bridge",\ - .property = "dynamic-reconfiguration",\ - .value = "off",\ - }, - -#define SPAPR_COMPAT_2_2 \ - SPAPR_COMPAT_2_3 \ - HW_COMPAT_2_2 \ - {\ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ - .property = "mem_win_size",\ - .value = "0x20000000",\ - }, - -#define SPAPR_COMPAT_2_1 \ - SPAPR_COMPAT_2_2 \ - HW_COMPAT_2_1 +#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ + static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ + void *data) \ + { \ + MachineClass *mc = MACHINE_CLASS(oc); \ + spapr_machine_##suffix##_class_options(mc); \ + if (latest) { \ + mc->alias = "pseries"; \ + mc->is_default = 1; \ + } \ + } \ + static void spapr_machine_##suffix##_instance_init(Object *obj) \ + { \ + MachineState *machine = MACHINE(obj); \ + spapr_machine_##suffix##_instance_options(machine); \ + } \ + static const TypeInfo spapr_machine_##suffix##_info = { \ + .name = MACHINE_TYPE_NAME("pseries-" verstr), \ + .parent = TYPE_SPAPR_MACHINE, \ + .class_init = spapr_machine_##suffix##_class_init, \ + .instance_init = spapr_machine_##suffix##_instance_init, \ + }; \ + static void spapr_machine_register_##suffix(void) \ + { \ + type_register(&spapr_machine_##suffix##_info); \ + } \ + machine_init(spapr_machine_register_##suffix) -static void spapr_compat_2_3(Object *obj) +/* + * pseries-2.6 + */ +static void spapr_machine_2_6_instance_options(MachineState *machine) { - savevm_skip_section_footers(); - global_state_set_optional(); } -static void spapr_compat_2_2(Object *obj) +static void spapr_machine_2_6_class_options(MachineClass *mc) { - spapr_compat_2_3(obj); + /* Defaults for the latest behaviour inherited from the base class */ } -static void spapr_compat_2_1(Object *obj) -{ - spapr_compat_2_2(obj); -} +DEFINE_SPAPR_MACHINE(2_6, "2.6", true); -static void spapr_machine_2_3_instance_init(Object *obj) +/* + * pseries-2.5 + */ +#define SPAPR_COMPAT_2_5 \ + HW_COMPAT_2_5 + +static void spapr_machine_2_5_instance_options(MachineState *machine) { - spapr_compat_2_3(obj); - spapr_machine_initfn(obj); } -static void spapr_machine_2_2_instance_init(Object *obj) +static void spapr_machine_2_5_class_options(MachineClass *mc) { - spapr_compat_2_2(obj); - spapr_machine_initfn(obj); + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_2_6_class_options(mc); + smc->use_ohci_by_default = true; + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); } -static void spapr_machine_2_1_instance_init(Object *obj) +DEFINE_SPAPR_MACHINE(2_5, "2.5", false); + +/* + * pseries-2.4 + */ +#define SPAPR_COMPAT_2_4 \ + HW_COMPAT_2_4 + +static void spapr_machine_2_4_instance_options(MachineState *machine) { - spapr_compat_2_1(obj); - spapr_machine_initfn(obj); + spapr_machine_2_5_instance_options(machine); } -static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) +static void spapr_machine_2_4_class_options(MachineClass *mc) { - MachineClass *mc = MACHINE_CLASS(oc); - static GlobalProperty compat_props[] = { - SPAPR_COMPAT_2_1 - { /* end of list */ } - }; + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); - mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; - mc->compat_props = compat_props; + spapr_machine_2_5_class_options(mc); + smc->dr_lmb_enabled = false; + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); } -static const TypeInfo spapr_machine_2_1_info = { - .name = MACHINE_TYPE_NAME("pseries-2.1"), - .parent = TYPE_SPAPR_MACHINE, - .class_init = spapr_machine_2_1_class_init, - .instance_init = spapr_machine_2_1_instance_init, -}; +DEFINE_SPAPR_MACHINE(2_4, "2.4", false); -static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) -{ - static GlobalProperty compat_props[] = { - SPAPR_COMPAT_2_2 - { /* end of list */ } - }; - MachineClass *mc = MACHINE_CLASS(oc); +/* + * pseries-2.3 + */ +#define SPAPR_COMPAT_2_3 \ + SPAPR_COMPAT_2_4 \ + HW_COMPAT_2_3 \ + {\ + .driver = "spapr-pci-host-bridge",\ + .property = "dynamic-reconfiguration",\ + .value = "off",\ + }, - mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; - mc->compat_props = compat_props; +static void spapr_machine_2_3_instance_options(MachineState *machine) +{ + spapr_machine_2_4_instance_options(machine); + savevm_skip_section_footers(); + global_state_set_optional(); } -static const TypeInfo spapr_machine_2_2_info = { - .name = MACHINE_TYPE_NAME("pseries-2.2"), - .parent = TYPE_SPAPR_MACHINE, - .class_init = spapr_machine_2_2_class_init, - .instance_init = spapr_machine_2_2_instance_init, -}; - -static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data) +static void spapr_machine_2_3_class_options(MachineClass *mc) { - static GlobalProperty compat_props[] = { - SPAPR_COMPAT_2_3 - { /* end of list */ } - }; - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3"; - mc->compat_props = compat_props; + spapr_machine_2_4_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); } +DEFINE_SPAPR_MACHINE(2_3, "2.3", false); -static const TypeInfo spapr_machine_2_3_info = { - .name = MACHINE_TYPE_NAME("pseries-2.3"), - .parent = TYPE_SPAPR_MACHINE, - .class_init = spapr_machine_2_3_class_init, - .instance_init = spapr_machine_2_3_instance_init, -}; +/* + * pseries-2.2 + */ + +#define SPAPR_COMPAT_2_2 \ + SPAPR_COMPAT_2_3 \ + HW_COMPAT_2_2 \ + {\ + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ + .property = "mem_win_size",\ + .value = "0x20000000",\ + }, -static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data) +static void spapr_machine_2_2_instance_options(MachineState *machine) { - static GlobalProperty compat_props[] = { - SPAPR_COMPAT_2_4 - { /* end of list */ } - }; - MachineClass *mc = MACHINE_CLASS(oc); + spapr_machine_2_3_instance_options(machine); +} - mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4"; - mc->compat_props = compat_props; +static void spapr_machine_2_2_class_options(MachineClass *mc) +{ + spapr_machine_2_3_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); } +DEFINE_SPAPR_MACHINE(2_2, "2.2", false); -static const TypeInfo spapr_machine_2_4_info = { - .name = MACHINE_TYPE_NAME("pseries-2.4"), - .parent = TYPE_SPAPR_MACHINE, - .class_init = spapr_machine_2_4_class_init, -}; +/* + * pseries-2.1 + */ +#define SPAPR_COMPAT_2_1 \ + SPAPR_COMPAT_2_2 \ + HW_COMPAT_2_1 -static void spapr_machine_2_5_class_init(ObjectClass *oc, void *data) +static void spapr_machine_2_1_instance_options(MachineState *machine) { - MachineClass *mc = MACHINE_CLASS(oc); - sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); - - mc->name = "pseries-2.5"; - mc->desc = "pSeries Logical Partition (PAPR compliant) v2.5"; - mc->alias = "pseries"; - mc->is_default = 1; - smc->dr_lmb_enabled = true; + spapr_machine_2_2_instance_options(machine); } -static const TypeInfo spapr_machine_2_5_info = { - .name = MACHINE_TYPE_NAME("pseries-2.5"), - .parent = TYPE_SPAPR_MACHINE, - .class_init = spapr_machine_2_5_class_init, -}; +static void spapr_machine_2_1_class_options(MachineClass *mc) +{ + spapr_machine_2_2_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); +} +DEFINE_SPAPR_MACHINE(2_1, "2.1", false); static void spapr_machine_register_types(void) { type_register_static(&spapr_machine_info); - type_register_static(&spapr_machine_2_1_info); - type_register_static(&spapr_machine_2_2_info); - type_register_static(&spapr_machine_2_3_info); - type_register_static(&spapr_machine_2_4_info); - type_register_static(&spapr_machine_2_5_info); } type_init(spapr_machine_register_types) diff --git a/hw/ppc/spapr_rtc.c b/hw/ppc/spapr_rtc.c index 34b27db709..b591a8ee23 100644 --- a/hw/ppc/spapr_rtc.c +++ b/hw/ppc/spapr_rtc.c @@ -200,7 +200,6 @@ static const TypeInfo spapr_rtc_info = { .name = TYPE_SPAPR_RTC, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(sPAPRRTCState), - .class_size = sizeof(XICSStateClass), .class_init = spapr_rtc_class_init, }; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index c51eb8e244..46f3b8d3ef 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -388,7 +388,7 @@ static void rtas_quiesce(PowerPCCPU *cpu, sPAPRMachineState *spapr, static VIOsPAPRDevice *reg_conflict(VIOsPAPRDevice *dev) { - VIOsPAPRBus *bus = DO_UPCAST(VIOsPAPRBus, bus, dev->qdev.parent_bus); + VIOsPAPRBus *bus = SPAPR_VIO_BUS(dev->qdev.parent_bus); BusChild *kid; VIOsPAPRDevice *other; @@ -449,7 +449,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp) } } else { /* Need to assign an address */ - VIOsPAPRBus *bus = DO_UPCAST(VIOsPAPRBus, bus, dev->qdev.parent_bus); + VIOsPAPRBus *bus = SPAPR_VIO_BUS(dev->qdev.parent_bus); do { dev->reg = bus->next_reg++; @@ -523,13 +523,12 @@ VIOsPAPRBus *spapr_vio_bus_init(void) DeviceState *dev; /* Create bridge device */ - dev = qdev_create(NULL, "spapr-vio-bridge"); + dev = qdev_create(NULL, TYPE_SPAPR_VIO_BRIDGE); qdev_init_nofail(dev); /* Create bus on bridge device */ - qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); - bus = DO_UPCAST(VIOsPAPRBus, bus, qbus); + bus = SPAPR_VIO_BUS(qbus); bus->next_reg = 0x71000000; /* hcall-vio */ @@ -567,9 +566,8 @@ static void spapr_vio_bridge_class_init(ObjectClass *klass, void *data) } static const TypeInfo spapr_vio_bridge_info = { - .name = "spapr-vio-bridge", + .name = TYPE_SPAPR_VIO_BRIDGE, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SysBusDevice), .class_init = spapr_vio_bridge_class_init, }; diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 19851ce6a9..343c3520de 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -1430,7 +1430,6 @@ void subch_device_save(SubchDev *s, QEMUFile *f) } qemu_put_byte(f, s->ccw_fmt_1); qemu_put_byte(f, s->ccw_no_data_cnt); - return; } int subch_device_load(SubchDev *s, QEMUFile *f) diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 98c726cfcd..8de35ffa05 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -123,7 +123,6 @@ void s390_pci_sclp_configure(int configure, SCCB *sccb) } psccb->header.response_code = cpu_to_be16(rc); - return; } static uint32_t s390_pci_get_pfid(PCIDevice *pdev) @@ -439,8 +438,6 @@ static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data, io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI; s390_io_interrupt(0, 0, 0, io_int_word); } - - return; } static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size) @@ -561,7 +558,6 @@ static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev, s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED, pbdev->fh, pbdev->fid); } - return; } static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev, diff --git a/hw/sh4/sh_pci.c b/hw/sh4/sh_pci.c index a2f6d9e0b6..4509053e1f 100644 --- a/hw/sh4/sh_pci.c +++ b/hw/sh4/sh_pci.c @@ -151,12 +151,11 @@ static int sh_pci_device_init(SysBusDevice *dev) return 0; } -static int sh_pci_host_init(PCIDevice *d) +static void sh_pci_host_realize(PCIDevice *d, Error **errp) { pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); - return 0; } static void sh_pci_host_class_init(ObjectClass *klass, void *data) @@ -164,7 +163,7 @@ static void sh_pci_host_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - k->init = sh_pci_host_init; + k->realize = sh_pci_host_realize; k->vendor_id = PCI_VENDOR_ID_HITACHI; k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R; /* diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index d6b929cf8f..7a433d33a7 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -363,6 +363,8 @@ void cpu_put_timer(QEMUFile *f, CPUTimer *s) qemu_put_be32s(f, &s->frequency); qemu_put_be32s(f, &s->disabled); qemu_put_be64s(f, &s->disabled_mask); + qemu_put_be32s(f, &s->npt); + qemu_put_be64s(f, &s->npt_mask); qemu_put_sbe64s(f, &s->clock_offset); timer_put(f, s->qtimer); @@ -373,6 +375,8 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s) qemu_get_be32s(f, &s->frequency); qemu_get_be32s(f, &s->disabled); qemu_get_be64s(f, &s->disabled_mask); + qemu_get_be32s(f, &s->npt); + qemu_get_be64s(f, &s->npt_mask); qemu_get_sbe64s(f, &s->clock_offset); timer_get(f, s->qtimer); @@ -380,15 +384,17 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s) static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, QEMUBHFunc *cb, uint32_t frequency, - uint64_t disabled_mask) + uint64_t disabled_mask, uint64_t npt_mask) { CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); timer->name = name; timer->frequency = frequency; timer->disabled_mask = disabled_mask; + timer->npt_mask = npt_mask; timer->disabled = 1; + timer->npt = 1; timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); @@ -494,17 +500,17 @@ static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) void cpu_tick_set_count(CPUTimer *timer, uint64_t count) { - uint64_t real_count = count & ~timer->disabled_mask; - uint64_t disabled_bit = count & timer->disabled_mask; + uint64_t real_count = count & ~timer->npt_mask; + uint64_t npt_bit = count & timer->npt_mask; int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - cpu_to_timer_ticks(real_count, timer->frequency); - TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n", + TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", timer->name, real_count, - timer->disabled?"disabled":"enabled", timer); + timer->npt ? "disabled" : "enabled", timer); - timer->disabled = disabled_bit ? 1 : 0; + timer->npt = npt_bit ? 1 : 0; timer->clock_offset = vm_clock_offset; } @@ -514,12 +520,13 @@ uint64_t cpu_tick_get_count(CPUTimer *timer) qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, timer->frequency); - TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n", + TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", timer->name, real_count, - timer->disabled?"disabled":"enabled", timer); + timer->npt ? "disabled" : "enabled", timer); - if (timer->disabled) - real_count |= timer->disabled_mask; + if (timer->npt) { + real_count |= timer->npt_mask; + } return real_count; } @@ -799,13 +806,16 @@ static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) env = &cpu->env; env->tick = cpu_timer_create("tick", cpu, tick_irq, - tick_frequency, TICK_NPT_MASK); + tick_frequency, TICK_INT_DIS, + TICK_NPT_MASK); env->stick = cpu_timer_create("stick", cpu, stick_irq, - stick_frequency, TICK_INT_DIS); + stick_frequency, TICK_INT_DIS, + TICK_NPT_MASK); env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, - hstick_frequency, TICK_INT_DIS); + hstick_frequency, TICK_INT_DIS, + TICK_NPT_MASK); reset_info = g_malloc0(sizeof(ResetData)); reset_info->cpu = cpu; diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 7f0391c786..d9d039b4ed 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -713,7 +713,7 @@ static void hpet_init(Object *obj) HPETState *s = HPET(obj); /* HPET Area */ - memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", 0x400); + memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_LEN); sysbus_init_mmio(sbd, &s->iomem); } diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c index af056c7df9..4177a87ea2 100644 --- a/hw/usb/dev-mtp.c +++ b/hw/usb/dev-mtp.c @@ -502,9 +502,9 @@ static void inotify_watchfn(void *arg) entry = g_new0(MTPMonEntry, 1); entry->handle = o->handle; entry->event = EVT_OBJ_REMOVED; - usb_mtp_object_free(s, o); trace_usb_mtp_inotify_event(s->dev.addr, o->path, event->mask, "Obj Deleted"); + usb_mtp_object_free(s, o); break; case IN_MODIFY: @@ -556,7 +556,7 @@ static int usb_mtp_inotify_init(MTPState *s) static void usb_mtp_inotify_cleanup(MTPState *s) { - MTPMonEntry *e; + MTPMonEntry *e, *p; if (!s->inotifyfd) { return; @@ -565,7 +565,7 @@ static void usb_mtp_inotify_cleanup(MTPState *s) qemu_set_fd_handler(s->inotifyfd, NULL, NULL, s); close(s->inotifyfd); - QTAILQ_FOREACH(e, &s->events, next) { + QTAILQ_FOREACH_SAFE(e, &s->events, next, p) { QTAILQ_REMOVE(&s->events, e, next); g_free(e); } diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 7d65818064..efeaf7371f 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -439,15 +439,37 @@ static void ohci_stop_endpoints(OHCIState *ohci) } } -/* Reset the controller */ -static void ohci_reset(void *opaque) +static void ohci_roothub_reset(OHCIState *ohci) { - OHCIState *ohci = opaque; OHCIPort *port; int i; ohci_bus_stop(ohci); - ohci->ctl = 0; + ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; + ohci->rhdesc_b = 0x0; /* Impl. specific */ + ohci->rhstatus = 0; + + for (i = 0; i < ohci->num_ports; i++) { + port = &ohci->rhport[i]; + port->ctrl = 0; + if (port->port.dev && port->port.dev->attached) { + usb_port_reset(&port->port); + } + } + if (ohci->async_td) { + usb_cancel_packet(&ohci->usb_packet); + ohci->async_td = 0; + } + ohci_stop_endpoints(ohci); +} + +/* Reset the controller */ +static void ohci_soft_reset(OHCIState *ohci) +{ + trace_usb_ohci_reset(ohci->name); + + ohci_bus_stop(ohci); + ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; ohci->old_ctl = 0; ohci->status = 0; ohci->intr_status = 0; @@ -470,25 +492,13 @@ static void ohci_reset(void *opaque) ohci->frame_number = 0; ohci->pstart = 0; ohci->lst = OHCI_LS_THRESH; +} - ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; - ohci->rhdesc_b = 0x0; /* Impl. specific */ - ohci->rhstatus = 0; - - for (i = 0; i < ohci->num_ports; i++) - { - port = &ohci->rhport[i]; - port->ctrl = 0; - if (port->port.dev && port->port.dev->attached) { - usb_port_reset(&port->port); - } - } - if (ohci->async_td) { - usb_cancel_packet(&ohci->usb_packet); - ohci->async_td = 0; - } - ohci_stop_endpoints(ohci); - trace_usb_ohci_reset(ohci->name); +static void ohci_hard_reset(OHCIState *ohci) +{ + ohci_soft_reset(ohci); + ohci->ctl = 0; + ohci_roothub_reset(ohci); } /* Get an array of dwords from main memory */ @@ -1231,11 +1241,16 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) return active; } -/* Generate a SOF event, and set a timer for EOF */ -static void ohci_sof(OHCIState *ohci) +/* set a timer for EOF */ +static void ohci_eof_timer(OHCIState *ohci) { ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); +} +/* Set a timer for EOF and generate a SOF event */ +static void ohci_sof(OHCIState *ohci) +{ + ohci_eof_timer(ohci); ohci_set_interrupt(ohci, OHCI_INTR_SF); } @@ -1343,7 +1358,12 @@ static int ohci_bus_start(OHCIState *ohci) trace_usb_ohci_start(ohci->name); - ohci_sof(ohci); + /* Delay the first SOF event by one frame time as + * linux driver is not ready to receive it and + * can meet some race conditions + */ + + ohci_eof_timer(ohci); return 1; } @@ -1436,12 +1456,15 @@ static void ohci_set_ctl(OHCIState *ohci, uint32_t val) break; case OHCI_USB_SUSPEND: ohci_bus_stop(ohci); + /* clear pending SF otherwise linux driver loops in ohci_irq() */ + ohci->intr_status &= ~OHCI_INTR_SF; + ohci_intr_update(ohci); break; case OHCI_USB_RESUME: trace_usb_ohci_resume(ohci->name); break; case OHCI_USB_RESET: - ohci_reset(ohci); + ohci_roothub_reset(ohci); break; } } @@ -1704,7 +1727,7 @@ static void ohci_mem_write(void *opaque, ohci->status |= val; if (ohci->status & OHCI_STATUS_HCR) - ohci_reset(ohci); + ohci_soft_reset(ohci); break; case 3: /* HcInterruptStatus */ @@ -1783,7 +1806,7 @@ static void ohci_mem_write(void *opaque, case 25: /* HcHReset */ ohci->hreset = val & ~OHCI_HRESET_FSBIR; if (val & OHCI_HRESET_FSBIR) - ohci_reset(ohci); + ohci_hard_reset(ohci); break; case 26: /* HcHInterruptEnable */ @@ -1960,7 +1983,7 @@ static void usb_ohci_reset_pci(DeviceState *d) OHCIPCIState *ohci = PCI_OHCI(dev); OHCIState *s = &ohci->state; - ohci_reset(s); + ohci_hard_reset(s); } #define TYPE_SYSBUS_OHCI "sysbus-ohci" @@ -1993,7 +2016,7 @@ static void usb_ohci_reset_sysbus(DeviceState *dev) OHCISysBusState *s = SYSBUS_OHCI(dev); OHCIState *ohci = &s->ohci; - ohci_reset(ohci); + ohci_hard_reset(ohci); } static Property ohci_pci_properties[] = { diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 1edef5945d..bd6b4df9ae 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1126,33 +1126,15 @@ static bool virtio_extra_state_needed(void *opaque) k->has_extra_state(qbus->parent); } -static void put_virtqueue_state(QEMUFile *f, void *pv, size_t size) -{ - VirtIODevice *vdev = pv; - int i; - - for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { - qemu_put_be64(f, vdev->vq[i].vring.avail); - qemu_put_be64(f, vdev->vq[i].vring.used); - } -} - -static int get_virtqueue_state(QEMUFile *f, void *pv, size_t size) -{ - VirtIODevice *vdev = pv; - int i; - - for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { - vdev->vq[i].vring.avail = qemu_get_be64(f); - vdev->vq[i].vring.used = qemu_get_be64(f); - } - return 0; -} - -static VMStateInfo vmstate_info_virtqueue = { +static const VMStateDescription vmstate_virtqueue = { .name = "virtqueue_state", - .get = get_virtqueue_state, - .put = put_virtqueue_state, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64(vring.avail, struct VirtQueue), + VMSTATE_UINT64(vring.used, struct VirtQueue), + VMSTATE_END_OF_LIST() + } }; static const VMStateDescription vmstate_virtio_virtqueues = { @@ -1161,44 +1143,20 @@ static const VMStateDescription vmstate_virtio_virtqueues = { .minimum_version_id = 1, .needed = &virtio_virtqueue_needed, .fields = (VMStateField[]) { - { - .name = "virtqueues", - .version_id = 0, - .field_exists = NULL, - .size = 0, - .info = &vmstate_info_virtqueue, - .flags = VMS_SINGLE, - .offset = 0, - }, + VMSTATE_STRUCT_VARRAY_KNOWN(vq, struct VirtIODevice, VIRTIO_QUEUE_MAX, + 0, vmstate_virtqueue, VirtQueue), VMSTATE_END_OF_LIST() } }; -static void put_ringsize_state(QEMUFile *f, void *pv, size_t size) -{ - VirtIODevice *vdev = pv; - int i; - - for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { - qemu_put_be32(f, vdev->vq[i].vring.num_default); - } -} - -static int get_ringsize_state(QEMUFile *f, void *pv, size_t size) -{ - VirtIODevice *vdev = pv; - int i; - - for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { - vdev->vq[i].vring.num_default = qemu_get_be32(f); - } - return 0; -} - -static VMStateInfo vmstate_info_ringsize = { +static const VMStateDescription vmstate_ringsize = { .name = "ringsize_state", - .get = get_ringsize_state, - .put = put_ringsize_state, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(vring.num_default, struct VirtQueue), + VMSTATE_END_OF_LIST() + } }; static const VMStateDescription vmstate_virtio_ringsize = { @@ -1207,15 +1165,8 @@ static const VMStateDescription vmstate_virtio_ringsize = { .minimum_version_id = 1, .needed = &virtio_ringsize_needed, .fields = (VMStateField[]) { - { - .name = "ringsize", - .version_id = 0, - .field_exists = NULL, - .size = 0, - .info = &vmstate_info_ringsize, - .flags = VMS_SINGLE, - .offset = 0, - }, + VMSTATE_STRUCT_VARRAY_KNOWN(vq, struct VirtIODevice, VIRTIO_QUEUE_MAX, + 0, vmstate_ringsize, VirtQueue), VMSTATE_END_OF_LIST() } }; @@ -1429,7 +1380,7 @@ int virtio_load(VirtIODevice *vdev, QEMUFile *f, int version_id) num = qemu_get_be32(f); if (num > VIRTIO_QUEUE_MAX) { - error_report("Invalid number of PCI queues: 0x%x", num); + error_report("Invalid number of virtqueues: 0x%x", num); return -1; } diff --git a/hw/xen/Makefile.objs b/hw/xen/Makefile.objs index a9ad7e70f7..d3670940b7 100644 --- a/hw/xen/Makefile.objs +++ b/hw/xen/Makefile.objs @@ -2,5 +2,4 @@ common-obj-$(CONFIG_XEN_BACKEND) += xen_backend.o xen_devconfig.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o -obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o -obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o xen_pt_graphics.o +obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_graphics.o xen_pt_msi.o |