diff options
Diffstat (limited to 'hw')
93 files changed, 446 insertions, 432 deletions
diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c index ea0fd95f84..9eb939f383 100644 --- a/hw/alpha_dp264.c +++ b/hw/alpha_dp264.c @@ -49,7 +49,7 @@ static void clipper_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *cpus[4]; + CPUAlphaState *cpus[4]; PCIBus *pci_bus; ISABus *isa_bus; qemu_irq rtc_irq; diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h index f9506c69a7..de40f8b613 100644 --- a/hw/alpha_sys.h +++ b/hw/alpha_sys.h @@ -11,7 +11,7 @@ #include "irq.h" -PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUState *[4], +PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4], pci_map_irq_fn); /* alpha_pci.c. */ diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index b539416589..872e1122e8 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -21,7 +21,7 @@ typedef struct TyphoonCchip { uint64_t drir; uint64_t dim[4]; uint32_t iic[4]; - CPUState *cpu[4]; + CPUAlphaState *cpu[4]; } TyphoonCchip; typedef struct TyphoonWindow { @@ -52,7 +52,7 @@ typedef struct TyphoonState { } TyphoonState; /* Called when one of DRIR or DIM changes. */ -static void cpu_irq_change(CPUState *env, uint64_t req) +static void cpu_irq_change(CPUAlphaState *env, uint64_t req) { /* If there are any non-masked interrupts, tell the cpu. */ if (env) { @@ -66,7 +66,7 @@ static void cpu_irq_change(CPUState *env, uint64_t req) static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size) { - CPUState *env = cpu_single_env; + CPUAlphaState *env = cpu_single_env; TyphoonState *s = opaque; uint64_t ret = 0; @@ -347,7 +347,7 @@ static void cchip_write(void *opaque, target_phys_addr_t addr, if ((newval ^ oldval) & 0xff0) { int i; for (i = 0; i < 4; ++i) { - CPUState *env = s->cchip.cpu[i]; + CPUAlphaState *env = s->cchip.cpu[i]; if (env) { /* IPI can be either cleared or set by the write. */ if (newval & (1 << (i + 8))) { @@ -655,7 +655,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) /* Deliver the interrupt to each CPU, considering each CPU's IIC. */ for (i = 0; i < 4; ++i) { - CPUState *env = s->cchip.cpu[i]; + CPUAlphaState *env = s->cchip.cpu[i]; if (env) { uint32_t iic = s->cchip.iic[i]; @@ -693,7 +693,7 @@ static void typhoon_alarm_timer(void *opaque) PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, qemu_irq *p_rtc_irq, - CPUState *cpus[4], pci_map_irq_fn sys_map_irq) + CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq) { const uint64_t MB = 1024 * 1024; const uint64_t GB = 1024 * MB; @@ -713,7 +713,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, /* Remember the CPUs so that we can deliver interrupts to them. */ for (i = 0; i < 4; i++) { - CPUState *env = cpus[i]; + CPUAlphaState *env = cpus[i]; s->cchip.cpu[i] = env; if (env) { env->alarm_timer = qemu_new_timer_ns(rtc_clock, diff --git a/hw/an5206.c b/hw/an5206.c index d57306d3ad..25407c0f50 100644 --- a/hw/an5206.c +++ b/hw/an5206.c @@ -24,7 +24,7 @@ static void an5206_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUM68KState *env; int kernel_size; uint64_t elf_entry; target_phys_addr_t entry; diff --git a/hw/apic.h b/hw/apic.h index d6d6d440ee..62179cebee 100644 --- a/hw/apic.h +++ b/hw/apic.h @@ -22,7 +22,7 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); /* pc.c */ -int cpu_is_bsp(CPUState *env); +int cpu_is_bsp(CPUX86State *env); DeviceState *cpu_get_current_apic(void); #endif diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 734bd82428..2f46e214cf 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -16,7 +16,7 @@ /* The CPU is also modeled as an interrupt controller. */ #define ARM_PIC_CPU_IRQ 0 #define ARM_PIC_CPU_FIQ 1 -qemu_irq *arm_pic_init_cpu(CPUState *env); +qemu_irq *arm_pic_init_cpu(CPUARMState *env); /* armv7m.c */ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, @@ -50,16 +50,16 @@ struct arm_boot_info { * perform any necessary CPU reset handling and set the PC for thei * secondary CPUs to point at this boot blob. */ - void (*write_secondary_boot)(CPUState *env, + void (*write_secondary_boot)(CPUARMState *env, const struct arm_boot_info *info); - void (*secondary_cpu_reset_hook)(CPUState *env, + void (*secondary_cpu_reset_hook)(CPUARMState *env, const struct arm_boot_info *info); /* Used internally by arm_boot.c */ int is_linux; target_phys_addr_t initrd_size; target_phys_addr_t entry; }; -void arm_load_kernel(CPUState *env, struct arm_boot_info *info); +void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info); /* Multiplication factor to convert from system clock ticks to qemu timer ticks. */ diff --git a/hw/arm_boot.c b/hw/arm_boot.c index fc669100c5..7447f5c169 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -59,7 +59,7 @@ static uint32_t smpboot[] = { 0 /* bootreg: Boot register address is held here */ }; -static void default_write_secondary(CPUState *env, +static void default_write_secondary(CPUARMState *env, const struct arm_boot_info *info) { int n; @@ -72,7 +72,7 @@ static void default_write_secondary(CPUState *env, info->smp_loader_start); } -static void default_reset_secondary(CPUState *env, +static void default_reset_secondary(CPUARMState *env, const struct arm_boot_info *info) { stl_phys_notdirty(info->smp_bootreg_addr, 0); @@ -274,10 +274,10 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) static void do_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUARMState *env = opaque; const struct arm_boot_info *info = env->boot_info; - cpu_reset(env); + cpu_state_reset(env); if (info) { if (!info->is_linux) { /* Jump to the entry point. */ @@ -300,7 +300,7 @@ static void do_cpu_reset(void *opaque) } } -void arm_load_kernel(CPUState *env, struct arm_boot_info *info) +void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) { int kernel_size; int initrd_size; diff --git a/hw/arm_pic.c b/hw/arm_pic.c index a2e8a73301..109496528c 100644 --- a/hw/arm_pic.c +++ b/hw/arm_pic.c @@ -13,7 +13,7 @@ /* Input 0 is IRQ and input 1 is FIQ. */ static void arm_pic_cpu_handler(void *opaque, int irq, int level) { - CPUState *env = (CPUState *)opaque; + CPUARMState *env = (CPUARMState *)opaque; switch (irq) { case ARM_PIC_CPU_IRQ: if (level) @@ -32,7 +32,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) } } -qemu_irq *arm_pic_init_cpu(CPUState *env) +qemu_irq *arm_pic_init_cpu(CPUARMState *env) { return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); } diff --git a/hw/armv7m.c b/hw/armv7m.c index 6b805798e6..4aac076e48 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -149,7 +149,7 @@ static void armv7m_bitband_init(void) static void armv7m_reset(void *opaque) { - cpu_reset((CPUState *)opaque); + cpu_state_reset((CPUARMState *)opaque); } /* Init CPU and memory for a v7-M based board. @@ -160,7 +160,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, int flash_size, int sram_size, const char *kernel_filename, const char *cpu_model) { - CPUState *env; + CPUARMState *env; DeviceState *nvic; /* FIXME: make this local state. */ static qemu_irq pic[64]; diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index c9301fda1d..2304e3533a 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -247,7 +247,7 @@ void axisdev88_init (ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUCRISState *env; DeviceState *dev; SysBusDevice *s; DriveInfo *nand; diff --git a/hw/cris-boot.c b/hw/cris-boot.c index 37894f8b53..ca6c52fa8e 100644 --- a/hw/cris-boot.c +++ b/hw/cris-boot.c @@ -29,12 +29,12 @@ static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUCRISState *env = opaque; struct cris_load_info *li; li = env->load_info; - cpu_reset(env); + cpu_state_reset(env); if (!li) { /* nothing more to do. */ @@ -60,7 +60,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x80000000LL; } -void cris_load_image(CPUState *env, struct cris_load_info *li) +void cris_load_image(CPUCRISState *env, struct cris_load_info *li) { uint64_t entry, high; int kcmdline_len; diff --git a/hw/cris-boot.h b/hw/cris-boot.h index e9caf8dee8..ecb9779e49 100644 --- a/hw/cris-boot.h +++ b/hw/cris-boot.h @@ -8,4 +8,4 @@ struct cris_load_info target_phys_addr_t entry; }; -void cris_load_image(CPUState *env, struct cris_load_info *li); +void cris_load_image(CPUCRISState *env, struct cris_load_info *li); diff --git a/hw/cris_pic_cpu.c b/hw/cris_pic_cpu.c index 06ae484950..3da0e86536 100644 --- a/hw/cris_pic_cpu.c +++ b/hw/cris_pic_cpu.c @@ -30,7 +30,7 @@ static void cris_pic_cpu_handler(void *opaque, int irq, int level) { - CPUState *env = (CPUState *)opaque; + CPUCRISState *env = (CPUCRISState *)opaque; int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; if (level) @@ -39,7 +39,7 @@ static void cris_pic_cpu_handler(void *opaque, int irq, int level) cpu_reset_interrupt(env, type); } -qemu_irq *cris_pic_init_cpu(CPUState *env) +qemu_irq *cris_pic_init_cpu(CPUCRISState *env) { return qemu_allocate_irqs(cris_pic_cpu_handler, env, 2); } diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c index e3c574008f..7cc7a99bfb 100644 --- a/hw/dummy_m68k.c +++ b/hw/dummy_m68k.c @@ -21,7 +21,7 @@ static void dummy_m68k_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUM68KState *env; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); int kernel_size; diff --git a/hw/etraxfs.h b/hw/etraxfs.h index 24e8fd880b..c62f94b7b7 100644 --- a/hw/etraxfs.h +++ b/hw/etraxfs.h @@ -25,7 +25,7 @@ #include "net.h" #include "etraxfs_dma.h" -qemu_irq *cris_pic_init_cpu(CPUState *env); +qemu_irq *cris_pic_init_cpu(CPUCRISState *env); /* Instantiate an ETRAXFS Ethernet MAC. */ static inline DeviceState * diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c index cecd819584..5f16b17835 100644 --- a/hw/etraxfs_ser.c +++ b/hw/etraxfs_ser.c @@ -78,7 +78,7 @@ static uint64_t ser_read(void *opaque, target_phys_addr_t addr, unsigned int size) { struct etrax_serial *s = opaque; - D(CPUState *env = s->env); + D(CPUCRISState *env = s->env); uint32_t r = 0; addr >>= 2; @@ -116,7 +116,7 @@ ser_write(void *opaque, target_phys_addr_t addr, struct etrax_serial *s = opaque; uint32_t value = val64; unsigned char ch = val64; - D(CPUState *env = s->env); + D(CPUCRISState *env = s->env); D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); addr >>= 2; diff --git a/hw/exynos4210.h b/hw/exynos4210.h index e7522f851a..c112e03bfb 100644 --- a/hw/exynos4210.h +++ b/hw/exynos4210.h @@ -83,7 +83,7 @@ typedef struct Exynos4210Irq { } Exynos4210Irq; typedef struct Exynos4210State { - CPUState * env[EXYNOS4210_NCPUS]; + CPUARMState * env[EXYNOS4210_NCPUS]; Exynos4210Irq irqs; qemu_irq *irq_table; diff --git a/hw/grlib.h b/hw/grlib.h index fdf4b1190a..e1c41378d4 100644 --- a/hw/grlib.h +++ b/hw/grlib.h @@ -42,7 +42,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno); static inline DeviceState *grlib_irqmp_create(target_phys_addr_t base, - CPUState *env, + CPUSPARCState *env, qemu_irq **cpu_irqs, uint32_t nr_irqs, set_pil_in_fn set_pil_in) diff --git a/hw/highbank.c b/hw/highbank.c index 489c00e5b9..906eed5a47 100644 --- a/hw/highbank.c +++ b/hw/highbank.c @@ -37,12 +37,12 @@ /* Board init. */ static void highbank_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUARMState *env = opaque; env->cp15.c15_config_base_address = GIC_BASE_ADDR; } -static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info) +static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info) { int n; uint32_t smpboot[] = { @@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info) rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); } -static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info) +static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info) { switch (info->nb_cpus) { case 4: @@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env = NULL; + CPUARMState *env = NULL; DeviceState *dev; SysBusDevice *busdev; qemu_irq *irqp; diff --git a/hw/integratorcp.c b/hw/integratorcp.c index 5b06c81c9b..9bdb9e62d6 100644 --- a/hw/integratorcp.c +++ b/hw/integratorcp.c @@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUARMState *env; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *ram_alias = g_new(MemoryRegion, 1); diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c index 9ca68f81aa..ffe7a521b7 100644 --- a/hw/kvm/apic.c +++ b/hw/kvm/apic.c @@ -124,7 +124,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s) static void do_inject_external_nmi(void *data) { APICCommonState *s = data; - CPUState *env = s->cpu_env; + CPUX86State *env = s->cpu_env; uint32_t lvt; int ret; diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c index e8bfeec3de..5d83625f4a 100644 --- a/hw/kvmvapic.c +++ b/hw/kvmvapic.c @@ -142,7 +142,7 @@ static void update_guest_rom_state(VAPICROMState *s) write_guest_rom_state(s); } -static int find_real_tpr_addr(VAPICROMState *s, CPUState *env) +static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) { target_phys_addr_t paddr; target_ulong addr; @@ -185,7 +185,7 @@ static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr) modrm_reg(opcode[1]) == instr->modrm_reg); } -static int evaluate_tpr_instruction(VAPICROMState *s, CPUState *env, +static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env, target_ulong *pip, TPRAccess access) { const TPRInstruction *instr; @@ -267,7 +267,7 @@ instruction_ok: return 0; } -static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip) +static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip) { target_phys_addr_t paddr; uint32_t rom_state_vaddr; @@ -330,7 +330,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip) * cannot be accessed or is considered invalid. This also ensures that we are * not patching the wrong guest. */ -static int get_kpcr_number(CPUState *env) +static int get_kpcr_number(CPUX86State *env) { struct kpcr { uint8_t fill1[0x1c]; @@ -347,7 +347,7 @@ static int get_kpcr_number(CPUState *env) return kpcr.number; } -static int vapic_enable(VAPICROMState *s, CPUState *env) +static int vapic_enable(VAPICROMState *s, CPUX86State *env) { int cpu_number = get_kpcr_number(env); target_phys_addr_t vapic_paddr; @@ -367,12 +367,12 @@ static int vapic_enable(VAPICROMState *s, CPUState *env) return 0; } -static void patch_byte(CPUState *env, target_ulong addr, uint8_t byte) +static void patch_byte(CPUX86State *env, target_ulong addr, uint8_t byte) { cpu_memory_rw_debug(env, addr, &byte, 1, 1); } -static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip, +static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip, uint32_t target) { uint32_t offset; @@ -382,7 +382,7 @@ static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip, cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1); } -static void patch_instruction(VAPICROMState *s, CPUState *env, target_ulong ip) +static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip) { target_phys_addr_t paddr; VAPICHandlers *handlers; @@ -439,7 +439,7 @@ void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip, TPRAccess access) { VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev); - CPUState *env = cpu; + CPUX86State *env = cpu; cpu_synchronize_state(env); @@ -475,7 +475,7 @@ static void vapic_enable_tpr_reporting(bool enable) VAPICEnableTPRReporting info = { .enable = enable, }; - CPUState *env; + CPUX86State *env; for (env = first_cpu; env != NULL; env = env->next_cpu) { info.apic = env->apic_state; @@ -606,7 +606,7 @@ static int vapic_prepare(VAPICROMState *s) static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data, unsigned int size) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; target_phys_addr_t rom_paddr; VAPICROMState *s = opaque; diff --git a/hw/leon3.c b/hw/leon3.c index 71d79a65a7..0a5ff165a1 100644 --- a/hw/leon3.c +++ b/hw/leon3.c @@ -42,16 +42,16 @@ #define MAX_PILS 16 typedef struct ResetData { - CPUState *env; + CPUSPARCState *env; uint32_t entry; /* save kernel entry in case of reset */ } ResetData; static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUSPARCState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->halted = 0; env->pc = s->entry; @@ -65,7 +65,7 @@ void leon3_irq_ack(void *irq_manager, int intno) static void leon3_set_pil_in(void *opaque, uint32_t pil_in) { - CPUState *env = (CPUState *)opaque; + CPUSPARCState *env = (CPUSPARCState *)opaque; assert(env != NULL); @@ -101,7 +101,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUSPARCState *env; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *prom = g_new(MemoryRegion, 1); diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c index 3cdf120a14..4dd4f0ab90 100644 --- a/hw/lm32_boards.c +++ b/hw/lm32_boards.c @@ -31,7 +31,7 @@ #include "exec-memory.h" typedef struct { - CPUState *env; + CPULM32State *env; target_phys_addr_t bootstrap_pc; target_phys_addr_t flash_base; target_phys_addr_t hwsetup_base; @@ -42,7 +42,7 @@ typedef struct { static void cpu_irq_handler(void *opaque, int irq, int level) { - CPUState *env = opaque; + CPULM32State *env = opaque; if (level) { cpu_interrupt(env, CPU_INTERRUPT_HARD); @@ -54,9 +54,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { ResetInfo *reset_info = opaque; - CPUState *env = reset_info->env; + CPULM32State *env = reset_info->env; - cpu_reset(env); + cpu_state_reset(env); /* init defaults */ env->pc = (uint32_t)reset_info->bootstrap_pc; @@ -75,7 +75,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *phys_ram = g_new(MemoryRegion, 1); @@ -163,7 +163,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *phys_ram = g_new(MemoryRegion, 1); diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 8b5cf8c81f..2b59c36ee6 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -24,8 +24,6 @@ #include "hw.h" #include "qemu-timer.h" #include "sysemu.h" -#include "pc.h" -#include "isa.h" #include "mc146818rtc.h" #ifdef TARGET_I386 diff --git a/hw/mcf.h b/hw/mcf.h index baa790b0c5..19a8b54778 100644 --- a/hw/mcf.h +++ b/hw/mcf.h @@ -17,7 +17,7 @@ void mcf_uart_mm_init(struct MemoryRegion *sysmem, /* mcf_intc.c */ qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem, target_phys_addr_t base, - CPUState *env); + CPUM68KState *env); /* mcf_fec.c */ void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd, @@ -25,6 +25,6 @@ void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd, /* mcf5206.c */ qemu_irq *mcf5206_init(struct MemoryRegion *sysmem, - uint32_t base, CPUState *env); + uint32_t base, CPUM68KState *env); #endif diff --git a/hw/mcf5206.c b/hw/mcf5206.c index 5110d833af..539b391338 100644 --- a/hw/mcf5206.c +++ b/hw/mcf5206.c @@ -145,7 +145,7 @@ static m5206_timer_state *m5206_timer_init(qemu_irq irq) /* System Integration Module. */ typedef struct { - CPUState *env; + CPUM68KState *env; MemoryRegion iomem; m5206_timer_state *timer[2]; void *uart[2]; @@ -525,7 +525,7 @@ static const MemoryRegionOps m5206_mbar_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUState *env) +qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, CPUM68KState *env) { m5206_mbar_state *s; qemu_irq *pic; diff --git a/hw/mcf5208.c b/hw/mcf5208.c index aa11a755cc..d3ebe8d9ad 100644 --- a/hw/mcf5208.c +++ b/hw/mcf5208.c @@ -192,7 +192,7 @@ static void mcf5208evb_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUM68KState *env; int kernel_size; uint64_t elf_entry; target_phys_addr_t entry; diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c index 0b498dd3ac..cc1a5f3763 100644 --- a/hw/mcf_intc.c +++ b/hw/mcf_intc.c @@ -16,7 +16,7 @@ typedef struct { uint64_t ifr; uint64_t enabled; uint8_t icr[64]; - CPUState *env; + CPUM68KState *env; int active_vector; } mcf_intc_state; @@ -139,7 +139,7 @@ static const MemoryRegionOps mcf_intc_ops = { qemu_irq *mcf_intc_init(MemoryRegion *sysmem, target_phys_addr_t base, - CPUState *env) + CPUM68KState *env) { mcf_intc_state *s; diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c index b2f96df344..b4fbb10dd0 100644 --- a/hw/microblaze_boot.c +++ b/hw/microblaze_boot.c @@ -35,7 +35,7 @@ static struct { - void (*machine_cpu_reset)(CPUState *); + void (*machine_cpu_reset)(CPUMBState *); uint32_t bootstrap_pc; uint32_t cmdline; uint32_t fdt; @@ -43,9 +43,9 @@ static struct static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUMBState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->regs[5] = boot_info.cmdline; env->regs[7] = boot_info.fdt; env->sregs[SR_PC] = boot_info.bootstrap_pc; @@ -99,9 +99,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x30000000LL; } -void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUState *)) + void (*machine_cpu_reset)(CPUMBState *)) { QemuOpts *machine_opts; diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h index 69d4ac635b..bf9d136f12 100644 --- a/hw/microblaze_boot.h +++ b/hw/microblaze_boot.h @@ -3,8 +3,8 @@ #include "hw.h" -void microblaze_load_kernel(CPUState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUState *)); + void (*machine_cpu_reset)(CPUMBState *)); #endif /* __MICROBLAZE_BOOT __ */ diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c index 8b5623ce28..ff36a526fc 100644 --- a/hw/microblaze_pic_cpu.c +++ b/hw/microblaze_pic_cpu.c @@ -29,7 +29,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) { - CPUState *env = (CPUState *)opaque; + CPUMBState *env = (CPUMBState *)opaque; int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; if (level) @@ -38,7 +38,7 @@ static void microblaze_pic_cpu_handler(void *opaque, int irq, int level) cpu_reset_interrupt(env, type); } -qemu_irq *microblaze_pic_init_cpu(CPUState *env) +qemu_irq *microblaze_pic_init_cpu(CPUMBState *env) { return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2); } diff --git a/hw/microblaze_pic_cpu.h b/hw/microblaze_pic_cpu.h index 4c76275976..43090a48ef 100644 --- a/hw/microblaze_pic_cpu.h +++ b/hw/microblaze_pic_cpu.h @@ -3,6 +3,6 @@ #include "qemu-common.h" -qemu_irq *microblaze_pic_init_cpu(CPUState *env); +qemu_irq *microblaze_pic_init_cpu(CPUMBState *env); #endif /* MICROBLAZE_PIC_CPU_H */ diff --git a/hw/milkymist.c b/hw/milkymist.c index eaef0c24c3..8bb6a97b22 100644 --- a/hw/milkymist.c +++ b/hw/milkymist.c @@ -37,7 +37,7 @@ #define KERNEL_LOAD_ADDR 0x40000000 typedef struct { - CPUState *env; + CPULM32State *env; target_phys_addr_t bootstrap_pc; target_phys_addr_t flash_base; target_phys_addr_t initrd_base; @@ -47,7 +47,7 @@ typedef struct { static void cpu_irq_handler(void *opaque, int irq, int level) { - CPUState *env = opaque; + CPULM32State *env = opaque; if (level) { cpu_interrupt(env, CPU_INTERRUPT_HARD); @@ -59,9 +59,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { ResetInfo *reset_info = opaque; - CPUState *env = reset_info->env; + CPULM32State *env = reset_info->env; - cpu_reset(env); + cpu_state_reset(env); /* init defaults */ env->pc = reset_info->bootstrap_pc; @@ -79,7 +79,7 @@ milkymist_init(ram_addr_t ram_size_not_used, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPULM32State *env; int kernel_size; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); diff --git a/hw/mips_cpudevs.h b/hw/mips_cpudevs.h index db82b4105c..6bea24bf10 100644 --- a/hw/mips_cpudevs.h +++ b/hw/mips_cpudevs.h @@ -7,9 +7,9 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); /* mips_int.c */ -void cpu_mips_irq_init_cpu(CPUState *env); +void cpu_mips_irq_init_cpu(CPUMIPSState *env); /* mips_timer.c */ -void cpu_mips_clock_init(CPUState *); +void cpu_mips_clock_init(CPUMIPSState *); #endif diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c index efdfdc29ff..37dc711e08 100644 --- a/hw/mips_fulong2e.c +++ b/hw/mips_fulong2e.c @@ -102,7 +102,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index, va_end(ap); } -static int64_t load_kernel (CPUState *env) +static int64_t load_kernel (CPUMIPSState *env) { int64_t kernel_entry, kernel_low, kernel_high; int index = 0; @@ -168,7 +168,7 @@ static int64_t load_kernel (CPUState *env) return kernel_entry; } -static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr) +static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr) { uint32_t *p; @@ -198,9 +198,9 @@ static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr) static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUMIPSState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); /* TODO: 2E reset stuff */ if (loaderparams.kernel_filename) { env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); @@ -248,7 +248,7 @@ static void network_init (void) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUMIPSState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -272,7 +272,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device, i2c_bus *smbus; int i; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - CPUState *env; + CPUMIPSState *env; /* init CPUs */ if (cpu_model == NULL) { diff --git a/hw/mips_int.c b/hw/mips_int.c index 477f6abf95..6423fd0bd9 100644 --- a/hw/mips_int.c +++ b/hw/mips_int.c @@ -26,7 +26,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) { - CPUState *env = (CPUState *)opaque; + CPUMIPSState *env = (CPUMIPSState *)opaque; if (irq < 0 || irq > 7) return; @@ -44,7 +44,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) } } -void cpu_mips_irq_init_cpu(CPUState *env) +void cpu_mips_irq_init_cpu(CPUMIPSState *env) { qemu_irq *qi; int i; @@ -55,7 +55,7 @@ void cpu_mips_irq_init_cpu(CPUState *env) } } -void cpu_mips_soft_irq(CPUState *env, int irq, int level) +void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) { if (irq < 0 || irq > 2) { return; diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index 2b4678e170..a6bc7badff 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -50,8 +50,8 @@ enum jazz_model_e static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; - cpu_reset(env); + CPUMIPSState *env = opaque; + cpu_state_reset(env); } static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) @@ -97,7 +97,7 @@ static const MemoryRegionOps dma_dummy_ops = { static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUMIPSState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -112,7 +112,7 @@ static void mips_jazz_init(MemoryRegion *address_space, { char *filename; int bios_size, n; - CPUState *env; + CPUMIPSState *env; qemu_irq *rc4030, *i8259; rc4030_dma *dmas; void* rc4030_opaque; diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 866699dbf0..5e26775e64 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -500,7 +500,7 @@ static void network_init(void) a3 - RAM size in bytes */ -static void write_bootloader (CPUState *env, uint8_t *base, +static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_entry) { uint32_t *p; @@ -736,7 +736,7 @@ static int64_t load_kernel (void) return kernel_entry; } -static void malta_mips_config(CPUState *env) +static void malta_mips_config(CPUMIPSState *env) { env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC); @@ -744,8 +744,8 @@ static void malta_mips_config(CPUState *env) static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; - cpu_reset(env); + CPUMIPSState *env = opaque; + cpu_state_reset(env); /* The bootloader does not need to be rewritten as it is located in a read only location. The kernel location and the arguments table @@ -759,7 +759,7 @@ static void main_cpu_reset(void *opaque) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUMIPSState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -781,7 +781,7 @@ void mips_malta_init (ram_addr_t ram_size, int64_t kernel_entry; PCIBus *pci_bus; ISABus *isa_bus; - CPUState *env; + CPUMIPSState *env; qemu_irq *isa_irq; qemu_irq *cpu_exit_irq; int piix4_devfn; diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index 76c95b2ec0..1ea7b58323 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -46,7 +46,7 @@ static struct _loaderparams { } loaderparams; typedef struct ResetData { - CPUState *env; + CPUMIPSState *env; uint64_t vector; } ResetData; @@ -105,9 +105,9 @@ static int64_t load_kernel(void) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUMIPSState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->active_tc.PC = s->vector & ~(target_ulong)1; if (s->vector & 1) { env->hflags |= MIPS_HFLAG_M16; @@ -140,7 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); - CPUState *env; + CPUMIPSState *env; ResetData *reset_info; int bios_size; diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index 83401f0648..e2da49c09d 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = { }; typedef struct ResetData { - CPUState *env; + CPUMIPSState *env; uint64_t vector; } ResetData; @@ -143,9 +143,9 @@ static int64_t load_kernel(void) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUMIPSState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->active_tc.PC = s->vector; } @@ -162,7 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size, MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); int bios_size; - CPUState *env; + CPUMIPSState *env; ResetData *reset_info; int i; qemu_irq *i8259; diff --git a/hw/mips_timer.c b/hw/mips_timer.c index cf6ac694e3..7aa9004a0e 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -27,7 +27,7 @@ #define TIMER_FREQ 100 * 1000 * 1000 /* XXX: do not use a global */ -uint32_t cpu_mips_get_random (CPUState *env) +uint32_t cpu_mips_get_random (CPUMIPSState *env) { static uint32_t lfsr = 1; static uint32_t prev_idx = 0; @@ -42,7 +42,7 @@ uint32_t cpu_mips_get_random (CPUState *env) } /* MIPS R4K timer */ -static void cpu_mips_timer_update(CPUState *env) +static void cpu_mips_timer_update(CPUMIPSState *env) { uint64_t now, next; uint32_t wait; @@ -55,7 +55,7 @@ static void cpu_mips_timer_update(CPUState *env) } /* Expire the timer. */ -static void cpu_mips_timer_expire(CPUState *env) +static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); if (env->insn_flags & ISA_MIPS32R2) { @@ -64,7 +64,7 @@ static void cpu_mips_timer_expire(CPUState *env) qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } -uint32_t cpu_mips_get_count (CPUState *env) +uint32_t cpu_mips_get_count (CPUMIPSState *env) { if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; @@ -83,7 +83,7 @@ uint32_t cpu_mips_get_count (CPUState *env) } } -void cpu_mips_store_count (CPUState *env, uint32_t count) +void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) { if (env->CP0_Cause & (1 << CP0Ca_DC)) env->CP0_Count = count; @@ -97,7 +97,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count) } } -void cpu_mips_store_compare (CPUState *env, uint32_t value) +void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value) { env->CP0_Compare = value; if (!(env->CP0_Cause & (1 << CP0Ca_DC))) @@ -107,12 +107,12 @@ void cpu_mips_store_compare (CPUState *env, uint32_t value) qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } -void cpu_mips_start_count(CPUState *env) +void cpu_mips_start_count(CPUMIPSState *env) { cpu_mips_store_count(env, env->CP0_Count); } -void cpu_mips_stop_count(CPUState *env) +void cpu_mips_stop_count(CPUMIPSState *env) { /* Store the current value */ env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock), @@ -121,7 +121,7 @@ void cpu_mips_stop_count(CPUState *env) static void mips_timer_cb (void *opaque) { - CPUState *env; + CPUMIPSState *env; env = opaque; #if 0 @@ -139,7 +139,7 @@ static void mips_timer_cb (void *opaque) env->CP0_Count--; } -void cpu_mips_clock_init (CPUState *env) +void cpu_mips_clock_init (CPUMIPSState *env) { env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env); env->CP0_Compare = 0; diff --git a/hw/mpc8544_guts.c b/hw/mpc8544_guts.c index aeb2de7ccc..13b0dddc1e 100644 --- a/hw/mpc8544_guts.c +++ b/hw/mpc8544_guts.c @@ -62,7 +62,7 @@ static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr, unsigned size) { uint32_t value = 0; - CPUState *env = cpu_single_env; + CPUPPCState *env = cpu_single_env; addr &= MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/musicpal.c b/hw/musicpal.c index 187a1aef5e..c9f845a3f2 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUARMState *env; qemu_irq *cpu_pic; qemu_irq pic[32]; DeviceState *dev; diff --git a/hw/omap.h b/hw/omap.h index 60fa34cef2..63ef847ed0 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -813,7 +813,7 @@ struct omap_mpu_state_s { omap3630, } mpu_model; - CPUState *env; + CPUARMState *env; qemu_irq *drq; diff --git a/hw/omap1.c b/hw/omap1.c index 1aa5f2388b..5317b9be2b 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque) omap_lpg_reset(mpu->led[0]); omap_lpg_reset(mpu->led[1]); omap_clkm_reset(mpu); - cpu_reset(mpu->env); + cpu_state_reset(mpu->env); } static const struct omap_map_s { diff --git a/hw/omap2.c b/hw/omap2.c index a6851b0fb0..157defb393 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque) omap_mcspi_reset(mpu->mcspi[1]); omap_i2c_reset(mpu->i2c[0]); omap_i2c_reset(mpu->i2c[1]); - cpu_reset(mpu->env); + cpu_state_reset(mpu->env); } static int omap2_validate_addr(struct omap_mpu_state_s *s, diff --git a/hw/pc.c b/hw/pc.c index bb9867b070..83a1b5b32b 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -140,7 +140,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *arg) smm_arg = arg; } -void cpu_smm_update(CPUState *env) +void cpu_smm_update(CPUX86State *env) { if (smm_set && smm_arg && env == first_cpu) smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); @@ -148,7 +148,7 @@ void cpu_smm_update(CPUState *env) /* IRQ handling */ -int cpu_get_pic_interrupt(CPUState *env) +int cpu_get_pic_interrupt(CPUX86State *env) { int intno; @@ -167,7 +167,7 @@ int cpu_get_pic_interrupt(CPUState *env) static void pic_irq_request(void *opaque, int irq, int level) { - CPUState *env = first_cpu; + CPUX86State *env = first_cpu; DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); if (env->apic_state) { @@ -522,7 +522,7 @@ type_init(port92_register_types) static void handle_a20_line_change(void *opaque, int irq, int level) { - CPUState *cpu = opaque; + CPUX86State *cpu = opaque; /* XXX: send to all CPUs ? */ /* XXX: add logic to handle multiple A20 line sources */ @@ -869,7 +869,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) nb_ne2k++; } -int cpu_is_bsp(CPUState *env) +int cpu_is_bsp(CPUX86State *env) { /* We hard-wire the BSP to the first CPU. */ return env->cpu_index == 0; @@ -917,7 +917,7 @@ static DeviceState *apic_init(void *env, uint8_t apic_id) void pc_acpi_smi_interrupt(void *opaque, int irq, int level) { - CPUState *s = opaque; + CPUX86State *s = opaque; if (level) { cpu_interrupt(s, CPU_INTERRUPT_SMI); @@ -926,15 +926,15 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level) static void pc_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUX86State *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->halted = !cpu_is_bsp(env); } -static CPUState *pc_new_cpu(const char *cpu_model) +static CPUX86State *pc_new_cpu(const char *cpu_model) { - CPUState *env; + CPUX86State *env; env = cpu_init(cpu_model); if (!env) { @@ -1070,7 +1070,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; if (env && level) { cpu_exit(env); diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index c87fa1186c..31a434872d 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -54,7 +54,7 @@ #define AXIENET_BASEADDR 0x82780000 #define AXIDMA_BASEADDR 0x84600000 -static void machine_cpu_reset(CPUState *env) +static void machine_cpu_reset(CPUMBState *env) { env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ @@ -75,7 +75,7 @@ petalogix_ml605_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev; - CPUState *env; + CPUMBState *env; DriveInfo *dinfo; int i; target_phys_addr_t ddr_base = MEMORY_BASEADDR; diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 2cb0b1f10a..ff154c7aa9 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -49,7 +49,7 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 -static void machine_cpu_reset(CPUState *env) +static void machine_cpu_reset(CPUMBState *env) { /* FIXME: move to machine specfic cpu reset */ env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */ @@ -63,7 +63,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { DeviceState *dev; - CPUState *env; + CPUMBState *env; DriveInfo *dinfo; int i; target_phys_addr_t ddr_base = MEMORY_BASEADDR; diff --git a/hw/ppc.c b/hw/ppc.c index 59882e2ecd..98546de991 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -47,10 +47,10 @@ # define LOG_TB(...) do { } while (0) #endif -static void cpu_ppc_tb_stop (CPUState *env); -static void cpu_ppc_tb_start (CPUState *env); +static void cpu_ppc_tb_stop (CPUPPCState *env); +static void cpu_ppc_tb_start (CPUPPCState *env); -void ppc_set_irq(CPUState *env, int n_IRQ, int level) +void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level) { unsigned int old_pending = env->pending_interrupts; @@ -77,7 +77,7 @@ void ppc_set_irq(CPUState *env, int n_IRQ, int level) /* PowerPC 6xx / 7xx internal IRQ controller */ static void ppc6xx_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -131,13 +131,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) /* Level sensitive - active low */ if (level) { LOG_IRQ("%s: reset the CPU\n", __func__); - env->interrupt_request |= CPU_INTERRUPT_EXITTB; - /* XXX: TOFIX */ -#if 0 - cpu_reset(env); -#else - qemu_system_reset_request(); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); } break; case PPC6xx_INPUT_SRESET: @@ -157,7 +151,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) } } -void ppc6xx_irq_init (CPUState *env) +void ppc6xx_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, PPC6xx_INPUT_NB); @@ -167,7 +161,7 @@ void ppc6xx_irq_init (CPUState *env) /* PowerPC 970 internal IRQ controller */ static void ppc970_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -214,10 +208,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level) case PPC970_INPUT_HRESET: /* Level sensitive - active low */ if (level) { -#if 0 // XXX: TOFIX - LOG_IRQ("%s: reset the CPU\n", __func__); - cpu_reset(env); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); } break; case PPC970_INPUT_SRESET: @@ -242,7 +233,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level) } } -void ppc970_irq_init (CPUState *env) +void ppc970_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, PPC970_INPUT_NB); @@ -251,7 +242,7 @@ void ppc970_irq_init (CPUState *env) /* POWER7 internal IRQ controller */ static void power7_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, env, pin, level); @@ -275,7 +266,7 @@ static void power7_set_irq (void *opaque, int pin, int level) } } -void ppcPOWER7_irq_init (CPUState *env) +void ppcPOWER7_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env, POWER7_INPUT_NB); @@ -285,7 +276,7 @@ void ppcPOWER7_irq_init (CPUState *env) /* PowerPC 40x internal IRQ controller */ static void ppc40x_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -355,7 +346,7 @@ static void ppc40x_set_irq (void *opaque, int pin, int level) } } -void ppc40x_irq_init (CPUState *env) +void ppc40x_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, env, PPC40x_INPUT_NB); @@ -364,7 +355,7 @@ void ppc40x_irq_init (CPUState *env) /* PowerPC E500 internal IRQ controller */ static void ppce500_set_irq (void *opaque, int pin, int level) { - CPUState *env = opaque; + CPUPPCState *env = opaque; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -416,7 +407,7 @@ static void ppce500_set_irq (void *opaque, int pin, int level) } } -void ppce500_irq_init (CPUState *env) +void ppce500_irq_init (CPUPPCState *env) { env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, env, PPCE500_INPUT_NB); @@ -430,7 +421,7 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; } -uint64_t cpu_ppc_load_tbl (CPUState *env) +uint64_t cpu_ppc_load_tbl (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -445,7 +436,7 @@ uint64_t cpu_ppc_load_tbl (CPUState *env) return tb; } -static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) +static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -456,7 +447,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) return tb >> 32; } -uint32_t cpu_ppc_load_tbu (CPUState *env) +uint32_t cpu_ppc_load_tbu (CPUPPCState *env) { if (kvm_enabled()) { return env->spr[SPR_TBU]; @@ -473,7 +464,7 @@ static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, __func__, value, *tb_offsetp); } -void cpu_ppc_store_tbl (CPUState *env, uint32_t value) +void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -484,7 +475,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value) &tb_env->tb_offset, tb | (uint64_t)value); } -static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) +static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -495,12 +486,12 @@ static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) &tb_env->tb_offset, ((uint64_t)value << 32) | tb); } -void cpu_ppc_store_tbu (CPUState *env, uint32_t value) +void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_tbu(env, value); } -uint64_t cpu_ppc_load_atbl (CPUState *env) +uint64_t cpu_ppc_load_atbl (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -511,7 +502,7 @@ uint64_t cpu_ppc_load_atbl (CPUState *env) return tb; } -uint32_t cpu_ppc_load_atbu (CPUState *env) +uint32_t cpu_ppc_load_atbu (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -522,7 +513,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env) return tb >> 32; } -void cpu_ppc_store_atbl (CPUState *env, uint32_t value) +void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -533,7 +524,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value) &tb_env->atb_offset, tb | (uint64_t)value); } -void cpu_ppc_store_atbu (CPUState *env, uint32_t value) +void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb; @@ -544,7 +535,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value) &tb_env->atb_offset, ((uint64_t)value << 32) | tb); } -static void cpu_ppc_tb_stop (CPUState *env) +static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb, atb, vmclk; @@ -566,7 +557,7 @@ static void cpu_ppc_tb_stop (CPUState *env) } } -static void cpu_ppc_tb_start (CPUState *env) +static void cpu_ppc_tb_start (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t tb, atb, vmclk; @@ -587,7 +578,7 @@ static void cpu_ppc_tb_start (CPUState *env) } } -static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) +static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) { ppc_tb_t *tb_env = env->tb_env; uint32_t decr; @@ -606,7 +597,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) return decr; } -uint32_t cpu_ppc_load_decr (CPUState *env) +uint32_t cpu_ppc_load_decr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; @@ -617,14 +608,14 @@ uint32_t cpu_ppc_load_decr (CPUState *env) return _cpu_ppc_load_decr(env, tb_env->decr_next); } -uint32_t cpu_ppc_load_hdecr (CPUState *env) +uint32_t cpu_ppc_load_hdecr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; return _cpu_ppc_load_decr(env, tb_env->hdecr_next); } -uint64_t cpu_ppc_load_purr (CPUState *env) +uint64_t cpu_ppc_load_purr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; uint64_t diff; @@ -637,23 +628,23 @@ uint64_t cpu_ppc_load_purr (CPUState *env) /* When decrementer expires, * all we need to do is generate or queue a CPU exception */ -static inline void cpu_ppc_decr_excp(CPUState *env) +static inline void cpu_ppc_decr_excp(CPUPPCState *env) { /* Raise it */ LOG_TB("raise decrementer exception\n"); ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); } -static inline void cpu_ppc_hdecr_excp(CPUState *env) +static inline void cpu_ppc_hdecr_excp(CPUPPCState *env) { /* Raise it */ LOG_TB("raise decrementer exception\n"); ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); } -static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, +static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp, struct QEMUTimer *timer, - void (*raise_excp)(CPUState *), + void (*raise_excp)(CPUPPCState *), uint32_t decr, uint32_t value, int is_excp) { @@ -690,7 +681,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, } } -static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, +static inline void _cpu_ppc_store_decr(CPUPPCState *env, uint32_t decr, uint32_t value, int is_excp) { ppc_tb_t *tb_env = env->tb_env; @@ -699,7 +690,7 @@ static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, &cpu_ppc_decr_excp, decr, value, is_excp); } -void cpu_ppc_store_decr (CPUState *env, uint32_t value) +void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0); } @@ -709,7 +700,7 @@ static void cpu_ppc_decr_cb (void *opaque) _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, +static inline void _cpu_ppc_store_hdecr(CPUPPCState *env, uint32_t hdecr, uint32_t value, int is_excp) { ppc_tb_t *tb_env = env->tb_env; @@ -720,7 +711,7 @@ static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, } } -void cpu_ppc_store_hdecr (CPUState *env, uint32_t value) +void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0); } @@ -730,7 +721,7 @@ static void cpu_ppc_hdecr_cb (void *opaque) _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -void cpu_ppc_store_purr (CPUState *env, uint64_t value) +void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value) { ppc_tb_t *tb_env = env->tb_env; @@ -740,7 +731,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) { - CPUState *env = opaque; + CPUPPCState *env = opaque; ppc_tb_t *tb_env = env->tb_env; tb_env->tb_freq = freq; @@ -755,7 +746,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) } /* Set up (once) timebase frequency (in Hz) */ -clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) +clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) { ppc_tb_t *tb_env; @@ -778,28 +769,28 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) /* Specific helpers for POWER & PowerPC 601 RTC */ #if 0 -static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) +static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env) { return cpu_ppc_tb_init(env, 7812500); } #endif -void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) +void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) { _cpu_ppc_store_tbu(env, value); } -uint32_t cpu_ppc601_load_rtcu (CPUState *env) +uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) { return _cpu_ppc_load_tbu(env); } -void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) +void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) { cpu_ppc_store_tbl(env, value & 0x3FFFFF80); } -uint32_t cpu_ppc601_load_rtcl (CPUState *env) +uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) { return cpu_ppc_load_tbl(env) & 0x3FFFFF80; } @@ -823,7 +814,7 @@ struct ppc40x_timer_t { /* Fixed interval timer */ static void cpu_4xx_fit_cb (void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; uint64_t now, next; @@ -862,7 +853,7 @@ static void cpu_4xx_fit_cb (void *opaque) } /* Programmable interval timer */ -static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) +static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) { ppc40x_timer_t *ppc40x_timer; uint64_t now, next; @@ -891,7 +882,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) static void cpu_4xx_pit_cb (void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; @@ -913,7 +904,7 @@ static void cpu_4xx_pit_cb (void *opaque) /* Watchdog timer */ static void cpu_4xx_wdt_cb (void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; uint64_t now, next; @@ -978,7 +969,7 @@ static void cpu_4xx_wdt_cb (void *opaque) } } -void store_40x_pit (CPUState *env, target_ulong val) +void store_40x_pit (CPUPPCState *env, target_ulong val) { ppc_tb_t *tb_env; ppc40x_timer_t *ppc40x_timer; @@ -990,14 +981,14 @@ void store_40x_pit (CPUState *env, target_ulong val) start_stop_pit(env, tb_env, 0); } -target_ulong load_40x_pit (CPUState *env) +target_ulong load_40x_pit (CPUPPCState *env) { return cpu_ppc_load_decr(env); } static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) { - CPUState *env = opaque; + CPUPPCState *env = opaque; ppc_tb_t *tb_env = env->tb_env; LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, @@ -1007,7 +998,7 @@ static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) /* XXX: we should also update all timers */ } -clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, +clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, unsigned int decr_excp) { ppc_tb_t *tb_env; @@ -1093,7 +1084,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) return -1; } -int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, +int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, dcr_read_cb dcr_read, dcr_write_cb dcr_write) { ppc_dcr_t *dcr_env; @@ -1116,7 +1107,7 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, return 0; } -int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), +int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), int (*write_error)(int dcrn)) { ppc_dcr_t *dcr_env; diff --git a/hw/ppc.h b/hw/ppc.h index 9f911704af..2f3ea277bc 100644 --- a/hw/ppc.h +++ b/hw/ppc.h @@ -1,4 +1,4 @@ -void ppc_set_irq (CPUState *env, int n_IRQ, int level); +void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level); /* PowerPC hardware exceptions management helpers */ typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); @@ -43,32 +43,32 @@ struct ppc_tb_t { */ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); -clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); +clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq); /* Embedded PowerPC DCR management */ typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val); -int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), +int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn), int (*dcr_write_error)(int dcrn)); -int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, +int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, dcr_read_cb drc_read, dcr_write_cb dcr_write); -clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, +clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, unsigned int decr_excp); /* Embedded PowerPC reset */ -void ppc40x_core_reset (CPUState *env); -void ppc40x_chip_reset (CPUState *env); -void ppc40x_system_reset (CPUState *env); +void ppc40x_core_reset (CPUPPCState *env); +void ppc40x_chip_reset (CPUPPCState *env); +void ppc40x_system_reset (CPUPPCState *env); void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); extern CPUWriteMemoryFunc * const PPC_io_write[]; extern CPUReadMemoryFunc * const PPC_io_read[]; void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); -void ppc40x_irq_init (CPUState *env); -void ppce500_irq_init (CPUState *env); -void ppc6xx_irq_init (CPUState *env); -void ppc970_irq_init (CPUState *env); -void ppcPOWER7_irq_init (CPUState *env); +void ppc40x_irq_init (CPUPPCState *env); +void ppce500_irq_init (CPUPPCState *env); +void ppc6xx_irq_init (CPUPPCState *env); +void ppc970_irq_init (CPUPPCState *env); +void ppcPOWER7_irq_init (CPUPPCState *env); /* PPC machines for OpenBIOS */ enum { @@ -89,4 +89,4 @@ enum { #define PPC_SERIAL_MM_BAUDBASE 399193 /* ppc_booke.c */ -void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags); +void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags); diff --git a/hw/ppc405.h b/hw/ppc405.h index d8fdf0930a..1f5dc5fd36 100644 --- a/hw/ppc405.h +++ b/hw/ppc405.h @@ -56,23 +56,23 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, +ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags); -CPUState *ppc405cr_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[4], target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init); -CPUState *ppc405ep_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init); /* IBM STBxxx microcontrollers */ -CPUState *ppc_stb025_init (MemoryRegion ram_memories[2], +CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 98079fa23f..6f8342e0e7 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -41,7 +41,7 @@ #define DEBUG_CLOCKS //#define DEBUG_CLOCKS_LL -ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, +ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) { ram_addr_t bdloc; @@ -169,7 +169,7 @@ static void ppc4xx_plb_reset (void *opaque) plb->besr = 0x00000000; } -static void ppc4xx_plb_init(CPUState *env) +static void ppc4xx_plb_init(CPUPPCState *env) { ppc4xx_plb_t *plb; @@ -245,7 +245,7 @@ static void ppc4xx_pob_reset (void *opaque) pob->besr[1] = 0x0000000; } -static void ppc4xx_pob_init(CPUState *env) +static void ppc4xx_pob_init(CPUPPCState *env) { ppc4xx_pob_t *pob; @@ -574,7 +574,7 @@ static void ebc_reset (void *opaque) ebc->cfg = 0x80400000; } -static void ppc405_ebc_init(CPUState *env) +static void ppc405_ebc_init(CPUPPCState *env) { ppc4xx_ebc_t *ebc; @@ -657,7 +657,7 @@ static void ppc405_dma_reset (void *opaque) dma->pol = 0x00000000; } -static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) +static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) { ppc405_dma_t *dma; @@ -960,7 +960,7 @@ static void ocm_reset (void *opaque) ocm->dsacntl = dsacntl; } -static void ppc405_ocm_init(CPUState *env) +static void ppc405_ocm_init(CPUPPCState *env) { ppc405_ocm_t *ocm; @@ -1713,7 +1713,7 @@ static void ppc40x_mal_reset (void *opaque) mal->txeobisr = 0x00000000; } -static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) +static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) { ppc40x_mal_t *mal; int i; @@ -1764,36 +1764,24 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) /*****************************************************************************/ /* SPR */ -void ppc40x_core_reset (CPUState *env) +void ppc40x_core_reset (CPUPPCState *env) { target_ulong dbsr; printf("Reset PowerPC core\n"); - env->interrupt_request |= CPU_INTERRUPT_EXITTB; - /* XXX: TOFIX */ -#if 0 - cpu_reset(env); -#else - qemu_system_reset_request(); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); dbsr = env->spr[SPR_40x_DBSR]; dbsr &= ~0x00000300; dbsr |= 0x00000100; env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_chip_reset (CPUState *env) +void ppc40x_chip_reset (CPUPPCState *env) { target_ulong dbsr; printf("Reset PowerPC chip\n"); - env->interrupt_request |= CPU_INTERRUPT_EXITTB; - /* XXX: TOFIX */ -#if 0 - cpu_reset(env); -#else - qemu_system_reset_request(); -#endif + cpu_interrupt(env, CPU_INTERRUPT_RESET); /* XXX: TODO reset all internal peripherals */ dbsr = env->spr[SPR_40x_DBSR]; dbsr &= ~0x00000300; @@ -1801,13 +1789,13 @@ void ppc40x_chip_reset (CPUState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_system_reset (CPUState *env) +void ppc40x_system_reset (CPUPPCState *env) { printf("Reset PowerPC system\n"); qemu_system_reset_request(); } -void store_40x_dbcr0 (CPUState *env, uint32_t val) +void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) { switch ((val >> 28) & 0x3) { case 0x0: @@ -2078,7 +2066,7 @@ static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) cpc->psr |= D << 17; } -static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], +static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], uint32_t sysclk) { ppc405cr_cpc_t *cpc; @@ -2108,7 +2096,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], qemu_register_reset(ppc405cr_cpc_reset, cpc); } -CPUState *ppc405cr_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[4], target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], @@ -2117,7 +2105,7 @@ CPUState *ppc405cr_init(MemoryRegion *address_space_mem, { clk_setup_t clk_setup[PPC405CR_CLK_NB]; qemu_irq dma_irqs[4]; - CPUState *env; + CPUPPCState *env; qemu_irq *pic, *irqs; memset(clk_setup, 0, sizeof(clk_setup)); @@ -2420,7 +2408,7 @@ static void ppc405ep_cpc_reset (void *opaque) } /* XXX: sysclk should be between 25 and 100 MHz */ -static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], +static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], uint32_t sysclk) { ppc405ep_cpc_t *cpc; @@ -2457,7 +2445,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init(MemoryRegion *address_space_mem, +CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], @@ -2466,7 +2454,7 @@ CPUState *ppc405ep_init(MemoryRegion *address_space_mem, { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; - CPUState *env; + CPUPPCState *env; qemu_irq *pic, *irqs; memset(clk_setup, 0, sizeof(clk_setup)); diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index f86b16838a..220c81d06e 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -121,7 +121,7 @@ out: } /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa) { @@ -145,9 +145,9 @@ static void mmubooke_create_initial_mapping(CPUState *env, static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->gpr[1] = (16<<20) - 8; env->gpr[3] = FDT_ADDR; env->nip = entry; @@ -172,7 +172,7 @@ static void bamboo_init(ram_addr_t ram_size, qemu_irq *pic; qemu_irq *irqs; PCIBus *pcibus; - CPUState *env; + CPUPPCState *env; uint64_t elf_entry; uint64_t elf_lowaddr; target_phys_addr_t loadaddr = 0; diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h index f969e44e1b..b511020aeb 100644 --- a/hw/ppc4xx.h +++ b/hw/ppc4xx.h @@ -28,7 +28,7 @@ #include "pci.h" /* PowerPC 4xx core initialization */ -CPUState *ppc4xx_init (const char *cpu_model, +CPUPPCState *ppc4xx_init (const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk); @@ -38,7 +38,7 @@ enum { PPCUIC_OUTPUT_CINT = 1, PPCUIC_OUTPUT_NB, }; -qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, +qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, @@ -47,13 +47,13 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, target_phys_addr_t ram_sizes[], const unsigned int sdram_bank_sizes[]); -void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion ram_memories[], target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init); -PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], +PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4], target_phys_addr_t config_space, target_phys_addr_t int_ack, target_phys_addr_t special_cycle, diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 26040ac3ad..00e36f4109 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -38,13 +38,20 @@ # define LOG_UIC(...) do { } while (0) #endif +static void ppc4xx_reset(void *opaque) +{ + CPUPPCState *env = opaque; + + cpu_state_reset(env); +} + /*****************************************************************************/ /* Generic PowerPC 4xx processor instantiation */ -CPUState *ppc4xx_init (const char *cpu_model, +CPUPPCState *ppc4xx_init (const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk) { - CPUState *env; + CPUPPCState *env; /* init CPUs */ env = cpu_init(cpu_model); @@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model, tb_clk->opaque = env; ppc_dcr_init(env, NULL, NULL); /* Register qemu callbacks */ - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc4xx_reset, env); return env; } @@ -288,7 +295,7 @@ static void ppcuic_reset (void *opaque) } } -qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, +qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr) { ppcuic_t *uic; @@ -634,7 +641,7 @@ static void sdram_reset (void *opaque) sdram->cfg = 0x00800000; } -void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, +void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion *ram_memories, target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c index 88719458b0..d51e7fad67 100644 --- a/hw/ppc_booke.c +++ b/hw/ppc_booke.c @@ -71,7 +71,7 @@ struct booke_timer_t { uint32_t flags; }; -static void booke_update_irq(CPUState *env) +static void booke_update_irq(CPUPPCState *env) { ppc_set_irq(env, PPC_INTERRUPT_DECR, (env->spr[SPR_BOOKE_TSR] & TSR_DIS @@ -88,7 +88,7 @@ static void booke_update_irq(CPUState *env) /* Return the location of the bit of time base at which the FIT will raise an interrupt */ -static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env) +static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) { uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; @@ -106,7 +106,7 @@ static uint8_t booke_get_fit_target(CPUState *env, ppc_tb_t *tb_env) /* Return the location of the bit of time base at which the WDT will raise an interrupt */ -static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env) +static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) { uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; @@ -122,7 +122,7 @@ static uint8_t booke_get_wdt_target(CPUState *env, ppc_tb_t *tb_env) return wp; } -static void booke_update_fixed_timer(CPUState *env, +static void booke_update_fixed_timer(CPUPPCState *env, uint8_t target_bit, uint64_t *next, struct QEMUTimer *timer) @@ -153,7 +153,7 @@ static void booke_update_fixed_timer(CPUState *env, static void booke_decr_cb(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; env->spr[SPR_BOOKE_TSR] |= TSR_DIS; booke_update_irq(env); @@ -166,7 +166,7 @@ static void booke_decr_cb(void *opaque) static void booke_fit_cb(void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; booke_timer_t *booke_timer; @@ -185,7 +185,7 @@ static void booke_fit_cb(void *opaque) static void booke_wdt_cb(void *opaque) { - CPUState *env; + CPUPPCState *env; ppc_tb_t *tb_env; booke_timer_t *booke_timer; @@ -203,13 +203,13 @@ static void booke_wdt_cb(void *opaque) booke_timer->wdt_timer); } -void store_booke_tsr(CPUState *env, target_ulong val) +void store_booke_tsr(CPUPPCState *env, target_ulong val) { env->spr[SPR_BOOKE_TSR] &= ~val; booke_update_irq(env); } -void store_booke_tcr(CPUState *env, target_ulong val) +void store_booke_tcr(CPUPPCState *env, target_ulong val) { ppc_tb_t *tb_env = env->tb_env; booke_timer_t *booke_timer = tb_env->opaque; @@ -231,7 +231,7 @@ void store_booke_tcr(CPUState *env, target_ulong val) } -void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags) +void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags) { ppc_tb_t *tb_env; booke_timer_t *booke_timer; diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 2fec5b4d67..879651018b 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -121,6 +121,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; } +static void ppc_core99_reset(void *opaque) +{ + CPUPPCState *env = opaque; + + cpu_state_reset(env); +} + /* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init (ram_addr_t ram_size, const char *boot_device, @@ -129,7 +136,7 @@ static void ppc_core99_init (ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env = NULL; + CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; MemoryRegion *unin_memory = g_new(MemoryRegion, 1); @@ -166,7 +173,7 @@ static void ppc_core99_init (ram_addr_t ram_size, } /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc_core99_reset, env); } /* allocate RAM */ diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 49c2c9795e..7e73d37c34 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -65,6 +65,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; } +static void ppc_heathrow_reset(void *opaque) +{ + CPUPPCState *env = opaque; + + cpu_state_reset(env); +} + static void ppc_heathrow_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, @@ -73,7 +80,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *sysmem = get_system_memory(); - CPUState *env = NULL; + CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; @@ -104,7 +111,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, } /* Set time-base frequency to 16.6 Mhz */ cpu_ppc_tb_init(env, 16600000UL); - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc_heathrow_reset, env); } /* allocate RAM */ diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index dc9edd7bf5..06d589d97b 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -463,13 +463,20 @@ static const MemoryRegionOps PPC_prep_io_ops = { static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUPPCState *env = cpu_single_env; if (env && level) { cpu_exit(env); } } +static void ppc_prep_reset(void *opaque) +{ + CPUPPCState *env = opaque; + + cpu_state_reset(env); +} + /* PowerPC PREP hardware initialisation */ static void ppc_prep_init (ram_addr_t ram_size, const char *boot_device, @@ -479,7 +486,7 @@ static void ppc_prep_init (ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *sysmem = get_system_memory(); - CPUState *env = NULL; + CPUPPCState *env = NULL; char *filename; nvram_t nvram; M48t59State *m48t59; @@ -524,7 +531,7 @@ static void ppc_prep_init (ram_addr_t ram_size, /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); } - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc_prep_reset, env); } /* allocate RAM */ diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index d69f78cf33..5ee8cb34c1 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -58,7 +58,7 @@ struct boot_info uint32_t entry; }; -static int mpc8544_load_device_tree(CPUState *env, +static int mpc8544_load_device_tree(CPUPPCState *env, target_phys_addr_t addr, uint32_t ramsize, target_phys_addr_t initrd_base, @@ -178,7 +178,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) return ffs(size >> 10) - 1; } -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa) { @@ -196,9 +196,9 @@ static void mmubooke_create_initial_mapping(CPUState *env, static void mpc8544ds_cpu_reset_sec(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ @@ -208,10 +208,10 @@ static void mpc8544ds_cpu_reset_sec(void *opaque) static void mpc8544ds_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; struct boot_info *bi = env->load_info; - cpu_reset(env); + cpu_state_reset(env); /* Set initial guest state. */ env->halted = 0; @@ -231,7 +231,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); PCIBus *pci_bus; - CPUState *env = NULL; + CPUPPCState *env = NULL; uint64_t elf_entry; uint64_t elf_lowaddr; target_phys_addr_t entry=0; @@ -244,7 +244,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; qemu_irq **irqs, *mpic; DeviceState *dev; - CPUState *firstenv = NULL; + CPUPPCState *firstenv = NULL; /* Setup CPUs */ if (cpu_model == NULL) { diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c index 6b8a189c0e..268f5fdb9c 100644 --- a/hw/ppce500_spin.c +++ b/hw/ppce500_spin.c @@ -49,7 +49,7 @@ typedef struct spin_state { } SpinState; typedef struct spin_kick { - CPUState *env; + CPUPPCState *env; SpinInfo *spin; } SpinKick; @@ -73,7 +73,7 @@ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) return (ffs(size >> 10) - 1) >> 1; } -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa, target_phys_addr_t len) @@ -91,7 +91,7 @@ static void mmubooke_create_initial_mapping(CPUState *env, static void spin_kick(void *data) { SpinKick *kick = data; - CPUState *env = kick->env; + CPUPPCState *env = kick->env; SpinInfo *curspin = kick->spin; target_phys_addr_t map_size = 64 * 1024 * 1024; target_phys_addr_t map_start; @@ -121,7 +121,7 @@ static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value, { SpinState *s = opaque; int env_idx = addr / sizeof(SpinInfo); - CPUState *env; + CPUPPCState *env; SpinInfo *curspin = &s->spin[env_idx]; uint8_t *curspin_p = (uint8_t*)curspin; diff --git a/hw/pxa.h b/hw/pxa.h index e7787393c7..025be34f86 100644 --- a/hw/pxa.h +++ b/hw/pxa.h @@ -65,11 +65,11 @@ # define PXA2XX_INTERNAL_SIZE 0x40000 /* pxa2xx_pic.c */ -DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); +DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env); /* pxa2xx_gpio.c */ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, - CPUState *env, DeviceState *pic, int lines); + CPUARMState *env, DeviceState *pic, int lines); void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); /* pxa2xx_dma.c */ @@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState; typedef struct PXA2xxFIrState PXA2xxFIrState; typedef struct { - CPUState *env; + CPUARMState *env; DeviceState *pic; qemu_irq reset; MemoryRegion sdram; diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 1ab27012c1..f55287774a 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level) PXA2xxState *s = (PXA2xxState *) opaque; if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ - cpu_reset(s->env); + cpu_state_reset(s->env); /* TODO: reset peripherals */ } } diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index d5f57162ed..09a408b781 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo { qemu_irq irq0, irq1, irqX; int lines; int ncpu; - CPUState *cpu_env; + CPUARMState *cpu_env; /* XXX: GNU C vectors are more suitable */ uint32_t ilevel[PXA2XX_GPIO_BANKS]; @@ -249,7 +249,7 @@ static const MemoryRegionOps pxa_gpio_ops = { }; DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, - CPUState *env, DeviceState *pic, int lines) + CPUARMState *env, DeviceState *pic, int lines) { DeviceState *dev; diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index 6b2bdb0df1..a806b80b0f 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -34,7 +34,7 @@ typedef struct { SysBusDevice busdev; MemoryRegion iomem; - CPUState *cpu_env; + CPUARMState *cpu_env; uint32_t int_enabled[2]; uint32_t int_pending[2]; uint32_t is_fiq[2]; @@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id) return 0; } -DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env) +DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env) { DeviceState *dev = qdev_create(NULL, "pxa2xx_pic"); PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev)); diff --git a/hw/r2d.c b/hw/r2d.c index c80f9e3a29..c55de0141b 100644 --- a/hw/r2d.c +++ b/hw/r2d.c @@ -192,16 +192,16 @@ static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, } typedef struct ResetData { - CPUState *env; + CPUSH4State *env; uint32_t vector; } ResetData; static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUSH4State *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->pc = s->vector; } @@ -224,7 +224,7 @@ static void r2d_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUSH4State *env; ResetData *reset_info; struct SH7750State *s; MemoryRegion *sdram = g_new(MemoryRegion, 1); diff --git a/hw/realview.c b/hw/realview.c index 50ea67cb26..cf55204c96 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -128,7 +128,7 @@ static void realview_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model, enum realview_board_type board_type) { - CPUState *env = NULL; + CPUARMState *env = NULL; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram_lo = g_new(MemoryRegion, 1); MemoryRegion *ram_hi = g_new(MemoryRegion, 1); diff --git a/hw/s390-virtio-bus.c b/hw/s390-virtio-bus.c index c450e4bb5b..be1f5f1061 100644 --- a/hw/s390-virtio-bus.c +++ b/hw/s390-virtio-bus.c @@ -85,7 +85,7 @@ VirtIOS390Bus *s390_virtio_bus_init(ram_addr_t *ram_size) return bus; } -static void s390_virtio_irq(CPUState *env, int config_change, uint64_t token) +static void s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token) { if (kvm_enabled()) { kvm_s390_virtio_irq(env, config_change, token); @@ -116,7 +116,7 @@ static int s390_virtio_device_init(VirtIOS390Device *dev, VirtIODevice *vdev) s390_virtio_device_sync(dev); if (dev->qdev.hotplugged) { - CPUState *env = s390_cpu_addr2state(0); + CPUS390XState *env = s390_cpu_addr2state(0); s390_virtio_irq(env, VIRTIO_PARAM_DEV_ADD, dev->dev_offs); } @@ -331,7 +331,7 @@ static void virtio_s390_notify(void *opaque, uint16_t vector) { VirtIOS390Device *dev = (VirtIOS390Device*)opaque; uint64_t token = s390_virtio_device_vq_token(dev, vector); - CPUState *env = s390_cpu_addr2state(0); + CPUS390XState *env = s390_cpu_addr2state(0); s390_virtio_irq(env, 0, token); } diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c index 15e3ef389a..1ebe70d0e3 100644 --- a/hw/s390-virtio.c +++ b/hw/s390-virtio.c @@ -61,9 +61,9 @@ #define MAX_BLK_DEVS 10 static VirtIOS390Bus *s390_bus; -static CPUState **ipi_states; +static CPUS390XState **ipi_states; -CPUState *s390_cpu_addr2state(uint16_t cpu_addr) +CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr) { if (cpu_addr >= smp_cpus) { return NULL; @@ -72,7 +72,7 @@ CPUState *s390_cpu_addr2state(uint16_t cpu_addr) return ipi_states[cpu_addr]; } -int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall) +int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall) { int r = 0, i; @@ -129,7 +129,7 @@ int s390_virtio_hypercall(CPUState *env, uint64_t mem, uint64_t hypercall) */ static unsigned s390_running_cpus; -void s390_add_running_cpu(CPUState *env) +void s390_add_running_cpu(CPUS390XState *env) { if (env->halted) { s390_running_cpus++; @@ -138,7 +138,7 @@ void s390_add_running_cpu(CPUState *env) } } -unsigned s390_del_running_cpu(CPUState *env) +unsigned s390_del_running_cpu(CPUS390XState *env) { if (env->halted == 0) { assert(s390_running_cpus >= 1); @@ -157,7 +157,7 @@ static void s390_init(ram_addr_t my_ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env = NULL; + CPUS390XState *env = NULL; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); ram_addr_t kernel_size = 0; @@ -205,10 +205,10 @@ static void s390_init(ram_addr_t my_ram_size, cpu_model = "host"; } - ipi_states = g_malloc(sizeof(CPUState *) * smp_cpus); + ipi_states = g_malloc(sizeof(CPUS390XState *) * smp_cpus); for (i = 0; i < smp_cpus; i++) { - CPUState *tmp_env; + CPUS390XState *tmp_env; tmp_env = cpu_init(cpu_model); if (!env) { diff --git a/hw/sh.h b/hw/sh.h index 6488db25c4..40df18c5dc 100644 --- a/hw/sh.h +++ b/hw/sh.h @@ -11,7 +11,7 @@ struct SH7750State; struct MemoryRegion; -struct SH7750State *sh7750_init(CPUState * cpu, struct MemoryRegion *sysmem); +struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *sysmem); typedef struct { /* The callback will be triggered if any of the designated lines change */ diff --git a/hw/shix.c b/hw/shix.c index e259c17c52..dd9ce174f9 100644 --- a/hw/shix.c +++ b/hw/shix.c @@ -43,7 +43,7 @@ static void shix_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { int ret; - CPUState *env; + CPUSH4State *env; struct SH7750State *s; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *rom = g_new(MemoryRegion, 1); diff --git a/hw/spapr.c b/hw/spapr.c index dffb6a2a50..3719e0e4a7 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -110,7 +110,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num) static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr) { int ret = 0, offset; - CPUState *env; + CPUPPCState *env; char cpu_model[32]; int smt = kvmppc_smt_threads(); @@ -155,7 +155,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model, long hash_shift) { void *fdt; - CPUState *env; + CPUPPCState *env; uint64_t mem_reg_property[2]; uint32_t start_prop = cpu_to_be32(initrd_base); uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); @@ -476,7 +476,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; } -static void emulate_spapr_hypercall(CPUState *env) +static void emulate_spapr_hypercall(CPUPPCState *env) { env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); } @@ -502,6 +502,13 @@ static void spapr_reset(void *opaque) } +static void spapr_cpu_reset(void *opaque) +{ + CPUPPCState *env = opaque; + + cpu_state_reset(env); +} + /* pSeries LPAR / sPAPR hardware init */ static void ppc_spapr_init(ram_addr_t ram_size, const char *boot_device, @@ -510,7 +517,7 @@ static void ppc_spapr_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUPPCState *env; int i; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); @@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size, } /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, TIMEBASE_FREQ); - qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); + qemu_register_reset(spapr_cpu_reset, env); env->hreset_vector = 0x60; env->hreset_excp_prefix = 0; diff --git a/hw/spapr.h b/hw/spapr.h index e946a3433e..a41641fdde 100644 --- a/hw/spapr.h +++ b/hw/spapr.h @@ -278,12 +278,12 @@ extern sPAPREnvironment *spapr; do { } while (0) #endif -typedef target_ulong (*spapr_hcall_fn)(CPUState *env, sPAPREnvironment *spapr, +typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args); void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); -target_ulong spapr_hypercall(CPUState *env, target_ulong opcode, +target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode, target_ulong *args); qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num); diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c index 6ac7384013..634763eefd 100644 --- a/hw/spapr_hcall.c +++ b/hw/spapr_hcall.c @@ -92,7 +92,7 @@ static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, return rb; } -static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_enter(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -181,7 +181,7 @@ enum { REMOVE_HW = 3, }; -static target_ulong remove_hpte(CPUState *env, target_ulong ptex, +static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex, target_ulong avpn, target_ulong flags, target_ulong *vp, target_ulong *rp) @@ -219,7 +219,7 @@ static target_ulong remove_hpte(CPUState *env, target_ulong ptex, return REMOVE_SUCCESS; } -static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -265,7 +265,7 @@ static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr, #define H_BULK_REMOVE_MAX_BATCH 4 -static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { int i; @@ -311,7 +311,7 @@ static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -356,7 +356,7 @@ static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_set_dabr(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* FIXME: actually implement this */ @@ -375,7 +375,7 @@ static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr, #define VPA_SHARED_PROC_OFFSET 0x9 #define VPA_SHARED_PROC_VAL 0x2 -static target_ulong register_vpa(CPUState *env, target_ulong vpa) +static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) { uint16_t size; uint8_t tmp; @@ -410,7 +410,7 @@ static target_ulong register_vpa(CPUState *env, target_ulong vpa) return H_SUCCESS; } -static target_ulong deregister_vpa(CPUState *env, target_ulong vpa) +static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) { if (env->slb_shadow) { return H_RESOURCE; @@ -424,7 +424,7 @@ static target_ulong deregister_vpa(CPUState *env, target_ulong vpa) return H_SUCCESS; } -static target_ulong register_slb_shadow(CPUState *env, target_ulong addr) +static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) { uint32_t size; @@ -451,13 +451,13 @@ static target_ulong register_slb_shadow(CPUState *env, target_ulong addr) return H_SUCCESS; } -static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr) +static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) { env->slb_shadow = 0; return H_SUCCESS; } -static target_ulong register_dtl(CPUState *env, target_ulong addr) +static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) { uint32_t size; @@ -482,7 +482,7 @@ static target_ulong register_dtl(CPUState *env, target_ulong addr) return H_SUCCESS; } -static target_ulong deregister_dtl(CPUState *emv, target_ulong addr) +static target_ulong deregister_dtl(CPUPPCState *emv, target_ulong addr) { env->dispatch_trace_log = 0; env->dtl_size = 0; @@ -490,14 +490,14 @@ static target_ulong deregister_dtl(CPUState *emv, target_ulong addr) return H_SUCCESS; } -static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; target_ulong procno = args[1]; target_ulong vpa = args[2]; target_ulong ret = H_PARAMETER; - CPUState *tenv; + CPUPPCState *tenv; for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) { if (tenv->cpu_index == procno) { @@ -538,7 +538,7 @@ static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr, return ret; } -static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { env->msr |= (1ULL << MSR_EE); @@ -549,7 +549,7 @@ static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong rtas_r3 = args[0]; @@ -561,7 +561,7 @@ static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr, nret, rtas_r3 + 12 + 4*nargs); } -static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong size = args[0]; @@ -584,7 +584,7 @@ static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr, return H_PARAMETER; } -static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong size = args[0]; @@ -608,14 +608,14 @@ static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr, return H_PARAMETER; } -static target_ulong h_logical_icbi(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_icbi(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* Nothing to do on emulation, KVM will trap this in the kernel */ return H_SUCCESS; } -static target_ulong h_logical_dcbf(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_dcbf(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* Nothing to do on emulation, KVM will trap this in the kernel */ @@ -644,7 +644,7 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) *slot = fn; } -target_ulong spapr_hypercall(CPUState *env, target_ulong opcode, +target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode, target_ulong *args) { if (msr_pr) { diff --git a/hw/spapr_llan.c b/hw/spapr_llan.c index 77d40479c8..cfc777804b 100644 --- a/hw/spapr_llan.c +++ b/hw/spapr_llan.c @@ -254,7 +254,7 @@ static int check_bd(VIOsPAPRVLANDevice *dev, vlan_bd_t bd, return 0; } -static target_ulong h_register_logical_lan(CPUState *env, +static target_ulong h_register_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) @@ -320,7 +320,7 @@ static target_ulong h_register_logical_lan(CPUState *env, } -static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_free_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -343,7 +343,7 @@ static target_ulong h_free_logical_lan(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_add_logical_lan_buffer(CPUState *env, +static target_ulong h_add_logical_lan_buffer(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) @@ -392,7 +392,7 @@ static target_ulong h_add_logical_lan_buffer(CPUState *env, return H_SUCCESS; } -static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_send_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -461,7 +461,7 @@ static target_ulong h_send_logical_lan(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_multicast_ctrl(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_multicast_ctrl(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c index c0723b3039..09465853ba 100644 --- a/hw/spapr_rtas.c +++ b/hw/spapr_rtas.c @@ -118,7 +118,7 @@ static void rtas_query_cpu_stopped_state(sPAPREnvironment *spapr, uint32_t nret, target_ulong rets) { target_ulong id; - CPUState *env; + CPUPPCState *env; if (nargs != 1 || nret != 2) { rtas_st(rets, 0, -3); @@ -151,7 +151,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr, uint32_t nret, target_ulong rets) { target_ulong id, start, r3; - CPUState *env; + CPUPPCState *env; if (nargs != 3 || nret != 1) { rtas_st(rets, 0, -3); diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c index ea317efbe4..2fb3cee266 100644 --- a/hw/spapr_vio.c +++ b/hw/spapr_vio.c @@ -194,7 +194,7 @@ static void rtce_init(VIOsPAPRDevice *dev) } } -static target_ulong h_put_tce(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_put_tce(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong liobn = args[0]; @@ -405,7 +405,7 @@ uint64_t ldq_tce(VIOsPAPRDevice *dev, uint64_t taddr) /* * CRQ handling */ -static target_ulong h_reg_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_reg_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -453,7 +453,7 @@ static target_ulong h_reg_crq(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_free_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_free_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -474,7 +474,7 @@ static target_ulong h_free_crq(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_send_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_send_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -498,7 +498,7 @@ static target_ulong h_send_crq(CPUState *env, sPAPREnvironment *spapr, return H_HARDWARE; } -static target_ulong h_enable_crq(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_enable_crq(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -680,7 +680,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev) return pc->init(dev); } -static target_ulong h_vio_signal(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_vio_signal(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c index 3efe24211e..60e22b1600 100644 --- a/hw/spapr_vty.c +++ b/hw/spapr_vty.c @@ -72,7 +72,7 @@ static int spapr_vty_init(VIOsPAPRDevice *sdev) /* Forward declaration */ static VIOsPAPRDevice *vty_lookup(sPAPREnvironment *spapr, target_ulong reg); -static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_put_term_char(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -99,7 +99,7 @@ static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_get_term_char(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_get_term_char(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; diff --git a/hw/strongarm.h b/hw/strongarm.h index 684f61bee3..02acac3db1 100644 --- a/hw/strongarm.h +++ b/hw/strongarm.h @@ -53,7 +53,7 @@ enum { }; typedef struct { - CPUState *env; + CPUARMState *env; MemoryRegion sdram; DeviceState *pic; DeviceState *gpio; diff --git a/hw/sun4m.c b/hw/sun4m.c index 99fb219b3a..7bcbf37e98 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -228,7 +228,7 @@ void sun4m_irq_info(Monitor *mon) slavio_irq_info(mon, slavio_intctl); } -void cpu_check_irqs(CPUState *env) +void cpu_check_irqs(CPUSPARCState *env) { if (env->pil_in && (env->interrupt_index == 0 || (env->interrupt_index & ~15) == TT_EXTINT)) { @@ -253,7 +253,7 @@ void cpu_check_irqs(CPUState *env) } } -static void cpu_kick_irq(CPUState *env) +static void cpu_kick_irq(CPUSPARCState *env) { env->halted = 0; cpu_check_irqs(env); @@ -262,7 +262,7 @@ static void cpu_kick_irq(CPUState *env) static void cpu_set_irq(void *opaque, int irq, int level) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; if (level) { trace_sun4m_cpu_set_irq_raise(irq); @@ -281,17 +281,17 @@ static void dummy_cpu_set_irq(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->halted = 0; } static void secondary_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->halted = 1; } @@ -809,7 +809,7 @@ static TypeInfo ram_info = { static void cpu_devinit(const char *cpu_model, unsigned int id, uint64_t prom_addr, qemu_irq **cpu_irqs) { - CPUState *env; + CPUSPARCState *env; env = cpu_init(cpu_model); if (!env) { diff --git a/hw/sun4u.c b/hw/sun4u.c index 423108f236..c32eddb31f 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -243,7 +243,7 @@ static unsigned long sun4u_load_kernel(const char *kernel_filename, return kernel_size; } -void cpu_check_irqs(CPUState *env) +void cpu_check_irqs(CPUSPARCState *env) { uint32_t pil = env->pil_in | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); @@ -297,7 +297,7 @@ void cpu_check_irqs(CPUState *env) } } -static void cpu_kick_irq(CPUState *env) +static void cpu_kick_irq(CPUSPARCState *env) { env->halted = 0; cpu_check_irqs(env); @@ -306,7 +306,7 @@ static void cpu_kick_irq(CPUState *env) static void cpu_set_irq(void *opaque, int irq, int level) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; if (level) { CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq); @@ -320,7 +320,7 @@ static void cpu_set_irq(void *opaque, int irq, int level) } typedef struct ResetData { - CPUState *env; + CPUSPARCState *env; uint64_t prom_addr; } ResetData; @@ -344,7 +344,7 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s) qemu_get_timer(f, s->qtimer); } -static CPUTimer* cpu_timer_create(const char* name, CPUState *env, +static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env, QEMUBHFunc *cb, uint32_t frequency, uint64_t disabled_mask) { @@ -373,10 +373,10 @@ static void cpu_timer_reset(CPUTimer *timer) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUSPARCState *env = s->env; static unsigned int nr_resets; - cpu_reset(env); + cpu_state_reset(env); cpu_timer_reset(env->tick); cpu_timer_reset(env->stick); @@ -396,7 +396,7 @@ static void main_cpu_reset(void *opaque) static void tick_irq(void *opaque) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; CPUTimer* timer = env->tick; @@ -413,7 +413,7 @@ static void tick_irq(void *opaque) static void stick_irq(void *opaque) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; CPUTimer* timer = env->stick; @@ -430,7 +430,7 @@ static void stick_irq(void *opaque) static void hstick_irq(void *opaque) { - CPUState *env = opaque; + CPUSPARCState *env = opaque; CPUTimer* timer = env->hstick; @@ -714,9 +714,9 @@ static TypeInfo ram_info = { .class_init = ram_class_init, }; -static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) +static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) { - CPUState *env; + CPUSPARCState *env; ResetData *reset_info; uint32_t tick_frequency = 100*1000000; @@ -755,7 +755,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, const char *initrd_filename, const char *cpu_model, const struct hwdef *hwdef) { - CPUState *env; + CPUSPARCState *env; M48t59State *nvram; unsigned int i; long initrd_size, kernel_size; diff --git a/hw/versatilepb.c b/hw/versatilepb.c index c1687a5b89..25afb1eb31 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -167,7 +167,7 @@ static void versatile_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model, int board_id) { - CPUState *env; + CPUARMState *env; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); qemu_irq *cpu_pic; diff --git a/hw/vexpress.c b/hw/vexpress.c index b9aafec4cc..18d87ac378 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -159,7 +159,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, const char *cpu_model, qemu_irq *pic, uint32_t *proc_id) { - CPUState *env = NULL; + CPUARMState *env = NULL; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *lowram = g_new(MemoryRegion, 1); @@ -259,7 +259,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, qemu_irq *pic, uint32_t *proc_id) { int n; - CPUState *env = NULL; + CPUARMState *env = NULL; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c index f8d2b1be04..4a133b5d1e 100644 --- a/hw/virtex_ml507.c +++ b/hw/virtex_ml507.c @@ -56,7 +56,7 @@ static struct boot_info } boot_info; /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ -static void mmubooke_create_initial_mapping(CPUState *env, +static void mmubooke_create_initial_mapping(CPUPPCState *env, target_ulong va, target_phys_addr_t pa) { @@ -78,12 +78,12 @@ static void mmubooke_create_initial_mapping(CPUState *env, tlb->PID = 0; } -static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size, +static CPUPPCState *ppc440_init_xilinx(ram_addr_t *ram_size, int do_init, const char *cpu_model, uint32_t sysclk) { - CPUState *env; + CPUPPCState *env; qemu_irq *irqs; env = cpu_init(cpu_model); @@ -106,10 +106,10 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size, static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUPPCState *env = opaque; struct boot_info *bi = env->load_info; - cpu_reset(env); + cpu_state_reset(env); /* Linux Kernel Parameters (passing device tree): * r3: pointer to the fdt * r4: 0 @@ -188,7 +188,7 @@ static void virtex_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev; - CPUState *env; + CPUPPCState *env; target_phys_addr_t ram_base = 0; DriveInfo *dinfo; MemoryRegion *phys_ram = g_new(MemoryRegion, 1); diff --git a/hw/vmport.c b/hw/vmport.c index 9373be9775..a4f52ee5bb 100644 --- a/hw/vmport.c +++ b/hw/vmport.c @@ -57,7 +57,7 @@ void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque) static uint32_t vmport_ioport_read(void *opaque, uint32_t addr) { VMPortState *s = opaque; - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; unsigned char command; uint32_t eax; @@ -83,21 +83,21 @@ static uint32_t vmport_ioport_read(void *opaque, uint32_t addr) static void vmport_ioport_write(void *opaque, uint32_t addr, uint32_t val) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; env->regs[R_EAX] = vmport_ioport_read(opaque, addr); } static uint32_t vmport_cmd_get_version(void *opaque, uint32_t addr) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; env->regs[R_EBX] = VMPORT_MAGIC; return 6; } static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; env->regs[R_EBX] = 0x1177; return ram_size; } @@ -105,7 +105,7 @@ static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr) /* vmmouse helpers */ void vmmouse_get_data(uint32_t *data) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; data[0] = env->regs[R_EAX]; data[1] = env->regs[R_EBX]; data[2] = env->regs[R_ECX]; data[3] = env->regs[R_EDX]; @@ -114,7 +114,7 @@ void vmmouse_get_data(uint32_t *data) void vmmouse_set_data(const uint32_t *data) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; env->regs[R_EAX] = data[0]; env->regs[R_EBX] = data[1]; env->regs[R_ECX] = data[2]; env->regs[R_EDX] = data[3]; diff --git a/hw/xen_machine_pv.c b/hw/xen_machine_pv.c index 7985d11d5a..7eee770eea 100644 --- a/hw/xen_machine_pv.c +++ b/hw/xen_machine_pv.c @@ -36,7 +36,7 @@ static void xen_init_pv(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { - CPUState *env; + CPUX86State *env; DriveInfo *dinfo; int i; diff --git a/hw/xics.c b/hw/xics.c index 1c5eaa4135..f7963f3096 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -268,7 +268,7 @@ qemu_irq xics_find_qirq(struct icp_state *icp, int irq) return icp->ics->qirqs[irq - icp->ics->offset]; } -static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong cppr = args[0]; @@ -277,7 +277,7 @@ static target_ulong h_cppr(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong server = args[0]; @@ -292,7 +292,7 @@ static target_ulong h_ipi(CPUState *env, sPAPREnvironment *spapr, } -static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index); @@ -301,7 +301,7 @@ static target_ulong h_xirr(CPUState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_eoi(CPUState *env, sPAPREnvironment *spapr, +static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong xirr = args[0]; @@ -424,7 +424,7 @@ static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token, struct icp_state *xics_system_init(int nr_irqs) { - CPUState *env; + CPUPPCState *env; int max_server_num; int i; struct icp_state *icp; diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index ea13e8c844..7290c64a4c 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -50,7 +50,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env = NULL; + CPUARMState *env = NULL; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c index 26112c3eb0..afdef494b2 100644 --- a/hw/xtensa_lx60.c +++ b/hw/xtensa_lx60.c @@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) return cpu_get_phys_page_debug(env, addr); } -static void lx60_reset(void *env) +static void lx60_reset(void *opaque) { - cpu_reset(env); + CPUXtensaState *env = opaque; + + cpu_state_reset(env); } static void lx_init(const LxBoardDesc *board, @@ -162,7 +164,7 @@ static void lx_init(const LxBoardDesc *board, int be = 0; #endif MemoryRegion *system_memory = get_system_memory(); - CPUState *env = NULL; + CPUXtensaState *env = NULL; MemoryRegion *ram, *rom, *system_io; DriveInfo *dinfo; pflash_t *flash = NULL; @@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board, /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ - cpu_reset(env); + cpu_state_reset(env); } ram = g_malloc(sizeof(*ram)); diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c index 71d5fc89d4..653ded6820 100644 --- a/hw/xtensa_pic.c +++ b/hw/xtensa_pic.c @@ -29,7 +29,7 @@ #include "qemu-log.h" #include "qemu-timer.h" -void xtensa_advance_ccount(CPUState *env, uint32_t d) +void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d) { uint32_t old_ccount = env->sregs[CCOUNT]; @@ -45,7 +45,7 @@ void xtensa_advance_ccount(CPUState *env, uint32_t d) } } -void check_interrupts(CPUState *env) +void check_interrupts(CPUXtensaState *env) { int minlevel = xtensa_get_cintlevel(env); uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE]; @@ -84,7 +84,7 @@ void check_interrupts(CPUState *env) static void xtensa_set_irq(void *opaque, int irq, int active) { - CPUState *env = opaque; + CPUXtensaState *env = opaque; if (irq >= env->config->ninterrupt) { qemu_log("%s: bad IRQ %d\n", __func__, irq); @@ -101,12 +101,12 @@ static void xtensa_set_irq(void *opaque, int irq, int active) } } -void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active) +void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active) { qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active); } -void xtensa_rearm_ccompare_timer(CPUState *env) +void xtensa_rearm_ccompare_timer(CPUXtensaState *env) { int i; uint32_t wake_ccount = env->sregs[CCOUNT] - 1; @@ -125,7 +125,7 @@ void xtensa_rearm_ccompare_timer(CPUState *env) static void xtensa_ccompare_cb(void *opaque) { - CPUState *env = opaque; + CPUXtensaState *env = opaque; if (env->halted) { env->halt_clock = qemu_get_clock_ns(vm_clock); @@ -137,7 +137,7 @@ static void xtensa_ccompare_cb(void *opaque) } } -void xtensa_irq_init(CPUState *env) +void xtensa_irq_init(CPUXtensaState *env) { env->irq_inputs = (void **)qemu_allocate_irqs( xtensa_set_irq, env, env->config->ninterrupt); @@ -148,7 +148,7 @@ void xtensa_irq_init(CPUState *env) } } -void *xtensa_get_extint(CPUState *env, unsigned extint) +void *xtensa_get_extint(CPUXtensaState *env, unsigned extint) { if (extint < env->config->nextint) { unsigned irq = env->config->extint[extint]; diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c index 104e5dc619..c7e05dcf4e 100644 --- a/hw/xtensa_sim.c +++ b/hw/xtensa_sim.c @@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) static void sim_reset(void *env) { - cpu_reset(env); + cpu_state_reset(env); } static void sim_init(ram_addr_t ram_size, @@ -47,7 +47,7 @@ static void sim_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { - CPUState *env = NULL; + CPUXtensaState *env = NULL; MemoryRegion *ram, *rom; int n; |