diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/block/fdc-isa.c | 11 | ||||
| -rw-r--r-- | hw/ppc/ppc.c | 21 | ||||
| -rw-r--r-- | hw/ppc/prep.c | 9 |
3 files changed, 9 insertions, 32 deletions
diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c index 3bf64e0665..ab663dce93 100644 --- a/hw/block/fdc-isa.c +++ b/hw/block/fdc-isa.c @@ -216,6 +216,7 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0) static void fdc_isa_build_aml(ISADevice *isadev, Aml *scope) { + FDCtrlISABus *isa = ISA_FDC(isadev); Aml *dev; Aml *crs; int i; @@ -227,11 +228,13 @@ static void fdc_isa_build_aml(ISADevice *isadev, Aml *scope) }; crs = aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); - aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); - aml_append(crs, aml_irq_no_flags(6)); aml_append(crs, - aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); + aml_io(AML_DECODE16, isa->iobase + 2, isa->iobase + 2, 0x00, 0x04)); + aml_append(crs, + aml_io(AML_DECODE16, isa->iobase + 7, isa->iobase + 7, 0x00, 0x01)); + aml_append(crs, aml_irq_no_flags(isa->irq)); + aml_append(crs, + aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, isa->dma)); dev = aml_device("FDC0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 462c87dba8..ba7fa0f3b5 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1083,27 +1083,6 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) return &cpu_ppc_set_tb_clk; } -/* Specific helpers for POWER & PowerPC 601 RTC */ -void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) -{ - _cpu_ppc_store_tbu(env, value); -} - -uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) -{ - return _cpu_ppc_load_tbu(env); -} - -void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) -{ - cpu_ppc_store_tbl(env, value & 0x3FFFFF80); -} - -uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) -{ - return cpu_ppc_load_tbl(env) & 0x3FFFFF80; -} - /*****************************************************************************/ /* PowerPC 40x timers */ diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 25a2e86b42..bf622aa38f 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -255,13 +255,8 @@ static void ibm_40p_init(MachineState *machine) exit(1); } - if (env->flags & POWERPC_FLAG_RTC_CLK) { - /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ - cpu_ppc_tb_init(env, 7812500UL); - } else { - /* Set time-base frequency to 100 Mhz */ - cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); - } + /* Set time-base frequency to 100 Mhz */ + cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); qemu_register_reset(ppc_prep_reset, cpu); /* PCI host */ |