diff options
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/alpha/typhoon.c | 202 | ||||
| -rw-r--r-- | hw/block/dataplane/virtio-blk.c | 25 | ||||
| -rw-r--r-- | hw/core/qdev.c | 11 |
3 files changed, 190 insertions, 48 deletions
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index b7fb04406c..245004530c 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -26,9 +26,9 @@ typedef struct TyphoonCchip { } TyphoonCchip; typedef struct TyphoonWindow { - uint32_t base_addr; - uint32_t mask; - uint32_t translated_base_pfn; + uint64_t wba; + uint64_t wsm; + uint64_t tba; } TyphoonWindow; typedef struct TyphoonPchip { @@ -37,6 +37,10 @@ typedef struct TyphoonPchip { MemoryRegion reg_mem; MemoryRegion reg_io; MemoryRegion reg_conf; + + AddressSpace iommu_as; + MemoryRegion iommu; + uint64_t ctl; TyphoonWindow win[4]; } TyphoonPchip; @@ -209,53 +213,53 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) switch (addr) { case 0x0000: /* WSBA0: Window Space Base Address Register. */ - ret = s->pchip.win[0].base_addr; + ret = s->pchip.win[0].wba; break; case 0x0040: /* WSBA1 */ - ret = s->pchip.win[1].base_addr; + ret = s->pchip.win[1].wba; break; case 0x0080: /* WSBA2 */ - ret = s->pchip.win[2].base_addr; + ret = s->pchip.win[2].wba; break; case 0x00c0: /* WSBA3 */ - ret = s->pchip.win[3].base_addr; + ret = s->pchip.win[3].wba; break; case 0x0100: /* WSM0: Window Space Mask Register. */ - ret = s->pchip.win[0].mask; + ret = s->pchip.win[0].wsm; break; case 0x0140: /* WSM1 */ - ret = s->pchip.win[1].mask; + ret = s->pchip.win[1].wsm; break; case 0x0180: /* WSM2 */ - ret = s->pchip.win[2].mask; + ret = s->pchip.win[2].wsm; break; case 0x01c0: /* WSM3 */ - ret = s->pchip.win[3].mask; + ret = s->pchip.win[3].wsm; break; case 0x0200: /* TBA0: Translated Base Address Register. */ - ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10; + ret = s->pchip.win[0].tba; break; case 0x0240: /* TBA1 */ - ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10; + ret = s->pchip.win[1].tba; break; case 0x0280: /* TBA2 */ - ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10; + ret = s->pchip.win[2].tba; break; case 0x02c0: /* TBA3 */ - ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10; + ret = s->pchip.win[3].tba; break; case 0x0300: @@ -458,53 +462,53 @@ static void pchip_write(void *opaque, hwaddr addr, switch (addr) { case 0x0000: /* WSBA0: Window Space Base Address Register. */ - s->pchip.win[0].base_addr = val; + s->pchip.win[0].wba = val & 0xfff00003u; break; case 0x0040: /* WSBA1 */ - s->pchip.win[1].base_addr = val; + s->pchip.win[1].wba = val & 0xfff00003u; break; case 0x0080: /* WSBA2 */ - s->pchip.win[2].base_addr = val; + s->pchip.win[2].wba = val & 0xfff00003u; break; case 0x00c0: /* WSBA3 */ - s->pchip.win[3].base_addr = val; + s->pchip.win[3].wba = (val & 0x80fff00001ull) | 2; break; case 0x0100: /* WSM0: Window Space Mask Register. */ - s->pchip.win[0].mask = val; + s->pchip.win[0].wsm = val & 0xfff00000u; break; case 0x0140: /* WSM1 */ - s->pchip.win[1].mask = val; + s->pchip.win[1].wsm = val & 0xfff00000u; break; case 0x0180: /* WSM2 */ - s->pchip.win[2].mask = val; + s->pchip.win[2].wsm = val & 0xfff00000u; break; case 0x01c0: /* WSM3 */ - s->pchip.win[3].mask = val; + s->pchip.win[3].wsm = val & 0xfff00000u; break; case 0x0200: /* TBA0: Translated Base Address Register. */ - s->pchip.win[0].translated_base_pfn = val >> 10; + s->pchip.win[0].tba = val & 0x7fffffc00ull; break; case 0x0240: /* TBA1 */ - s->pchip.win[1].translated_base_pfn = val >> 10; + s->pchip.win[1].tba = val & 0x7fffffc00ull; break; case 0x0280: /* TBA2 */ - s->pchip.win[2].translated_base_pfn = val >> 10; + s->pchip.win[2].tba = val & 0x7fffffc00ull; break; case 0x02c0: /* TBA3 */ - s->pchip.win[3].translated_base_pfn = val >> 10; + s->pchip.win[3].tba = val & 0x7fffffc00ull; break; case 0x0300: @@ -512,7 +516,6 @@ static void pchip_write(void *opaque, hwaddr addr, oldval = s->pchip.ctl; oldval &= ~0x00001cff0fc7ffull; /* RW fields */ oldval |= val & 0x00001cff0fc7ffull; - s->pchip.ctl = oldval; break; @@ -593,6 +596,140 @@ static const MemoryRegionOps pchip_ops = { }, }; +/* A subroutine of typhoon_translate_iommu that builds an IOMMUTLBEntry + using the given translated address and mask. */ +static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask, IOMMUTLBEntry *ret) +{ + *ret = (IOMMUTLBEntry) { + .target_as = &address_space_memory, + .translated_addr = taddr, + .addr_mask = mask, + .perm = IOMMU_RW, + }; + return true; +} + +/* A subroutine of typhoon_translate_iommu that handles scatter-gather + translation, given the address of the PTE. */ +static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret) +{ + uint64_t pte = ldq_phys(pte_addr); + + /* Check valid bit. */ + if ((pte & 1) == 0) { + return false; + } + + return make_iommu_tlbe((pte & 0x3ffffe) << 12, 0x1fff, ret); +} + +/* A subroutine of typhoon_translate_iommu that handles one of the + four single-address-cycle translation windows. */ +static bool window_translate(TyphoonWindow *win, hwaddr addr, + IOMMUTLBEntry *ret) +{ + uint32_t wba = win->wba; + uint64_t wsm = win->wsm; + uint64_t tba = win->tba; + uint64_t wsm_ext = wsm | 0xfffff; + + /* Check for window disabled. */ + if ((wba & 1) == 0) { + return false; + } + + /* Check for window hit. */ + if ((addr & ~wsm_ext) != (wba & 0xfff00000u)) { + return false; + } + + if (wba & 2) { + /* Scatter-gather translation. */ + hwaddr pte_addr; + + /* See table 10-6, Generating PTE address for PCI DMA Address. */ + pte_addr = tba & ~(wsm >> 10); + pte_addr |= (addr & (wsm | 0xfe000)) >> 10; + return pte_translate(pte_addr, ret); + } else { + /* Direct-mapped translation. */ + return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret); + } +} + +/* Handle PCI-to-system address translation. */ +/* TODO: A translation failure here ought to set PCI error codes on the + Pchip and generate a machine check interrupt. */ +static IOMMUTLBEntry typhoon_translate_iommu(MemoryRegion *iommu, hwaddr addr) +{ + TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu); + IOMMUTLBEntry ret; + int i; + + if (addr <= 0xffffffffu) { + /* Single-address cycle. */ + + /* Check for the Window Hole, inhibiting matching. */ + if ((pchip->ctl & 0x20) + && addr >= 0x80000 + && addr <= 0xfffff) { + goto failure; + } + + /* Check the first three windows. */ + for (i = 0; i < 3; ++i) { + if (window_translate(&pchip->win[i], addr, &ret)) { + goto success; + } + } + + /* Check the fourth window for DAC disable. */ + if ((pchip->win[3].wba & 0x80000000000ull) == 0 + && window_translate(&pchip->win[3], addr, &ret)) { + goto success; + } + } else { + /* Double-address cycle. */ + + if (addr >= 0x10000000000ull && addr < 0x20000000000ull) { + /* Check for the DMA monster window. */ + if (pchip->ctl & 0x40) { + /* See 10.1.4.4; in particular <39:35> is ignored. */ + make_iommu_tlbe(0, 0x007ffffffffull, &ret); + goto success; + } + } + + if (addr >= 0x80000000000 && addr <= 0xfffffffffff) { + /* Check the fourth window for DAC enable and window enable. */ + if ((pchip->win[3].wba & 0x80000000001ull) == 0x80000000001ull) { + uint64_t pte_addr; + + pte_addr = pchip->win[3].tba & 0x7ffc00000ull; + pte_addr |= (addr & 0xffffe000u) >> 10; + if (pte_translate(pte_addr, &ret)) { + goto success; + } + } + } + } + + failure: + ret = (IOMMUTLBEntry) { .perm = IOMMU_NONE }; + success: + return ret; +} + +static const MemoryRegionIOMMUOps typhoon_iommu_ops = { + .translate = typhoon_translate_iommu, +}; + +static AddressSpace *typhoon_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) +{ + TyphoonState *s = opaque; + return &s->pchip.iommu_as; +} + static void typhoon_set_irq(void *opaque, int irq, int level) { TyphoonState *s = opaque; @@ -688,6 +825,9 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, s = TYPHOON_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); + s->cchip.misc = 0x800000000ull; /* Revision: Typhoon. */ + s->pchip.win[3].wba = 2; /* Window 3 SG always enabled. */ + /* Remember the CPUs so that we can deliver interrupts to them. */ for (i = 0; i < 4; i++) { AlphaCPU *cpu = cpus[i]; @@ -746,6 +886,12 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 0, 64, TYPE_PCI_BUS); phb->bus = b; + /* Host memory as seen from the PCI side, via the IOMMU. */ + memory_region_init_iommu(&s->pchip.iommu, OBJECT(s), &typhoon_iommu_ops, + "iommu-typhoon", UINT64_MAX); + address_space_init(&s->pchip.iommu_as, &s->pchip.iommu, "pchip0-pci"); + pci_setup_iommu(b, typhoon_pci_dma_iommu, s); + /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */ memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops, b, "pci0-iack", 64*MB); diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index 411becc06e..5a96ccd416 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -261,11 +261,6 @@ static int process_request(IOQueue *ioq, struct iovec iov[], } } -static int flush_true(EventNotifier *e) -{ - return true; -} - static void handle_notify(EventNotifier *e) { VirtIOBlockDataPlane *s = container_of(e, VirtIOBlockDataPlane, @@ -345,14 +340,6 @@ static void handle_notify(EventNotifier *e) } } -static int flush_io(EventNotifier *e) -{ - VirtIOBlockDataPlane *s = container_of(e, VirtIOBlockDataPlane, - io_notifier); - - return s->num_reqs > 0; -} - static void handle_io(EventNotifier *e) { VirtIOBlockDataPlane *s = container_of(e, VirtIOBlockDataPlane, @@ -376,9 +363,9 @@ static void *data_plane_thread(void *opaque) { VirtIOBlockDataPlane *s = opaque; - do { + while (!s->stopping || s->num_reqs > 0) { aio_poll(s->ctx, true); - } while (!s->stopping || s->num_reqs > 0); + } return NULL; } @@ -485,7 +472,7 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) exit(1); } s->host_notifier = *virtio_queue_get_host_notifier(vq); - aio_set_event_notifier(s->ctx, &s->host_notifier, handle_notify, flush_true); + aio_set_event_notifier(s->ctx, &s->host_notifier, handle_notify); /* Set up ioqueue */ ioq_init(&s->ioqueue, s->fd, REQ_MAX); @@ -493,7 +480,7 @@ void virtio_blk_data_plane_start(VirtIOBlockDataPlane *s) ioq_put_iocb(&s->ioqueue, &s->requests[i].iocb); } s->io_notifier = *ioq_get_notifier(&s->ioqueue); - aio_set_event_notifier(s->ctx, &s->io_notifier, handle_io, flush_io); + aio_set_event_notifier(s->ctx, &s->io_notifier, handle_io); s->started = true; trace_virtio_blk_data_plane_start(s); @@ -525,10 +512,10 @@ void virtio_blk_data_plane_stop(VirtIOBlockDataPlane *s) qemu_thread_join(&s->thread); } - aio_set_event_notifier(s->ctx, &s->io_notifier, NULL, NULL); + aio_set_event_notifier(s->ctx, &s->io_notifier, NULL); ioq_cleanup(&s->ioqueue); - aio_set_event_notifier(s->ctx, &s->host_notifier, NULL, NULL); + aio_set_event_notifier(s->ctx, &s->host_notifier, NULL); k->set_host_notifier(qbus->parent, 0, false); aio_context_unref(s->ctx); diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 9190a7ee76..758de9fccc 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -752,7 +752,6 @@ static void device_initfn(Object *obj) } class = object_class_get_parent(class); } while (class != object_class_by_name(TYPE_DEVICE)); - qdev_prop_set_globals(dev, &err); if (err != NULL) { qerror_report_err(err); error_free(err); @@ -764,6 +763,15 @@ static void device_initfn(Object *obj) assert_no_error(err); } +static void device_post_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + Error *err = NULL; + + qdev_prop_set_globals(dev, &err); + assert_no_error(err); +} + /* Unlink device from bus and free the structure. */ static void device_finalize(Object *obj) { @@ -853,6 +861,7 @@ static const TypeInfo device_type_info = { .parent = TYPE_OBJECT, .instance_size = sizeof(DeviceState), .instance_init = device_initfn, + .instance_post_init = device_post_init, .instance_finalize = device_finalize, .class_base_init = device_class_base_init, .class_init = device_class_init, |