diff options
Diffstat (limited to 'include/hw/misc/npcm_clk.h')
| -rw-r--r-- | include/hw/misc/npcm_clk.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index f47614ac8d..8fa1e14bdd 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -1,5 +1,5 @@ /* - * Nuvoton NPCM7xx Clock Control Registers. + * Nuvoton NPCM7xx/8xx Clock Control Registers. * * Copyright 2020 Google LLC * @@ -21,11 +21,12 @@ #include "hw/sysbus.h" #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) +#define NPCM8XX_CLK_NR_REGS (0xc4 / sizeof(uint32_t)) /* * Number of maximum registers in NPCM device state structure. Don't change * this without incrementing the version_id in the vmstate. */ -#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS +#define NPCM_CLK_MAX_NR_REGS NPCM8XX_CLK_NR_REGS #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" @@ -162,6 +163,10 @@ struct NPCMCLKState { MemoryRegion iomem; /* Clock converters */ + /* + * TODO: Implement unique clock converters for NPCM8xx. + * NPCM8xx adds a few more clock outputs. + */ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS]; NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; @@ -185,5 +190,6 @@ typedef struct NPCMCLKClass { #define TYPE_NPCM_CLK "npcm-clk" OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK) #define TYPE_NPCM7XX_CLK "npcm7xx-clk" +#define TYPE_NPCM8XX_CLK "npcm8xx-clk" #endif /* NPCM_CLK_H */ |