diff options
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/acpi/piix4.h | 6 | ||||
| -rw-r--r-- | include/hw/arm/boot.h | 7 | ||||
| -rw-r--r-- | include/hw/core/cpu.h | 24 | ||||
| -rw-r--r-- | include/hw/i386/pc.h | 37 | ||||
| -rw-r--r-- | include/hw/irq.h | 5 | ||||
| -rw-r--r-- | include/hw/isa/isa.h | 2 | ||||
| -rw-r--r-- | include/hw/pci-host/i440fx.h | 36 | ||||
| -rw-r--r-- | include/hw/ptimer.h | 45 | ||||
| -rw-r--r-- | include/hw/southbridge/piix.h | 74 | ||||
| -rw-r--r-- | include/hw/virtio/virtio.h | 1 | ||||
| -rw-r--r-- | include/hw/xen/interface/io/blkif.h | 2 |
11 files changed, 140 insertions, 99 deletions
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h deleted file mode 100644 index 028bb53e3d..0000000000 --- a/include/hw/acpi/piix4.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef HW_ACPI_PIIX4_H -#define HW_ACPI_PIIX4_H - -#define TYPE_PIIX4_PM "PIIX4_PM" - -#endif diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index 7f4d0ca7cd..ce2b48b88b 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -107,9 +107,12 @@ struct arm_boot_info { void (*write_board_setup)(ARMCPU *cpu, const struct arm_boot_info *info); - /* If set, the board specific loader/setup blob will be run from secure + /* + * If set, the board specific loader/setup blob will be run from secure * mode, regardless of secure_boot. The blob becomes responsible for - * changing to non-secure state if implementing a non-secure boot + * changing to non-secure state if implementing a non-secure boot, + * including setting up EL3/Secure registers such as the NSACR as + * required by the Linux booting ABI before the switch to non-secure. */ bool secure_board_setup; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e1c383ba84..77c6f05299 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -72,10 +72,6 @@ typedef enum MMUAccessType { typedef struct CPUWatchpoint CPUWatchpoint; -typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int opaque, - unsigned size); - struct TranslationBlock; /** @@ -87,8 +83,6 @@ struct TranslationBlock; * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. * @do_interrupt: Callback for interrupt handling. - * @do_unassigned_access: Callback for unassigned access handling. - * (this is deprecated: new targets should use do_transaction_failed instead) * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions @@ -175,7 +169,6 @@ typedef struct CPUClass { int reset_dump_flags; bool (*has_work)(CPUState *cpu); void (*do_interrupt)(CPUState *cpu); - CPUUnassignedAccess do_unassigned_access; void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -415,12 +408,6 @@ struct CPUState { * we store some rarely used information in the CPU context. */ uintptr_t mem_io_pc; - /* - * This is only needed for the legacy cpu_unassigned_access() hook; - * when all targets using it have been converted to use - * cpu_transaction_failed() instead it can be removed. - */ - MMUAccessType mem_io_access_type; int kvm_fd; struct KVMState *kvm_state; @@ -896,17 +883,6 @@ void cpu_interrupt(CPUState *cpu, int mask); #ifdef NEED_CPU_H #ifdef CONFIG_SOFTMMU -static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int opaque, unsigned size) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - - if (cc->do_unassigned_access) { - cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); - } -} - static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f040a72095..e6fa8418ca 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -228,46 +228,9 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0); #define PORT92_A20_LINE "a20" -/* acpi_piix.c */ - -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - int smm_enabled, DeviceState **piix4_pm); - /* hpet.c */ extern int no_hpet; -/* piix_pci.c */ -struct PCII440FXState; -typedef struct PCII440FXState PCII440FXState; - -#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" -#define TYPE_I440FX_PCI_DEVICE "i440FX" - -#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" - -/* - * Reset Control Register: PCI-accessible ISA-Compatible Register at address - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). - */ -#define RCR_IOPORT 0xcf9 - -PCIBus *i440fx_init(const char *host_type, const char *pci_type, - PCII440FXState **pi440fx_state, int *piix_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - ram_addr_t below_4g_mem_size, - ram_addr_t above_4g_mem_size, - MemoryRegion *pci_memory, - MemoryRegion *ram_memory); - -PCIBus *find_i440fx(void); -/* piix4.c */ -extern PCIDevice *piix4_dev; -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); - /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); diff --git a/include/hw/irq.h b/include/hw/irq.h index fe527f6f51..24ba0ece11 100644 --- a/include/hw/irq.h +++ b/include/hw/irq.h @@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq); */ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); -/* Returns a new IRQ set which connects 1:1 to another IRQ set, which - * may be set later. - */ -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n); - /* For internal use in qtest. Similar to qemu_irq_split, but operating on an existing vector of qemu_irq. */ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index 018ada4f6f..79f703fd6c 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d) return ISA_BUS(qdev_get_parent_bus(DEVICE(d))); } +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa" + #endif diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h new file mode 100644 index 0000000000..f54e6466e4 --- /dev/null +++ b/include/hw/pci-host/i440fx.h @@ -0,0 +1,36 @@ +/* + * QEMU i440FX North Bridge Emulation + * + * Copyright (c) 2006 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_PCI_I440FX_H +#define HW_PCI_I440FX_H + +#include "hw/hw.h" +#include "hw/pci/pci_bus.h" + +typedef struct PCII440FXState PCII440FXState; + +#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" +#define TYPE_I440FX_PCI_DEVICE "i440FX" + +#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" + +PCIBus *i440fx_init(const char *host_type, const char *pci_type, + PCII440FXState **pi440fx_state, + MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + ram_addr_t ram_size, + ram_addr_t below_4g_mem_size, + ram_addr_t above_4g_mem_size, + MemoryRegion *pci_memory, + MemoryRegion *ram_memory); + +PCIBus *find_i440fx(void); + +#endif diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h index 4c321f65dc..412763fffb 100644 --- a/include/hw/ptimer.h +++ b/include/hw/ptimer.h @@ -10,15 +10,24 @@ #include "qemu/timer.h" -/* The ptimer API implements a simple periodic countdown timer. +/* + * The ptimer API implements a simple periodic countdown timer. * The countdown timer has a value (which can be read and written via * ptimer_get_count() and ptimer_set_count()). When it is enabled * using ptimer_run(), the value will count downwards at the frequency * which has been configured using ptimer_set_period() or ptimer_set_freq(). - * When it reaches zero it will trigger a QEMU bottom half handler, and + * When it reaches zero it will trigger a callback function, and * can be set to either reload itself from a specified limit value * and keep counting down, or to stop (as a one-shot timer). * + * A transaction-based API is used for modifying ptimer state: all calls + * to functions which modify ptimer state must be between matched calls to + * ptimer_transaction_begin() and ptimer_transaction_commit(). + * When ptimer_transaction_commit() is called it will evaluate the state + * of the timer after all the changes in the transaction, and call the + * callback if necessary. (See the ptimer_init() documentation for the full + * list of state-modifying functions and detailed semantics of the callback.) + * * Forgetting to set the period/frequency (or setting it to zero) is a * bug in the QEMU device and will cause warning messages to be printed * to stderr when the guest attempts to enable the timer. @@ -72,7 +81,7 @@ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer * (though it will cause a reload). Only a counter decrement to "0" * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER; - * ptimer_init_with_bh() will assert() that you don't set both. + * ptimer_init() will assert() that you don't set both. */ #define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5) @@ -81,17 +90,6 @@ typedef struct ptimer_state ptimer_state; typedef void (*ptimer_cb)(void *opaque); /** - * ptimer_init_with_bh - Allocate and return a new ptimer - * @bh: QEMU bottom half which is run on timer expiry - * @policy: PTIMER_POLICY_* bits specifying behaviour - * - * The ptimer returned must be freed using ptimer_free(). - * The ptimer takes ownership of @bh and will delete it - * when the ptimer is eventually freed. - */ -ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask); - -/** * ptimer_init - Allocate and return a new ptimer * @callback: function to call on ptimer expiry * @callback_opaque: opaque pointer passed to @callback @@ -127,8 +125,7 @@ ptimer_state *ptimer_init(ptimer_cb callback, * ptimer_free - Free a ptimer * @s: timer to free * - * Free a ptimer created using ptimer_init_with_bh() (including - * deleting the bottom half which it is using). + * Free a ptimer created using ptimer_init(). */ void ptimer_free(ptimer_state *s); @@ -164,7 +161,7 @@ void ptimer_transaction_commit(ptimer_state *s); * may be more appropriate. * * This function will assert if it is called outside a - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. + * ptimer_transaction_begin/commit block. */ void ptimer_set_period(ptimer_state *s, int64_t period); @@ -180,7 +177,7 @@ void ptimer_set_period(ptimer_state *s, int64_t period); * precise to fractions of a nanosecond, avoiding rounding errors. * * This function will assert if it is called outside a - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. + * ptimer_transaction_begin/commit block. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq); @@ -210,7 +207,7 @@ uint64_t ptimer_get_limit(ptimer_state *s); * reload the counter when their reload register is written to. * * This function will assert if it is called outside a - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. + * ptimer_transaction_begin/commit block. */ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); @@ -234,7 +231,7 @@ uint64_t ptimer_get_count(ptimer_state *s); * point in the future. * * This function will assert if it is called outside a - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. + * ptimer_transaction_begin/commit block. */ void ptimer_set_count(ptimer_state *s, uint64_t count); @@ -243,15 +240,15 @@ void ptimer_set_count(ptimer_state *s, uint64_t count); * @s: ptimer * @oneshot: non-zero if this timer should only count down once * - * Start a ptimer counting down; when it reaches zero the bottom half - * passed to ptimer_init_with_bh() will be invoked. + * Start a ptimer counting down; when it reaches zero the callback function + * passed to ptimer_init() will be invoked. * If the @oneshot argument is zero, * the counter value will then be reloaded from the limit and it will * start counting down again. If @oneshot is non-zero, then the counter * will disable itself when it reaches zero. * * This function will assert if it is called outside a - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. + * ptimer_transaction_begin/commit block. */ void ptimer_run(ptimer_state *s, int oneshot); @@ -266,7 +263,7 @@ void ptimer_run(ptimer_state *s, int oneshot); * restarted. * * This function will assert if it is called outside a - * ptimer_transaction_begin/commit block, unless this is a bottom-half ptimer. + * ptimer_transaction_begin/commit block. */ void ptimer_stop(ptimer_state *s); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h new file mode 100644 index 0000000000..152628c6d9 --- /dev/null +++ b/include/hw/southbridge/piix.h @@ -0,0 +1,74 @@ +/* + * QEMU PIIX South Bridge Emulation + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_SOUTHBRIDGE_PIIX_H +#define HW_SOUTHBRIDGE_PIIX_H + +#include "hw/pci/pci.h" + +#define TYPE_PIIX4_PM "PIIX4_PM" + +I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + int smm_enabled, DeviceState **piix4_pm); + +/* PIRQRC[A:D]: PIRQx Route Control Registers */ +#define PIIX_PIRQCA 0x60 +#define PIIX_PIRQCB 0x61 +#define PIIX_PIRQCC 0x62 +#define PIIX_PIRQCD 0x63 + +/* + * Reset Control Register: PCI-accessible ISA-Compatible Register at address + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). + */ +#define PIIX_RCR_IOPORT 0xcf9 + +#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ +#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ + +typedef struct PIIXState { + PCIDevice dev; + + /* + * bitmap to track pic levels. + * The pic level is the logical OR of all the PCI irqs mapped to it + * So one PIC level is tracked by PIIX_NUM_PIRQS bits. + * + * PIRQ is mapped to PIC pins, we track it by + * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with + * pic_irq * PIIX_NUM_PIRQS + pirq + */ +#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#error "unable to encode pic state in 64bit in pic_levels." +#endif + uint64_t pic_levels; + + qemu_irq *pic; + + /* This member isn't used. Just for save/load compatibility */ + int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + + /* Reset Control Register contents */ + uint8_t rcr; + + /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ + MemoryRegion rcr_mem; +} PIIX3State; + +extern PCIDevice *piix4_dev; + +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); + +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, + I2CBus **smbus, size_t ide_buses); + +#endif diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index 3448d67d2a..c32a815303 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -312,6 +312,7 @@ int virtio_device_grab_ioeventfd(VirtIODevice *vdev); void virtio_device_release_ioeventfd(VirtIODevice *vdev); bool virtio_device_ioeventfd_enabled(VirtIODevice *vdev); EventNotifier *virtio_queue_get_host_notifier(VirtQueue *vq); +void virtio_queue_set_host_notifier_enabled(VirtQueue *vq, bool enabled); void virtio_queue_host_notifier_read(EventNotifier *n); void virtio_queue_aio_set_host_notifier_handler(VirtQueue *vq, AioContext *ctx, VirtIOHandleAIOOutput handle_output); diff --git a/include/hw/xen/interface/io/blkif.h b/include/hw/xen/interface/io/blkif.h index 8b1be50ce8..d07fa1e078 100644 --- a/include/hw/xen/interface/io/blkif.h +++ b/include/hw/xen/interface/io/blkif.h @@ -341,7 +341,7 @@ * access (even when it should be read-only). If the frontend hits the * maximum number of allowed persistently mapped grants, it can fallback * to non persistent mode. This will cause a performance degradation, - * since the the backend driver will still try to map those grants + * since the backend driver will still try to map those grants * persistently. Since the persistent grants protocol is compatible with * the previous protocol, a frontend driver can choose to work in * persistent mode even when the backend doesn't support it. |