diff options
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/xlnx-zynqmp.h | 2 | ||||
| -rw-r--r-- | include/hw/pci-host/gpex.h | 3 | ||||
| -rw-r--r-- | include/hw/pci/pci_ids.h | 1 | ||||
| -rw-r--r-- | include/hw/ppc/spapr_ovec.h | 3 |
4 files changed, 8 insertions, 1 deletions
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c2931bf39c..6eff81a995 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -91,6 +91,8 @@ typedef struct XlnxZynqMPState { /* Has the ARM Security extensions? */ bool secure; + /* Has the ARM Virtualization extensions? */ + bool virt; /* Has the RPU subsystem? */ bool has_rpu; } XlnxZynqMPState; diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 68c93488c9..aef38b881b 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -51,6 +51,9 @@ typedef struct GPEXHost { MemoryRegion io_ioport; MemoryRegion io_mmio; qemu_irq irq[GPEX_NUM_IRQS]; + int irq_num[GPEX_NUM_IRQS]; } GPEXHost; +int gpex_set_irq_num(GPEXHost *s, int index, int gsi); + #endif /* HW_GPEX_H */ diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 3752ddc93a..b9c2bad851 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -183,6 +183,7 @@ #define PCI_VENDOR_ID_APPLE 0x106b #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 #define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 #define PCI_VENDOR_ID_SUN 0x108e #define PCI_DEVICE_ID_SUN_EBUS 0x1000 diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index 9edfa5ff75..bf25e5d954 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -51,7 +51,8 @@ typedef struct sPAPROptionVector sPAPROptionVector; #define OV5_FORM1_AFFINITY OV_BIT(5, 0) #define OV5_HP_EVT OV_BIT(6, 5) #define OV5_HPT_RESIZE OV_BIT(6, 7) -#define OV5_XIVE_EXPLOIT OV_BIT(23, 7) +#define OV5_XIVE_BOTH OV_BIT(23, 0) +#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ /* ISA 3.00 MMU features: */ #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */ |