diff options
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/armsse.h | 7 | ||||
| -rw-r--r-- | include/hw/char/pl011.h | 34 | ||||
| -rw-r--r-- | include/hw/misc/tz-ppc.h | 8 | ||||
| -rw-r--r-- | include/hw/timer/pl031.h | 44 | ||||
| -rw-r--r-- | include/hw/virtio/virtio-gpu.h | 10 |
5 files changed, 96 insertions, 7 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f800bafb14..7ef871c7df 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -46,6 +46,10 @@ * being the same for both, to avoid having to have separate Property * lists for different variants. This restriction can be relaxed later * if necessary.) + * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the + * address of each SRAM bank (and thus the total amount of internal SRAM) + * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register + * (where it expects to load the PC and SP from the vector table on reset) * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for @@ -182,7 +186,7 @@ typedef struct ARMSSE { MemoryRegion cpu_container[SSE_MAX_CPUS]; MemoryRegion alias1; MemoryRegion alias2; - MemoryRegion alias3; + MemoryRegion alias3[SSE_MAX_CPUS]; MemoryRegion sram[MAX_SRAM_BANKS]; qemu_irq *exp_irqs[SSE_MAX_CPUS]; @@ -202,6 +206,7 @@ typedef struct ARMSSE { uint32_t exp_numirq; uint32_t mainclk_frq; uint32_t sram_addr_width; + uint32_t init_svtor; } ARMSSE; typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 83649324b6..dad3cf2912 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -15,6 +15,40 @@ #ifndef HW_PL011_H #define HW_PL011_H +#include "hw/sysbus.h" +#include "chardev/char-fe.h" + +#define TYPE_PL011 "pl011" +#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011) + +/* This shares the same struct (and cast macro) as the base pl011 device */ +#define TYPE_PL011_LUMINARY "pl011_luminary" + +typedef struct PL011State { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t readbuff; + uint32_t flags; + uint32_t lcr; + uint32_t rsr; + uint32_t cr; + uint32_t dmacr; + uint32_t int_enabled; + uint32_t int_level; + uint32_t read_fifo[16]; + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + uint32_t ifl; + int read_pos; + int read_count; + int read_trigger; + CharBackend chr; + qemu_irq irq[6]; + const unsigned char *id; +} PL011State; + static inline DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h index fc8b806e4d..080d6e2ec1 100644 --- a/include/hw/misc/tz-ppc.h +++ b/include/hw/misc/tz-ppc.h @@ -38,7 +38,13 @@ * * QEMU interface: * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end - * of each of the 16 ports of the PPC + * of each of the 16 ports of the PPC. When a port is unused (i.e. no + * downstream MemoryRegion is connected to it) at the end of the 0..15 + * range then no sysbus MMIO region is created for its upstream. When an + * unused port lies in the middle of the range with other used ports at + * higher port numbers, a dummy MMIO region is created to ensure that + * port N's upstream is always sysbus MMIO region N. Dummy regions should + * not be mapped, and will assert if any access is made to them. * + Property "port[0..15]": MemoryRegion defining the downstream device(s) * for each of the 16 ports of the PPC * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h new file mode 100644 index 0000000000..99416d8ba5 --- /dev/null +++ b/include/hw/timer/pl031.h @@ -0,0 +1,44 @@ +/* + * ARM AMBA PrimeCell PL031 RTC + * + * Copyright (c) 2007 CodeSourcery + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef HW_TIMER_PL031 +#define HW_TIMER_PL031 + +#include "hw/sysbus.h" + +#define TYPE_PL031 "pl031" +#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031) + +typedef struct PL031State { + SysBusDevice parent_obj; + + MemoryRegion iomem; + QEMUTimer *timer; + qemu_irq irq; + + /* + * Needed to preserve the tick_count across migration, even if the + * absolute value of the rtc_clock is different on the source and + * destination. + */ + uint32_t tick_offset_vmstate; + uint32_t tick_offset; + + uint32_t mr; + uint32_t lr; + uint32_t cr; + uint32_t im; + uint32_t is; +} PL031State; + +#endif diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index c8c599f1b9..98504f9075 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -61,12 +61,15 @@ struct virtio_gpu_requested_state { enum virtio_gpu_conf_flags { VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, VIRTIO_GPU_FLAG_STATS_ENABLED, + VIRTIO_GPU_FLAG_EDID_ENABLED, }; #define virtio_gpu_virgl_enabled(_cfg) \ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) #define virtio_gpu_stats_enabled(_cfg) \ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) +#define virtio_gpu_edid_enabled(_cfg) \ + (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED)) struct virtio_gpu_conf { uint64_t max_hostmem; @@ -81,7 +84,6 @@ struct virtio_gpu_ctrl_command { VirtQueue *vq; struct virtio_gpu_ctrl_hdr cmd_hdr; uint32_t error; - bool waiting; bool finished; QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; }; @@ -96,9 +98,6 @@ typedef struct VirtIOGPU { int enable; - int config_size; - DeviceState *qdev; - QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; @@ -159,6 +158,8 @@ void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, enum virtio_gpu_ctrl_type type); void virtio_gpu_get_display_info(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); +void virtio_gpu_get_edid(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd); int virtio_gpu_create_mapping_iov(VirtIOGPU *g, struct virtio_gpu_resource_attach_backing *ab, struct virtio_gpu_ctrl_command *cmd, @@ -172,7 +173,6 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); void virtio_gpu_virgl_reset(VirtIOGPU *g); -void virtio_gpu_gl_block(void *opaque, bool block); int virtio_gpu_virgl_init(VirtIOGPU *g); int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); #endif |