diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/exec/memory.h | 4 | ||||
| -rw-r--r-- | include/hw/pci-host/pnv_phb4.h | 80 | ||||
| -rw-r--r-- | include/hw/pci/pci.h | 12 | ||||
| -rw-r--r-- | include/hw/scsi/scsi.h | 4 | ||||
| -rw-r--r-- | include/sysemu/dma.h | 31 |
5 files changed, 62 insertions, 69 deletions
diff --git a/include/exec/memory.h b/include/exec/memory.h index 20f1b27377..63be794a06 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -738,6 +738,7 @@ struct MemoryRegion { const MemoryRegionOps *ops; void *opaque; MemoryRegion *container; + int mapped_via_alias; /* Mapped via an alias, container might be NULL */ Int128 size; hwaddr addr; void (*destructor)(MemoryRegion *mr); @@ -2296,7 +2297,8 @@ bool memory_region_present(MemoryRegion *container, hwaddr addr); /** * memory_region_is_mapped: returns true if #MemoryRegion is mapped - * into any address space. + * into another memory region, which does not necessarily imply that it is + * mapped into an address space. * * @mr: a #MemoryRegion which should be checked if it's mapped */ diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 4b7ce8a723..0c7635dec5 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -84,6 +84,9 @@ struct PnvPHB4 { uint64_t version; + /* The owner PEC */ + PnvPhb4PecState *pec; + char bus_path[8]; /* Main register images */ @@ -107,6 +110,29 @@ struct PnvPHB4 { MemoryRegion pci_mmio; MemoryRegion pci_io; + /* PCI registers (excluding pass-through) */ +#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf + uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; + MemoryRegion pci_regs_mr; + + /* Nest registers */ +#define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 + uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; + MemoryRegion nest_regs_mr; + + /* PHB pass-through XSCOM */ + MemoryRegion phb_regs_mr; + + /* Memory windows from PowerBus to PHB */ + MemoryRegion phbbar; + MemoryRegion intbar; + MemoryRegion mmbar0; + MemoryRegion mmbar1; + uint64_t mmio0_base; + uint64_t mmio0_size; + uint64_t mmio1_base; + uint64_t mmio1_size; + /* On-chip IODA tables */ uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; @@ -125,8 +151,6 @@ struct PnvPHB4 { XiveSource xsrc; qemu_irq *qirqs; - PnvPhb4PecStack *stack; - QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; }; @@ -140,49 +164,6 @@ extern const MemoryRegionOps pnv_phb4_xscom_ops; #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec" OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC) -#define TYPE_PNV_PHB4_PEC_STACK "pnv-phb4-pec-stack" -OBJECT_DECLARE_SIMPLE_TYPE(PnvPhb4PecStack, PNV_PHB4_PEC_STACK) - -/* Per-stack data */ -struct PnvPhb4PecStack { - DeviceState parent; - - /* My own stack number */ - uint32_t stack_no; - - /* Nest registers */ -#define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 - uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; - MemoryRegion nest_regs_mr; - - /* PCI registers (excluding pass-through) */ -#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf - uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; - MemoryRegion pci_regs_mr; - - /* PHB pass-through XSCOM */ - MemoryRegion phb_regs_mr; - - /* Memory windows from PowerBus to PHB */ - MemoryRegion mmbar0; - MemoryRegion mmbar1; - MemoryRegion phbbar; - MemoryRegion intbar; - uint64_t mmio0_base; - uint64_t mmio0_size; - uint64_t mmio1_base; - uint64_t mmio1_size; - - /* The owner PEC */ - PnvPhb4PecState *pec; - - /* - * PHB4 pointer. pnv_phb4_update_regions() needs to access - * the PHB4 via a PnvPhb4PecStack pointer. - */ - PnvPHB4 *phb; -}; - struct PnvPhb4PecState { DeviceState parent; @@ -202,10 +183,8 @@ struct PnvPhb4PecState { uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; MemoryRegion pci_regs_mr; - /* Stacks */ - #define PHB4_PEC_MAX_STACKS 3 - uint32_t num_stacks; - PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS]; + /* PHBs */ + uint32_t num_phbs; PnvChip *chip; }; @@ -223,7 +202,8 @@ struct PnvPhb4PecClass { const char *stk_compat; int stk_compat_size; uint64_t version; - const uint32_t *num_stacks; + const uint32_t *num_phbs; + const char *rp_model; }; #endif /* PCI_HOST_PNV_PHB4_H */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 483d5c7c72..023abc0f79 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -881,6 +881,18 @@ PCI_DMA_DEFINE_LDST(q_be, q_be, 64); #undef PCI_DMA_DEFINE_LDST +/** + * pci_dma_map: Map device PCI address space range into host virtual address + * @dev: #PCIDevice to be accessed + * @addr: address within that device's address space + * @plen: pointer to length of buffer; updated on return to indicate + * if only a subset of the requested range has been mapped + * @dir: indicates the transfer direction + * + * Return: A host pointer, or %NULL if the resources needed to + * perform the mapping are exhausted (in that case *@plen + * is set to zero). + */ static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, dma_addr_t *plen, DMADirection dir) { diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h index 2ef80af6dc..1ffb367f94 100644 --- a/include/hw/scsi/scsi.h +++ b/include/hw/scsi/scsi.h @@ -30,7 +30,7 @@ struct SCSIRequest { int16_t status; int16_t host_status; void *hba_private; - size_t resid; + uint64_t residual; SCSICommand cmd; NotifierList cancel_notifiers; @@ -125,7 +125,7 @@ struct SCSIBusInfo { void *hba_private); void (*transfer_data)(SCSIRequest *req, uint32_t arg); void (*fail)(SCSIRequest *req); - void (*complete)(SCSIRequest *req, size_t resid); + void (*complete)(SCSIRequest *req, size_t residual); void (*cancel)(SCSIRequest *req); void (*change)(SCSIBus *bus, SCSIDevice *dev, SCSISense sense); QEMUSGList *(*get_sg_list)(SCSIRequest *req); diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index b3faef41b2..a1ac5bc1b5 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -15,24 +15,11 @@ #include "block/block.h" #include "block/accounting.h" -typedef struct ScatterGatherEntry ScatterGatherEntry; - typedef enum { DMA_DIRECTION_TO_DEVICE = 0, DMA_DIRECTION_FROM_DEVICE = 1, } DMADirection; -struct QEMUSGList { - ScatterGatherEntry *sg; - int nsg; - int nalloc; - size_t size; - DeviceState *dev; - AddressSpace *as; -}; - -#ifndef CONFIG_USER_ONLY - /* * When an IOMMU is present, bus addresses become distinct from * CPU/memory physical addresses and may be a different size. Because @@ -45,6 +32,17 @@ typedef uint64_t dma_addr_t; #define DMA_ADDR_BITS 64 #define DMA_ADDR_FMT "%" PRIx64 +typedef struct ScatterGatherEntry ScatterGatherEntry; + +struct QEMUSGList { + ScatterGatherEntry *sg; + int nsg; + int nalloc; + dma_addr_t size; + DeviceState *dev; + AddressSpace *as; +}; + static inline void dma_barrier(AddressSpace *as, DMADirection dir) { /* @@ -288,7 +286,6 @@ void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint, AddressSpace *as); void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len); void qemu_sglist_destroy(QEMUSGList *qsg); -#endif typedef BlockAIOCB *DMAIOFunc(int64_t offset, QEMUIOVector *iov, BlockCompletionFunc *cb, void *cb_opaque, @@ -304,8 +301,10 @@ BlockAIOCB *dma_blk_read(BlockBackend *blk, BlockAIOCB *dma_blk_write(BlockBackend *blk, QEMUSGList *sg, uint64_t offset, uint32_t align, BlockCompletionFunc *cb, void *opaque); -uint64_t dma_buf_read(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs attrs); -uint64_t dma_buf_write(void *ptr, int32_t len, QEMUSGList *sg, MemTxAttrs attrs); +MemTxResult dma_buf_read(void *ptr, dma_addr_t len, dma_addr_t *residual, + QEMUSGList *sg, MemTxAttrs attrs); +MemTxResult dma_buf_write(void *ptr, dma_addr_t len, dma_addr_t *residual, + QEMUSGList *sg, MemTxAttrs attrs); void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie, QEMUSGList *sg, enum BlockAcctType type); |