diff options
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.h | 4 | ||||
| -rw-r--r-- | target-arm/helper.c | 91 | ||||
| -rw-r--r-- | target-arm/helper.h | 1 | ||||
| -rw-r--r-- | target-arm/op_helper.c | 9 | ||||
| -rw-r--r-- | target-arm/translate-a64.c | 2 | ||||
| -rw-r--r-- | target-arm/translate.c | 6 | ||||
| -rw-r--r-- | target-arm/translate.h | 2 |
7 files changed, 109 insertions, 6 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 49fef3fcbe..0a7edfe6cb 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -222,6 +222,10 @@ typedef struct CPUARMState { uint64_t dbgbcr[16]; /* breakpoint control registers */ uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value + */ + uint32_t c15_ccnt; } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 90f85f1899..f65cbac1ee 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -13,6 +13,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address, int access_type, int is_user, hwaddr *phys_ptr, int *prot, target_ulong *page_size); + +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 #endif static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) @@ -478,13 +483,84 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri) return CP_ACCESS_OK; } +#ifndef CONFIG_USER_ONLY static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + /* Don't computer the number of ticks in user mode */ + uint32_t temp_ticks; + + temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRE) { + /* If the counter is enabled */ + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; + } else { + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } + } + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt = 0; + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); + + if (env->cp15.c9_pmcr & PMCRE) { + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /= 64; + } + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } +} + +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t total_ticks; + + if (!(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, do not change value */ + return env->cp15.c15_ccnt; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + return total_ticks - env->cp15.c15_ccnt; +} + +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t total_ticks; + + if (!(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, set the absolute value */ + env->cp15.c15_ccnt = value; + return; + } + + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec() / 1000000; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + total_ticks /= 64; + } + env->cp15.c15_ccnt = total_ticks - value; } +#endif static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -604,10 +680,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, .accessfn = pmreg_access }, - /* Unimplemented, RAZ/WI. */ +#ifndef CONFIG_USER_ONLY { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, + .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, + .readfn = pmccntr_read, .writefn = pmccntr_write, .accessfn = pmreg_access }, +#endif { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), @@ -1873,8 +1951,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement no event counters. + * field as main ID register, and we implement only the cycle + * count register. */ +#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr = { .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, @@ -1882,12 +1962,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn = pmreg_access, .writefn = pmcr_write, .raw_writefn = raw_write, }; + define_one_arm_cp_reg(cpu, &pmcr); +#endif ARMCPRegInfo clidr = { .name = "CLIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr }; - define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); } else { @@ -2478,7 +2559,7 @@ uint32_t cpsr_read(CPUARMState *env) (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | ((env->condexec_bits & 0xfc) << 8) - | (env->GE << 16) | env->daif; + | (env->GE << 16) | (env->daif & CPSR_AIF); } void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) diff --git a/target-arm/helper.h b/target-arm/helper.h index 276f3a9149..8923f8ae71 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -50,6 +50,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception, void, env, i32) DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(wfe, void, env) DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 7d06d2f9a5..5851e041a0 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -225,6 +225,15 @@ void HELPER(wfi)(CPUARMState *env) cpu_loop_exit(env); } +void HELPER(wfe)(CPUARMState *env) +{ + /* Don't actually halt the CPU, just yield back to top + * level loop + */ + env->exception_index = EXCP_YIELD; + cpu_loop_exit(env); +} + void HELPER(exception)(CPUARMState *env, uint32_t excp) { env->exception_index = excp; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 08ac6591b6..37e05e81f7 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -210,7 +210,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); - tcg_gen_exit_tb((tcg_target_long)tb + n); + tcg_gen_exit_tb((intptr_t)tb + n); s->is_jmp = DISAS_TB_JUMP; } else { gen_a64_set_pc_im(dest); diff --git a/target-arm/translate.c b/target-arm/translate.c index 253d2a13eb..df259debcc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3939,6 +3939,9 @@ static void gen_nop_hint(DisasContext *s, int val) s->is_jmp = DISAS_WFI; break; case 2: /* wfe */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_WFE; + break; case 4: /* sev */ case 5: /* sevl */ /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */ @@ -10857,6 +10860,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, case DISAS_WFI: gen_helper_wfi(cpu_env); break; + case DISAS_WFE: + gen_helper_wfe(cpu_env); + break; case DISAS_SWI: gen_exception(EXCP_SWI); break; diff --git a/target-arm/translate.h b/target-arm/translate.h index 67da6996c9..2f491f9ff6 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -44,6 +44,8 @@ extern TCGv_ptr cpu_env; * emitting unreachable code at the end of the TB in the A64 decoder */ #define DISAS_EXC 6 +/* WFE */ +#define DISAS_WFE 7 #ifdef TARGET_AARCH64 void a64_translate_init(void); |