diff options
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cc_helper.c | 2 | ||||
| -rw-r--r-- | target-i386/cpu.h | 5 | ||||
| -rw-r--r-- | target-i386/fpu_helper.c | 15 | ||||
| -rw-r--r-- | target-i386/gdbstub.c | 2 | ||||
| -rw-r--r-- | target-i386/translate.c | 48 |
5 files changed, 52 insertions, 20 deletions
diff --git a/target-i386/cc_helper.c b/target-i386/cc_helper.c index ee04092b4e..05dd12b5a7 100644 --- a/target-i386/cc_helper.c +++ b/target-i386/cc_helper.c @@ -103,7 +103,7 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1, case CC_OP_EFLAGS: return src1; case CC_OP_CLR: - return CC_Z; + return CC_Z | CC_P; case CC_OP_MULB: return compute_all_mulb(dst, src1); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 1b94f0ffb7..0014acca7b 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -38,8 +38,10 @@ #ifdef TARGET_X86_64 #define ELF_MACHINE EM_X86_64 +#define ELF_MACHINE_UNAME "x86_64" #else #define ELF_MACHINE EM_386 +#define ELF_MACHINE_UNAME "i686" #endif #define CPUArchState struct CPUX86State @@ -1259,6 +1261,9 @@ static inline void cpu_load_efer(CPUX86State *env, uint64_t val) } } +/* fpu_helper.c */ +void cpu_set_mxcsr(CPUX86State *env, uint32_t val); + /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param); diff --git a/target-i386/fpu_helper.c b/target-i386/fpu_helper.c index c0427fec7a..de7ba76a49 100644 --- a/target-i386/fpu_helper.c +++ b/target-i386/fpu_helper.c @@ -1179,7 +1179,7 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64) if (env->cr[4] & CR4_OSFXSR_MASK) { /* XXX: finish it */ - env->mxcsr = cpu_ldl_data(env, ptr + 0x18); + cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18)); /* cpu_ldl_data(env, ptr + 0x1c); */ if (env->hflags & HF_CS64_MASK) { nb_xmm_regs = 16; @@ -1229,12 +1229,14 @@ floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) #define SSE_RC_CHOP 0x6000 #define SSE_FZ 0x8000 -static void update_sse_status(CPUX86State *env) +void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) { int rnd_type; + env->mxcsr = mxcsr; + /* set rounding mode */ - switch (env->mxcsr & SSE_RC_MASK) { + switch (mxcsr & SSE_RC_MASK) { default: case SSE_RC_NEAR: rnd_type = float_round_nearest_even; @@ -1252,16 +1254,15 @@ static void update_sse_status(CPUX86State *env) set_float_rounding_mode(rnd_type, &env->sse_status); /* set denormals are zero */ - set_flush_inputs_to_zero((env->mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); + set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); /* set flush to zero */ - set_flush_to_zero((env->mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); + set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); } void helper_ldmxcsr(CPUX86State *env, uint32_t val) { - env->mxcsr = val; - update_sse_status(env); + cpu_set_mxcsr(env, val); } void helper_enter_mmx(CPUX86State *env) diff --git a/target-i386/gdbstub.c b/target-i386/gdbstub.c index 15bebeff89..d34e5355f7 100644 --- a/target-i386/gdbstub.c +++ b/target-i386/gdbstub.c @@ -222,7 +222,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 4; case IDX_MXCSR_REG: - env->mxcsr = ldl_p(mem_buf); + cpu_set_mxcsr(env, ldl_p(mem_buf)); return 4; } } diff --git a/target-i386/translate.c b/target-i386/translate.c index 5dd2450798..707ebd5ca0 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -748,7 +748,7 @@ static void gen_compute_eflags(DisasContext *s) return; } if (s->cc_op == CC_OP_CLR) { - tcg_gen_movi_tl(cpu_cc_src, CC_Z); + tcg_gen_movi_tl(cpu_cc_src, CC_Z | CC_P); set_cc_op(s, CC_OP_EFLAGS); return; } @@ -4284,22 +4284,48 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (is_xmm) { op1_offset = offsetof(CPUX86State,xmm_regs[reg]); if (mod != 3) { + int sz = 4; + gen_lea_modrm(env, s, modrm); op2_offset = offsetof(CPUX86State,xmm_t0); - if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || - b == 0xc2)) { - /* specific case for SSE single instructions */ + + switch (b) { + case 0x50 ... 0x5a: + case 0x5c ... 0x5f: + case 0xc2: + /* Most sse scalar operations. */ if (b1 == 2) { - /* 32 bit access */ - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); + sz = 2; + } else if (b1 == 3) { + sz = 3; + } + break; + + case 0x2e: /* ucomis[sd] */ + case 0x2f: /* comis[sd] */ + if (b1 == 0) { + sz = 2; } else { - /* 64 bit access */ - gen_ldq_env_A0(s, offsetof(CPUX86State, - xmm_t0.XMM_D(0))); + sz = 3; } - } else { + break; + } + + switch (sz) { + case 2: + /* 32 bit access */ + gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); + tcg_gen_st32_tl(cpu_T[0], cpu_env, + offsetof(CPUX86State,xmm_t0.XMM_L(0))); + break; + case 3: + /* 64 bit access */ + gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_D(0))); + break; + default: + /* 128 bit access */ gen_ldo_env_A0(s, op2_offset); + break; } } else { rm = (modrm & 7) | REX_B(s); |