diff options
Diffstat (limited to 'target-mips/op_helper.c')
| -rw-r--r-- | target-mips/op_helper.c | 1065 |
1 files changed, 560 insertions, 505 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 3d242aafda..ce5ddaf050 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -18,8 +18,6 @@ */ #include <stdlib.h> #include "cpu.h" -#include "dyngen-exec.h" - #include "host-utils.h" #include "helper.h" @@ -35,7 +33,8 @@ static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); /*****************************************************************************/ /* Exceptions processing helpers */ -void helper_raise_exception_err (uint32_t exception, int error_code) +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) { #if 1 if (exception < 0x100) @@ -46,13 +45,13 @@ void helper_raise_exception_err (uint32_t exception, int error_code) cpu_loop_exit(env); } -void helper_raise_exception (uint32_t exception) +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) { - helper_raise_exception_err(exception, 0); + helper_raise_exception_err(env, exception, 0); } #if !defined(CONFIG_USER_ONLY) -static void do_restore_state(uintptr_t pc) +static void do_restore_state(CPUMIPSState *env, uintptr_t pc) { TranslationBlock *tb; @@ -65,20 +64,22 @@ static void do_restore_state(uintptr_t pc) #if defined(CONFIG_USER_ONLY) #define HELPER_LD(name, insn, type) \ -static inline type do_##name(target_ulong addr, int mem_idx) \ +static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ + int mem_idx) \ { \ return (type) insn##_raw(addr); \ } #else #define HELPER_LD(name, insn, type) \ -static inline type do_##name(target_ulong addr, int mem_idx) \ +static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ + int mem_idx) \ { \ switch (mem_idx) \ { \ - case 0: return (type) insn##_kernel(addr); break; \ - case 1: return (type) insn##_super(addr); break; \ + case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ + case 1: return (type) cpu_##insn##_super(env, addr); break; \ default: \ - case 2: return (type) insn##_user(addr); break; \ + case 2: return (type) cpu_##insn##_user(env, addr); break; \ } \ } #endif @@ -91,20 +92,22 @@ HELPER_LD(ld, ldq, int64_t) #if defined(CONFIG_USER_ONLY) #define HELPER_ST(name, insn, type) \ -static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ + type val, int mem_idx) \ { \ insn##_raw(addr, val); \ } #else #define HELPER_ST(name, insn, type) \ -static inline void do_##name(target_ulong addr, type val, int mem_idx) \ +static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ + type val, int mem_idx) \ { \ switch (mem_idx) \ { \ - case 0: insn##_kernel(addr, val); break; \ - case 1: insn##_super(addr, val); break; \ + case 0: cpu_##insn##_kernel(env, addr, val); break; \ + case 1: cpu_##insn##_super(env, addr, val); break; \ default: \ - case 2: insn##_user(addr, val); break; \ + case 2: cpu_##insn##_user(env, addr, val); break; \ } \ } #endif @@ -138,12 +141,12 @@ target_ulong helper_dclz (target_ulong arg1) #endif /* TARGET_MIPS64 */ /* 64 bits arithmetic for 32 bits hosts */ -static inline uint64_t get_HILO (void) +static inline uint64_t get_HILO(CPUMIPSState *env) { return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; } -static inline target_ulong set_HIT0_LO(uint64_t HILO) +static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) { target_ulong tmp; env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); @@ -151,7 +154,7 @@ static inline target_ulong set_HIT0_LO(uint64_t HILO) return tmp; } -static inline target_ulong set_HI_LOT0(uint64_t HILO) +static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) { target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); env->active_tc.HI[0] = (int32_t)(HILO >> 32); @@ -159,91 +162,110 @@ static inline target_ulong set_HI_LOT0(uint64_t HILO) } /* Multiplication variants of the vr54xx. */ -target_ulong helper_muls (target_ulong arg1, target_ulong arg2) +target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0(0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); + return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2)); } -target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0(0 - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); } -target_ulong helper_macc (target_ulong arg1, target_ulong arg2) +target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((int64_t)get_HILO() + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) +target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((int64_t)get_HILO() + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) +target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HI_LOT0(env, (uint64_t)get_HILO(env) + + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((uint64_t)get_HILO() + (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, (uint64_t)get_HILO(env) + + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_msac (target_ulong arg1, target_ulong arg2) +target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((int64_t)get_HILO() - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) +target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((int64_t)get_HILO() - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) +target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HI_LOT0((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HI_LOT0(env, (uint64_t)get_HILO(env) - + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((uint64_t)get_HILO() - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, (uint64_t)get_HILO(env) - + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); } -target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); } -target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); } -target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO(0 - (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); + return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); } -target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) +target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) { - return set_HIT0_LO(0 - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); + return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); } #ifdef TARGET_MIPS64 -void helper_dmult (target_ulong arg1, target_ulong arg2) +void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) { muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); } -void helper_dmultu (target_ulong arg1, target_ulong arg2) +void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) { mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); } @@ -251,7 +273,9 @@ void helper_dmultu (target_ulong arg1, target_ulong arg2) #ifndef CONFIG_USER_ONLY -static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) +static inline target_phys_addr_t do_translate_address(CPUMIPSState *env, + target_ulong address, + int rw) { target_phys_addr_t lladdr; @@ -265,10 +289,10 @@ static inline target_phys_addr_t do_translate_address(target_ulong address, int } #define HELPER_LD_ATOMIC(name, insn) \ -target_ulong helper_##name(target_ulong arg, int mem_idx) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ { \ - env->lladdr = do_translate_address(arg, 0); \ - env->llval = do_##insn(arg, mem_idx); \ + env->lladdr = do_translate_address(env, arg, 0); \ + env->llval = do_##insn(env, arg, mem_idx); \ return env->llval; \ } HELPER_LD_ATOMIC(ll, lw) @@ -278,18 +302,19 @@ HELPER_LD_ATOMIC(lld, ld) #undef HELPER_LD_ATOMIC #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ -target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ + target_ulong arg2, int mem_idx) \ { \ target_long tmp; \ \ if (arg2 & almask) { \ env->CP0_BadVAddr = arg2; \ - helper_raise_exception(EXCP_AdES); \ + helper_raise_exception(env, EXCP_AdES); \ } \ - if (do_translate_address(arg2, 1) == env->lladdr) { \ - tmp = do_##ld_insn(arg2, mem_idx); \ + if (do_translate_address(env, arg2, 1) == env->lladdr) { \ + tmp = do_##ld_insn(env, arg2, mem_idx); \ if (tmp == env->llval) { \ - do_##st_insn(arg2, arg1, mem_idx); \ + do_##st_insn(env, arg2, arg1, mem_idx); \ return 1; \ } \ } \ @@ -310,80 +335,84 @@ HELPER_ST_ATOMIC(scd, ld, sd, 0x7) #define GET_OFFSET(addr, offset) (addr - (offset)) #endif -target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { target_ulong tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); if (GET_LMASK(arg2) <= 2) { - tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx); arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); } if (GET_LMASK(arg2) <= 1) { - tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx); arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); } if (GET_LMASK(arg2) == 0) { - tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx); arg1 = (arg1 & 0xFFFFFF00) | tmp; } return (int32_t)arg1; } -target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { target_ulong tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0xFFFFFF00) | tmp; if (GET_LMASK(arg2) >= 1) { - tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx); arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); } if (GET_LMASK(arg2) >= 2) { - tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx); arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); } if (GET_LMASK(arg2) == 3) { - tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx); arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); } return (int32_t)arg1; } -void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx); if (GET_LMASK(arg2) <= 2) - do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK(arg2) <= 1) - do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK(arg2) == 0) - do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); + do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); } -void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)arg1, mem_idx); + do_sb(env, arg2, (uint8_t)arg1, mem_idx); if (GET_LMASK(arg2) >= 1) - do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK(arg2) >= 2) - do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK(arg2) == 3) - do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); } #if defined(TARGET_MIPS64) @@ -396,167 +425,172 @@ void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) #define GET_LMASK64(v) (((v) & 7) ^ 7) #endif -target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { uint64_t tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); if (GET_LMASK64(arg2) <= 6) { - tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx); arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); } if (GET_LMASK64(arg2) <= 5) { - tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx); arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); } if (GET_LMASK64(arg2) <= 4) { - tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx); arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); } if (GET_LMASK64(arg2) <= 3) { - tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx); arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); } if (GET_LMASK64(arg2) <= 2) { - tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); } if (GET_LMASK64(arg2) <= 1) { - tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); } if (GET_LMASK64(arg2) == 0) { - tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; } return arg1; } -target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx) +target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2, int mem_idx) { uint64_t tmp; - tmp = do_lbu(arg2, mem_idx); + tmp = do_lbu(env, arg2, mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; if (GET_LMASK64(arg2) >= 1) { - tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); } if (GET_LMASK64(arg2) >= 2) { - tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx); arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); } if (GET_LMASK64(arg2) >= 3) { - tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx); arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); } if (GET_LMASK64(arg2) >= 4) { - tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx); arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); } if (GET_LMASK64(arg2) >= 5) { - tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx); arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); } if (GET_LMASK64(arg2) >= 6) { - tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx); arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); } if (GET_LMASK64(arg2) == 7) { - tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx); + tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx); arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); } return arg1; } -void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx); + do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx); if (GET_LMASK64(arg2) <= 6) - do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); + do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); if (GET_LMASK64(arg2) <= 5) - do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); + do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); if (GET_LMASK64(arg2) <= 4) - do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); + do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); if (GET_LMASK64(arg2) <= 3) - do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); if (GET_LMASK64(arg2) <= 2) - do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK64(arg2) <= 1) - do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK64(arg2) <= 0) - do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); + do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); } -void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) { - do_sb(arg2, (uint8_t)arg1, mem_idx); + do_sb(env, arg2, (uint8_t)arg1, mem_idx); if (GET_LMASK64(arg2) >= 1) - do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); if (GET_LMASK64(arg2) >= 2) - do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); if (GET_LMASK64(arg2) >= 3) - do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); if (GET_LMASK64(arg2) >= 4) - do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); + do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); if (GET_LMASK64(arg2) >= 5) - do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); + do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); if (GET_LMASK64(arg2) >= 6) - do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); + do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); if (GET_LMASK64(arg2) == 7) - do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); + do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); } #endif /* TARGET_MIPS64 */ static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; -void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef ldfun -#define ldfun ldl_raw +#define ldfun(env, addr) ldl_raw(addr) #else - uint32_t (*ldfun)(target_ulong); + uint32_t (*ldfun)(CPUMIPSState *env, target_ulong); switch (mem_idx) { - case 0: ldfun = ldl_kernel; break; - case 1: ldfun = ldl_super; break; + case 0: ldfun = cpu_ldl_kernel; break; + case 1: ldfun = cpu_ldl_super; break; default: - case 2: ldfun = ldl_user; break; + case 2: ldfun = cpu_ldl_user; break; } #endif @@ -564,32 +598,33 @@ void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr); + env->active_tc.gpr[multiple_regs[i]] = (target_long)ldfun(env, addr); addr += 4; } } if (do_r31) { - env->active_tc.gpr[31] = (target_long) ldfun(addr); + env->active_tc.gpr[31] = (target_long)ldfun(env, addr); } } -void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef stfun -#define stfun stl_raw +#define stfun(env, addr, val) stl_raw(addr, val) #else - void (*stfun)(target_ulong, uint32_t); + void (*stfun)(CPUMIPSState *env, target_ulong, uint32_t); switch (mem_idx) { - case 0: stfun = stl_kernel; break; - case 1: stfun = stl_super; break; + case 0: stfun = cpu_stl_kernel; break; + case 1: stfun = cpu_stl_super; break; default: - case 2: stfun = stl_user; break; + case 2: stfun = cpu_stl_user; break; } #endif @@ -597,33 +632,34 @@ void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - stfun(addr, env->active_tc.gpr[multiple_regs[i]]); + stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); addr += 4; } } if (do_r31) { - stfun(addr, env->active_tc.gpr[31]); + stfun(env, addr, env->active_tc.gpr[31]); } } #if defined(TARGET_MIPS64) -void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef ldfun -#define ldfun ldq_raw +#define ldfun(env, addr) ldq_raw(addr) #else - uint64_t (*ldfun)(target_ulong); + uint64_t (*ldfun)(CPUMIPSState *env, target_ulong); switch (mem_idx) { - case 0: ldfun = ldq_kernel; break; - case 1: ldfun = ldq_super; break; + case 0: ldfun = cpu_ldq_kernel; break; + case 1: ldfun = cpu_ldq_super; break; default: - case 2: ldfun = ldq_user; break; + case 2: ldfun = cpu_ldq_user; break; } #endif @@ -631,32 +667,33 @@ void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = ldfun(addr); + env->active_tc.gpr[multiple_regs[i]] = ldfun(env, addr); addr += 8; } } if (do_r31) { - env->active_tc.gpr[31] = ldfun(addr); + env->active_tc.gpr[31] = ldfun(env, addr); } } -void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; #ifdef CONFIG_USER_ONLY #undef stfun -#define stfun stq_raw +#define stfun(env, addr, val) stq_raw(addr, val) #else - void (*stfun)(target_ulong, uint64_t); + void (*stfun)(CPUMIPSState *env, target_ulong, uint64_t); switch (mem_idx) { - case 0: stfun = stq_kernel; break; - case 1: stfun = stq_super; break; + case 0: stfun = cpu_stq_kernel; break; + case 1: stfun = cpu_stq_super; break; default: - case 2: stfun = stq_user; break; + case 2: stfun = cpu_stq_user; break; } #endif @@ -664,13 +701,13 @@ void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx) target_ulong i; for (i = 0; i < base_reglist; i++) { - stfun(addr, env->active_tc.gpr[multiple_regs[i]]); + stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); addr += 8; } } if (do_r31) { - stfun(addr, env->active_tc.gpr[31]); + stfun(env, addr, env->active_tc.gpr[31]); } } #endif @@ -723,7 +760,7 @@ static inline void mips_tc_sleep(CPUMIPSState *c, int tc) FIXME: This code assumes that all VPEs have the same number of TCs, which depends on runtime setup. Can probably be fixed by walking the list of CPUMIPSStates. */ -static CPUMIPSState *mips_cpu_map_tc(int *tc) +static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) { CPUMIPSState *other; int vpe_idx, nr_threads = env->nr_threads; @@ -750,7 +787,7 @@ static CPUMIPSState *mips_cpu_map_tc(int *tc) These helper call synchronizes the regs for a given cpu. */ /* Called for updates to CP0_Status. */ -static void sync_c0_status(CPUMIPSState *cpu, int tc) +static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) { int32_t tcstatus, *tcst; uint32_t v = cpu->CP0_Status; @@ -785,7 +822,8 @@ static void sync_c0_status(CPUMIPSState *cpu, int tc) } /* Called for updates to CP0_TCStatus. */ -static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, target_ulong v) +static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, + target_ulong v) { uint32_t status; uint32_t tcu, tmx, tasid, tksu; @@ -834,35 +872,35 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) } /* CP0 helpers */ -target_ulong helper_mfc0_mvpcontrol (void) +target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) { return env->mvp->CP0_MVPControl; } -target_ulong helper_mfc0_mvpconf0 (void) +target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) { return env->mvp->CP0_MVPConf0; } -target_ulong helper_mfc0_mvpconf1 (void) +target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) { return env->mvp->CP0_MVPConf1; } -target_ulong helper_mfc0_random (void) +target_ulong helper_mfc0_random(CPUMIPSState *env) { return (int32_t)cpu_mips_get_random(env); } -target_ulong helper_mfc0_tcstatus (void) +target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) { return env->active_tc.CP0_TCStatus; } -target_ulong helper_mftc0_tcstatus(void) +target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCStatus; @@ -870,15 +908,15 @@ target_ulong helper_mftc0_tcstatus(void) return other->tcs[other_tc].CP0_TCStatus; } -target_ulong helper_mfc0_tcbind (void) +target_ulong helper_mfc0_tcbind(CPUMIPSState *env) { return env->active_tc.CP0_TCBind; } -target_ulong helper_mftc0_tcbind(void) +target_ulong helper_mftc0_tcbind(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCBind; @@ -886,15 +924,15 @@ target_ulong helper_mftc0_tcbind(void) return other->tcs[other_tc].CP0_TCBind; } -target_ulong helper_mfc0_tcrestart (void) +target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) { return env->active_tc.PC; } -target_ulong helper_mftc0_tcrestart(void) +target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.PC; @@ -902,15 +940,15 @@ target_ulong helper_mftc0_tcrestart(void) return other->tcs[other_tc].PC; } -target_ulong helper_mfc0_tchalt (void) +target_ulong helper_mfc0_tchalt(CPUMIPSState *env) { return env->active_tc.CP0_TCHalt; } -target_ulong helper_mftc0_tchalt(void) +target_ulong helper_mftc0_tchalt(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCHalt; @@ -918,15 +956,15 @@ target_ulong helper_mftc0_tchalt(void) return other->tcs[other_tc].CP0_TCHalt; } -target_ulong helper_mfc0_tccontext (void) +target_ulong helper_mfc0_tccontext(CPUMIPSState *env) { return env->active_tc.CP0_TCContext; } -target_ulong helper_mftc0_tccontext(void) +target_ulong helper_mftc0_tccontext(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCContext; @@ -934,15 +972,15 @@ target_ulong helper_mftc0_tccontext(void) return other->tcs[other_tc].CP0_TCContext; } -target_ulong helper_mfc0_tcschedule (void) +target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) { return env->active_tc.CP0_TCSchedule; } -target_ulong helper_mftc0_tcschedule(void) +target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCSchedule; @@ -950,15 +988,15 @@ target_ulong helper_mftc0_tcschedule(void) return other->tcs[other_tc].CP0_TCSchedule; } -target_ulong helper_mfc0_tcschefback (void) +target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) { return env->active_tc.CP0_TCScheFBack; } -target_ulong helper_mftc0_tcschefback(void) +target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.CP0_TCScheFBack; @@ -966,24 +1004,24 @@ target_ulong helper_mftc0_tcschefback(void) return other->tcs[other_tc].CP0_TCScheFBack; } -target_ulong helper_mfc0_count (void) +target_ulong helper_mfc0_count(CPUMIPSState *env) { return (int32_t)cpu_mips_get_count(env); } -target_ulong helper_mftc0_entryhi(void) +target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_EntryHi; } -target_ulong helper_mftc0_cause(void) +target_ulong helper_mftc0_cause(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int32_t tccause; - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) { tccause = other->CP0_Cause; @@ -994,30 +1032,30 @@ target_ulong helper_mftc0_cause(void) return tccause; } -target_ulong helper_mftc0_status(void) +target_ulong helper_mftc0_status(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_Status; } -target_ulong helper_mfc0_lladdr (void) +target_ulong helper_mfc0_lladdr(CPUMIPSState *env) { return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); } -target_ulong helper_mfc0_watchlo (uint32_t sel) +target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) { return (int32_t)env->CP0_WatchLo[sel]; } -target_ulong helper_mfc0_watchhi (uint32_t sel) +target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) { return env->CP0_WatchHi[sel]; } -target_ulong helper_mfc0_debug (void) +target_ulong helper_mfc0_debug(CPUMIPSState *env) { target_ulong t0 = env->CP0_Debug; if (env->hflags & MIPS_HFLAG_DM) @@ -1026,11 +1064,11 @@ target_ulong helper_mfc0_debug (void) return t0; } -target_ulong helper_mftc0_debug(void) +target_ulong helper_mftc0_debug(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int32_t tcstatus; - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) tcstatus = other->active_tc.CP0_Debug_tcstatus; @@ -1043,43 +1081,43 @@ target_ulong helper_mftc0_debug(void) } #if defined(TARGET_MIPS64) -target_ulong helper_dmfc0_tcrestart (void) +target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) { return env->active_tc.PC; } -target_ulong helper_dmfc0_tchalt (void) +target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) { return env->active_tc.CP0_TCHalt; } -target_ulong helper_dmfc0_tccontext (void) +target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) { return env->active_tc.CP0_TCContext; } -target_ulong helper_dmfc0_tcschedule (void) +target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) { return env->active_tc.CP0_TCSchedule; } -target_ulong helper_dmfc0_tcschefback (void) +target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) { return env->active_tc.CP0_TCScheFBack; } -target_ulong helper_dmfc0_lladdr (void) +target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) { return env->lladdr >> env->CP0_LLAddr_shift; } -target_ulong helper_dmfc0_watchlo (uint32_t sel) +target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) { return env->CP0_WatchLo[sel]; } #endif /* TARGET_MIPS64 */ -void helper_mtc0_index (target_ulong arg1) +void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) { int num = 1; unsigned int tmp = env->tlb->nb_tlb; @@ -1091,7 +1129,7 @@ void helper_mtc0_index (target_ulong arg1) env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); } -void helper_mtc0_mvpcontrol (target_ulong arg1) +void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = 0; uint32_t newval; @@ -1108,7 +1146,7 @@ void helper_mtc0_mvpcontrol (target_ulong arg1) env->mvp->CP0_MVPControl = newval; } -void helper_mtc0_vpecontrol (target_ulong arg1) +void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) { uint32_t mask; uint32_t newval; @@ -1125,10 +1163,10 @@ void helper_mtc0_vpecontrol (target_ulong arg1) env->CP0_VPEControl = newval; } -void helper_mttc0_vpecontrol(target_ulong arg1) +void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); uint32_t mask; uint32_t newval; @@ -1141,23 +1179,23 @@ void helper_mttc0_vpecontrol(target_ulong arg1) other->CP0_VPEControl = newval; } -target_ulong helper_mftc0_vpecontrol(void) +target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); /* FIXME: Mask away return zero on read bits. */ return other->CP0_VPEControl; } -target_ulong helper_mftc0_vpeconf0(void) +target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_VPEConf0; } -void helper_mtc0_vpeconf0 (target_ulong arg1) +void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = 0; uint32_t newval; @@ -1174,10 +1212,10 @@ void helper_mtc0_vpeconf0 (target_ulong arg1) env->CP0_VPEConf0 = newval; } -void helper_mttc0_vpeconf0(target_ulong arg1) +void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); uint32_t mask = 0; uint32_t newval; @@ -1188,7 +1226,7 @@ void helper_mttc0_vpeconf0(target_ulong arg1) other->CP0_VPEConf0 = newval; } -void helper_mtc0_vpeconf1 (target_ulong arg1) +void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = 0; uint32_t newval; @@ -1206,25 +1244,25 @@ void helper_mtc0_vpeconf1 (target_ulong arg1) env->CP0_VPEConf1 = newval; } -void helper_mtc0_yqmask (target_ulong arg1) +void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) { /* Yield qualifier inputs not implemented. */ env->CP0_YQMask = 0x00000000; } -void helper_mtc0_vpeopt (target_ulong arg1) +void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) { env->CP0_VPEOpt = arg1 & 0x0000ffff; } -void helper_mtc0_entrylo0 (target_ulong arg1) +void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) { /* Large physaddr (PABITS) not implemented */ /* 1k pages not implemented */ env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; } -void helper_mtc0_tcstatus (target_ulong arg1) +void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = env->CP0_TCStatus_rw_bitmask; uint32_t newval; @@ -1235,10 +1273,10 @@ void helper_mtc0_tcstatus (target_ulong arg1) sync_c0_tcstatus(env, env->current_tc, newval); } -void helper_mttc0_tcstatus (target_ulong arg1) +void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCStatus = arg1; @@ -1247,7 +1285,7 @@ void helper_mttc0_tcstatus (target_ulong arg1) sync_c0_tcstatus(other, other_tc, arg1); } -void helper_mtc0_tcbind (target_ulong arg1) +void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = (1 << CP0TCBd_TBE); uint32_t newval; @@ -1258,12 +1296,12 @@ void helper_mtc0_tcbind (target_ulong arg1) env->active_tc.CP0_TCBind = newval; } -void helper_mttc0_tcbind (target_ulong arg1) +void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); uint32_t mask = (1 << CP0TCBd_TBE); uint32_t newval; - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) mask |= (1 << CP0TCBd_CurVPE); @@ -1276,7 +1314,7 @@ void helper_mttc0_tcbind (target_ulong arg1) } } -void helper_mtc0_tcrestart (target_ulong arg1) +void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) { env->active_tc.PC = arg1; env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); @@ -1284,10 +1322,10 @@ void helper_mtc0_tcrestart (target_ulong arg1) /* MIPS16 not implemented. */ } -void helper_mttc0_tcrestart (target_ulong arg1) +void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) { other->active_tc.PC = arg1; @@ -1302,7 +1340,7 @@ void helper_mttc0_tcrestart (target_ulong arg1) } } -void helper_mtc0_tchalt (target_ulong arg1) +void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCHalt = arg1 & 0x1; @@ -1314,10 +1352,10 @@ void helper_mtc0_tchalt (target_ulong arg1) } } -void helper_mttc0_tchalt (target_ulong arg1) +void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); // TODO: Halt TC / Restart (if allocated+active) TC. @@ -1333,15 +1371,15 @@ void helper_mttc0_tchalt (target_ulong arg1) } } -void helper_mtc0_tccontext (target_ulong arg1) +void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCContext = arg1; } -void helper_mttc0_tccontext (target_ulong arg1) +void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCContext = arg1; @@ -1349,15 +1387,15 @@ void helper_mttc0_tccontext (target_ulong arg1) other->tcs[other_tc].CP0_TCContext = arg1; } -void helper_mtc0_tcschedule (target_ulong arg1) +void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCSchedule = arg1; } -void helper_mttc0_tcschedule (target_ulong arg1) +void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCSchedule = arg1; @@ -1365,15 +1403,15 @@ void helper_mttc0_tcschedule (target_ulong arg1) other->tcs[other_tc].CP0_TCSchedule = arg1; } -void helper_mtc0_tcschefback (target_ulong arg1) +void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) { env->active_tc.CP0_TCScheFBack = arg1; } -void helper_mttc0_tcschefback (target_ulong arg1) +void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.CP0_TCScheFBack = arg1; @@ -1381,25 +1419,25 @@ void helper_mttc0_tcschefback (target_ulong arg1) other->tcs[other_tc].CP0_TCScheFBack = arg1; } -void helper_mtc0_entrylo1 (target_ulong arg1) +void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) { /* Large physaddr (PABITS) not implemented */ /* 1k pages not implemented */ env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; } -void helper_mtc0_context (target_ulong arg1) +void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) { env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); } -void helper_mtc0_pagemask (target_ulong arg1) +void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) { /* 1k pages not implemented */ env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); } -void helper_mtc0_pagegrain (target_ulong arg1) +void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) { /* SmartMIPS not implemented */ /* Large physaddr (PABITS) not implemented */ @@ -1407,47 +1445,47 @@ void helper_mtc0_pagegrain (target_ulong arg1) env->CP0_PageGrain = 0; } -void helper_mtc0_wired (target_ulong arg1) +void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { env->CP0_Wired = arg1 % env->tlb->nb_tlb; } -void helper_mtc0_srsconf0 (target_ulong arg1) +void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; } -void helper_mtc0_srsconf1 (target_ulong arg1) +void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; } -void helper_mtc0_srsconf2 (target_ulong arg1) +void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; } -void helper_mtc0_srsconf3 (target_ulong arg1) +void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; } -void helper_mtc0_srsconf4 (target_ulong arg1) +void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) { env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; } -void helper_mtc0_hwrena (target_ulong arg1) +void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) { env->CP0_HWREna = arg1 & 0x0000000F; } -void helper_mtc0_count (target_ulong arg1) +void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) { cpu_mips_store_count(env, arg1); } -void helper_mtc0_entryhi (target_ulong arg1) +void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val; @@ -1466,21 +1504,21 @@ void helper_mtc0_entryhi (target_ulong arg1) cpu_mips_tlb_flush(env, 1); } -void helper_mttc0_entryhi(target_ulong arg1) +void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); other->CP0_EntryHi = arg1; sync_c0_entryhi(other, other_tc); } -void helper_mtc0_compare (target_ulong arg1) +void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) { cpu_mips_store_compare(env, arg1); } -void helper_mtc0_status (target_ulong arg1) +void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { uint32_t val, old; uint32_t mask = env->CP0_Status_rw_bitmask; @@ -1489,7 +1527,7 @@ void helper_mtc0_status (target_ulong arg1) old = env->CP0_Status; env->CP0_Status = (env->CP0_Status & ~mask) | val; if (env->CP0_Config3 & (1 << CP0C3_MT)) { - sync_c0_status(env, env->current_tc); + sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); } @@ -1508,22 +1546,22 @@ void helper_mtc0_status (target_ulong arg1) } } -void helper_mttc0_status(target_ulong arg1) +void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); other->CP0_Status = arg1 & ~0xf1000018; - sync_c0_status(other, other_tc); + sync_c0_status(env, other, other_tc); } -void helper_mtc0_intctl (target_ulong arg1) +void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) { /* vectored interrupts not implemented, no performance counters. */ env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); } -void helper_mtc0_srsctl (target_ulong arg1) +void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) { uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); @@ -1557,52 +1595,52 @@ static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) } } -void helper_mtc0_cause(target_ulong arg1) +void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) { mtc0_cause(env, arg1); } -void helper_mttc0_cause(target_ulong arg1) +void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); mtc0_cause(other, arg1); } -target_ulong helper_mftc0_epc(void) +target_ulong helper_mftc0_epc(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_EPC; } -target_ulong helper_mftc0_ebase(void) +target_ulong helper_mftc0_ebase(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); return other->CP0_EBase; } -void helper_mtc0_ebase (target_ulong arg1) +void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) { /* vectored interrupts not implemented */ env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); } -void helper_mttc0_ebase(target_ulong arg1) +void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); } -target_ulong helper_mftc0_configx(target_ulong idx) +target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); switch (idx) { case 0: return other->CP0_Config0; @@ -1618,49 +1656,49 @@ target_ulong helper_mftc0_configx(target_ulong idx) return 0; } -void helper_mtc0_config0 (target_ulong arg1) +void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) { env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); } -void helper_mtc0_config2 (target_ulong arg1) +void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) { /* tertiary/secondary caches not implemented */ env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); } -void helper_mtc0_lladdr (target_ulong arg1) +void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) { target_long mask = env->CP0_LLAddr_rw_bitmask; arg1 = arg1 << env->CP0_LLAddr_shift; env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); } -void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) +void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { /* Watch exceptions for instructions, data loads, data stores not implemented. */ env->CP0_WatchLo[sel] = (arg1 & ~0x7); } -void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel) +void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } -void helper_mtc0_xcontext (target_ulong arg1) +void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) { target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); } -void helper_mtc0_framemask (target_ulong arg1) +void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) { env->CP0_Framemask = arg1; /* XXX */ } -void helper_mtc0_debug (target_ulong arg1) +void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) { env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); if (arg1 & (1 << CP0DB_DM)) @@ -1669,11 +1707,11 @@ void helper_mtc0_debug (target_ulong arg1) env->hflags &= ~MIPS_HFLAG_DM; } -void helper_mttc0_debug(target_ulong arg1) +void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); /* XXX: Might be wrong, check with EJTAG spec. */ if (other_tc == other->current_tc) @@ -1685,36 +1723,36 @@ void helper_mttc0_debug(target_ulong arg1) (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); } -void helper_mtc0_performance0 (target_ulong arg1) +void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) { env->CP0_Performance0 = arg1 & 0x000007ff; } -void helper_mtc0_taglo (target_ulong arg1) +void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) { env->CP0_TagLo = arg1 & 0xFFFFFCF6; } -void helper_mtc0_datalo (target_ulong arg1) +void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) { env->CP0_DataLo = arg1; /* XXX */ } -void helper_mtc0_taghi (target_ulong arg1) +void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) { env->CP0_TagHi = arg1; /* XXX */ } -void helper_mtc0_datahi (target_ulong arg1) +void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) { env->CP0_DataHi = arg1; /* XXX */ } /* MIPS MT functions */ -target_ulong helper_mftgpr(uint32_t sel) +target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.gpr[sel]; @@ -1722,10 +1760,10 @@ target_ulong helper_mftgpr(uint32_t sel) return other->tcs[other_tc].gpr[sel]; } -target_ulong helper_mftlo(uint32_t sel) +target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.LO[sel]; @@ -1733,10 +1771,10 @@ target_ulong helper_mftlo(uint32_t sel) return other->tcs[other_tc].LO[sel]; } -target_ulong helper_mfthi(uint32_t sel) +target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.HI[sel]; @@ -1744,10 +1782,10 @@ target_ulong helper_mfthi(uint32_t sel) return other->tcs[other_tc].HI[sel]; } -target_ulong helper_mftacx(uint32_t sel) +target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.ACX[sel]; @@ -1755,10 +1793,10 @@ target_ulong helper_mftacx(uint32_t sel) return other->tcs[other_tc].ACX[sel]; } -target_ulong helper_mftdsp(void) +target_ulong helper_mftdsp(CPUMIPSState *env) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) return other->active_tc.DSPControl; @@ -1766,10 +1804,10 @@ target_ulong helper_mftdsp(void) return other->tcs[other_tc].DSPControl; } -void helper_mttgpr(target_ulong arg1, uint32_t sel) +void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.gpr[sel] = arg1; @@ -1777,10 +1815,10 @@ void helper_mttgpr(target_ulong arg1, uint32_t sel) other->tcs[other_tc].gpr[sel] = arg1; } -void helper_mttlo(target_ulong arg1, uint32_t sel) +void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.LO[sel] = arg1; @@ -1788,10 +1826,10 @@ void helper_mttlo(target_ulong arg1, uint32_t sel) other->tcs[other_tc].LO[sel] = arg1; } -void helper_mtthi(target_ulong arg1, uint32_t sel) +void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.HI[sel] = arg1; @@ -1799,10 +1837,10 @@ void helper_mtthi(target_ulong arg1, uint32_t sel) other->tcs[other_tc].HI[sel] = arg1; } -void helper_mttacx(target_ulong arg1, uint32_t sel) +void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.ACX[sel] = arg1; @@ -1810,10 +1848,10 @@ void helper_mttacx(target_ulong arg1, uint32_t sel) other->tcs[other_tc].ACX[sel] = arg1; } -void helper_mttdsp(target_ulong arg1) +void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other = mips_cpu_map_tc(&other_tc); + CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); if (other_tc == other->current_tc) other->active_tc.DSPControl = arg1; @@ -1834,7 +1872,7 @@ target_ulong helper_emt(void) return 0; } -target_ulong helper_dvpe(void) +target_ulong helper_dvpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; @@ -1850,7 +1888,7 @@ target_ulong helper_dvpe(void) return prev; } -target_ulong helper_evpe(void) +target_ulong helper_evpe(CPUMIPSState *env) { CPUMIPSState *other_cpu = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; @@ -1876,7 +1914,7 @@ void helper_fork(target_ulong arg1, target_ulong arg2) // TODO: store to TC register } -target_ulong helper_yield(target_ulong arg) +target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) { target_long arg1 = arg; @@ -1887,13 +1925,13 @@ target_ulong helper_yield(target_ulong arg) env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; - helper_raise_exception(EXCP_THREAD); + helper_raise_exception(env, EXCP_THREAD); } } } else if (arg1 == 0) { if (0 /* TODO: TC underflow */) { env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - helper_raise_exception(EXCP_THREAD); + helper_raise_exception(env, EXCP_THREAD); } else { // TODO: Deallocate TC } @@ -1901,7 +1939,7 @@ target_ulong helper_yield(target_ulong arg) /* Yield qualifier inputs not implemented. */ env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; - helper_raise_exception(EXCP_THREAD); + helper_raise_exception(env, EXCP_THREAD); } return env->CP0_YQMask; } @@ -1923,7 +1961,7 @@ static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) } } -static void r4k_fill_tlb (int idx) +static void r4k_fill_tlb(CPUMIPSState *env, int idx) { r4k_tlb_t *tlb; @@ -1946,7 +1984,7 @@ static void r4k_fill_tlb (int idx) tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; } -void r4k_helper_tlbwi (void) +void r4k_helper_tlbwi(CPUMIPSState *env) { int idx; @@ -1958,18 +1996,18 @@ void r4k_helper_tlbwi (void) r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(idx); + r4k_fill_tlb(env, idx); } -void r4k_helper_tlbwr (void) +void r4k_helper_tlbwr(CPUMIPSState *env) { int r = cpu_mips_get_random(env); r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(r); + r4k_fill_tlb(env, r); } -void r4k_helper_tlbp (void) +void r4k_helper_tlbp(CPUMIPSState *env) { r4k_tlb_t *tlb; target_ulong mask; @@ -2011,7 +2049,7 @@ void r4k_helper_tlbp (void) } } -void r4k_helper_tlbr (void) +void r4k_helper_tlbr(CPUMIPSState *env) { r4k_tlb_t *tlb; uint8_t ASID; @@ -2035,28 +2073,28 @@ void r4k_helper_tlbr (void) (tlb->C1 << 3) | (tlb->PFN[1] >> 6); } -void helper_tlbwi(void) +void helper_tlbwi(CPUMIPSState *env) { - env->tlb->helper_tlbwi(); + env->tlb->helper_tlbwi(env); } -void helper_tlbwr(void) +void helper_tlbwr(CPUMIPSState *env) { - env->tlb->helper_tlbwr(); + env->tlb->helper_tlbwr(env); } -void helper_tlbp(void) +void helper_tlbp(CPUMIPSState *env) { - env->tlb->helper_tlbp(); + env->tlb->helper_tlbp(env); } -void helper_tlbr(void) +void helper_tlbr(CPUMIPSState *env) { - env->tlb->helper_tlbr(); + env->tlb->helper_tlbr(env); } /* Specials */ -target_ulong helper_di (void) +target_ulong helper_di(CPUMIPSState *env) { target_ulong t0 = env->CP0_Status; @@ -2064,7 +2102,7 @@ target_ulong helper_di (void) return t0; } -target_ulong helper_ei (void) +target_ulong helper_ei(CPUMIPSState *env) { target_ulong t0 = env->CP0_Status; @@ -2072,7 +2110,7 @@ target_ulong helper_ei (void) return t0; } -static void debug_pre_eret (void) +static void debug_pre_eret(CPUMIPSState *env) { if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, @@ -2085,7 +2123,7 @@ static void debug_pre_eret (void) } } -static void debug_post_eret (void) +static void debug_post_eret(CPUMIPSState *env) { if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, @@ -2103,7 +2141,7 @@ static void debug_post_eret (void) } } -static void set_pc (target_ulong error_pc) +static void set_pc(CPUMIPSState *env, target_ulong error_pc) { env->active_tc.PC = error_pc & ~(target_ulong)1; if (error_pc & 1) { @@ -2113,78 +2151,78 @@ static void set_pc (target_ulong error_pc) } } -void helper_eret (void) +void helper_eret(CPUMIPSState *env) { - debug_pre_eret(); + debug_pre_eret(env); if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env->CP0_ErrorEPC); + set_pc(env, env->CP0_ErrorEPC); env->CP0_Status &= ~(1 << CP0St_ERL); } else { - set_pc(env->CP0_EPC); + set_pc(env, env->CP0_EPC); env->CP0_Status &= ~(1 << CP0St_EXL); } compute_hflags(env); - debug_post_eret(); + debug_post_eret(env); env->lladdr = 1; } -void helper_deret (void) +void helper_deret(CPUMIPSState *env) { - debug_pre_eret(); - set_pc(env->CP0_DEPC); + debug_pre_eret(env); + set_pc(env, env->CP0_DEPC); env->hflags &= MIPS_HFLAG_DM; compute_hflags(env); - debug_post_eret(); + debug_post_eret(env); env->lladdr = 1; } #endif /* !CONFIG_USER_ONLY */ -target_ulong helper_rdhwr_cpunum(void) +target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 0))) return env->CP0_EBase & 0x3ff; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -target_ulong helper_rdhwr_synci_step(void) +target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 1))) return env->SYNCI_Step; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -target_ulong helper_rdhwr_cc(void) +target_ulong helper_rdhwr_cc(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 2))) return env->CP0_Count; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -target_ulong helper_rdhwr_ccres(void) +target_ulong helper_rdhwr_ccres(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << 3))) return env->CCRes; else - helper_raise_exception(EXCP_RI); + helper_raise_exception(env, EXCP_RI); return 0; } -void helper_pmon (int function) +void helper_pmon(CPUMIPSState *env, int function) { function /= 2; switch (function) { @@ -2210,16 +2248,17 @@ void helper_pmon (int function) } } -void helper_wait (void) +void helper_wait(CPUMIPSState *env) { env->halted = 1; cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE); - helper_raise_exception(EXCP_HLT); + helper_raise_exception(env, EXCP_HLT); } #if !defined(CONFIG_USER_ONLY) -static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, +static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, + target_ulong addr, int is_write, int is_user, uintptr_t retaddr); #define MMUSUFFIX _mmu @@ -2237,23 +2276,20 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, #define SHIFT 3 #include "softmmu_template.h" -static void do_unaligned_access(target_ulong addr, int is_write, - int is_user, uintptr_t retaddr) +static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, + int is_write, int is_user, uintptr_t retaddr) { env->CP0_BadVAddr = addr; - do_restore_state (retaddr); - helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); + do_restore_state(env, retaddr); + helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL); } -void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx, +void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { TranslationBlock *tb; - CPUMIPSState *saved_env; int ret; - saved_env = env; - env = env1; ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); if (ret) { if (retaddr) { @@ -2265,20 +2301,17 @@ void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx, cpu_restore_state(tb, env, retaddr); } } - helper_raise_exception_err(env->exception_index, env->error_code); + helper_raise_exception_err(env, env->exception_index, env->error_code); } - env = saved_env; } -void cpu_unassigned_access(CPUMIPSState *env1, target_phys_addr_t addr, +void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr, int is_write, int is_exec, int unused, int size) { - env = env1; - if (is_exec) - helper_raise_exception(EXCP_IBE); + helper_raise_exception(env, EXCP_IBE); else - helper_raise_exception(EXCP_DBE); + helper_raise_exception(env, EXCP_DBE); } #endif /* !CONFIG_USER_ONLY */ @@ -2307,7 +2340,7 @@ static unsigned int ieee_rm[] = { #define RESTORE_FLUSH_MODE \ set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); -target_ulong helper_cfc1 (uint32_t reg) +target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1; @@ -2332,7 +2365,7 @@ target_ulong helper_cfc1 (uint32_t reg) return arg1; } -void helper_ctc1 (target_ulong arg1, uint32_t reg) +void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg) { switch(reg) { case 25: @@ -2366,7 +2399,7 @@ void helper_ctc1 (target_ulong arg1, uint32_t reg) RESTORE_FLUSH_MODE; set_float_exception_flags(0, &env->active_fpu.fp_status); if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) - helper_raise_exception(EXCP_FPE); + helper_raise_exception(env, EXCP_FPE); } static inline int ieee_ex_to_mips(int xcpt) @@ -2392,13 +2425,13 @@ static inline int ieee_ex_to_mips(int xcpt) return ret; } -static inline void update_fcr31(void) +static inline void update_fcr31(CPUMIPSState *env) { int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); SET_FP_CAUSE(env->active_fpu.fcr31, tmp); if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) - helper_raise_exception(EXCP_FPE); + helper_raise_exception(env, EXCP_FPE); else UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); } @@ -2409,71 +2442,71 @@ static inline void update_fcr31(void) paired single lower "pl", paired single upper "pu". */ /* unary operations, modifying fp status */ -uint64_t helper_float_sqrt_d(uint64_t fdt0) +uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) { return float64_sqrt(fdt0, &env->active_fpu.fp_status); } -uint32_t helper_float_sqrt_s(uint32_t fst0) +uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) { return float32_sqrt(fst0, &env->active_fpu.fp_status); } -uint64_t helper_float_cvtd_s(uint32_t fst0) +uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint64_t helper_float_cvtd_w(uint32_t wt0) +uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint64_t helper_float_cvtd_l(uint64_t dt0) +uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint64_t helper_float_cvtl_d(uint64_t fdt0) +uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_cvtl_s(uint32_t fst0) +uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_cvtps_pw(uint64_t dt0) +uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) { uint32_t fst2; uint32_t fsth2; @@ -2481,11 +2514,11 @@ uint64_t helper_float_cvtps_pw(uint64_t dt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_cvtpw_ps(uint64_t fdt0) +uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; uint32_t wth2; @@ -2493,7 +2526,7 @@ uint64_t helper_float_cvtpw_ps(uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { wt2 = FLOAT_SNAN32; wth2 = FLOAT_SNAN32; @@ -2501,81 +2534,81 @@ uint64_t helper_float_cvtpw_ps(uint64_t fdt0) return ((uint64_t)wth2 << 32) | wt2; } -uint32_t helper_float_cvts_d(uint64_t fdt0) +uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint32_t helper_float_cvts_w(uint32_t wt0) +uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint32_t helper_float_cvts_l(uint64_t dt0) +uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint32_t helper_float_cvts_pl(uint32_t wt0) +uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = wt0; - update_fcr31(); + update_fcr31(env); return wt2; } -uint32_t helper_float_cvts_pu(uint32_t wth0) +uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = wth0; - update_fcr31(); + update_fcr31(env); return wt2; } -uint32_t helper_float_cvtw_s(uint32_t fst0) +uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_cvtw_d(uint64_t fdt0) +uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_roundl_d(uint64_t fdt0) +uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; @@ -2583,13 +2616,13 @@ uint64_t helper_float_roundl_d(uint64_t fdt0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_roundl_s(uint32_t fst0) +uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; @@ -2597,13 +2630,13 @@ uint64_t helper_float_roundl_s(uint32_t fst0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_roundw_d(uint64_t fdt0) +uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; @@ -2611,13 +2644,13 @@ uint32_t helper_float_roundw_d(uint64_t fdt0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_roundw_s(uint32_t fst0) +uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; @@ -2625,61 +2658,61 @@ uint32_t helper_float_roundw_s(uint32_t fst0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_truncl_d(uint64_t fdt0) +uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_truncl_s(uint32_t fst0) +uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_truncw_d(uint64_t fdt0) +uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_truncw_s(uint32_t fst0) +uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_ceill_d(uint64_t fdt0) +uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; @@ -2687,13 +2720,13 @@ uint64_t helper_float_ceill_d(uint64_t fdt0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_ceill_s(uint32_t fst0) +uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; @@ -2701,13 +2734,13 @@ uint64_t helper_float_ceill_s(uint32_t fst0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_ceilw_d(uint64_t fdt0) +uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; @@ -2715,13 +2748,13 @@ uint32_t helper_float_ceilw_d(uint64_t fdt0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_ceilw_s(uint32_t fst0) +uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; @@ -2729,13 +2762,13 @@ uint32_t helper_float_ceilw_s(uint32_t fst0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint64_t helper_float_floorl_d(uint64_t fdt0) +uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; @@ -2743,13 +2776,13 @@ uint64_t helper_float_floorl_d(uint64_t fdt0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint64_t helper_float_floorl_s(uint32_t fst0) +uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; @@ -2757,13 +2790,13 @@ uint64_t helper_float_floorl_s(uint32_t fst0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) dt2 = FLOAT_SNAN64; return dt2; } -uint32_t helper_float_floorw_d(uint64_t fdt0) +uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; @@ -2771,13 +2804,13 @@ uint32_t helper_float_floorw_d(uint64_t fdt0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; } -uint32_t helper_float_floorw_s(uint32_t fst0) +uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; @@ -2785,7 +2818,7 @@ uint32_t helper_float_floorw_s(uint32_t fst0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(); + update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) wt2 = FLOAT_SNAN32; return wt2; @@ -2815,69 +2848,69 @@ FLOAT_UNOP(chs) #undef FLOAT_UNOP /* MIPS specific unary operations */ -uint64_t helper_float_recip_d(uint64_t fdt0) +uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_recip_s(uint32_t fst0) +uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_rsqrt_d(uint64_t fdt0) +uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_rsqrt_s(uint32_t fst0) +uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_recip1_d(uint64_t fdt0) +uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_recip1_s(uint32_t fst0) +uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_recip1_ps(uint64_t fdt0) +uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; uint32_t fsth2; @@ -2885,33 +2918,33 @@ uint64_t helper_float_recip1_ps(uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_rsqrt1_d(uint64_t fdt0) +uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_rsqrt1_s(uint32_t fst0) +uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) +uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; uint32_t fsth2; @@ -2921,39 +2954,43 @@ uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -#define FLOAT_OP(name, p) void helper_float_##name##_##p(void) +#define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env) /* binary operations */ #define FLOAT_BINOP(name) \ -uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ +uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1) \ { \ uint64_t dt2; \ \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ - update_fcr31(); \ + update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ dt2 = FLOAT_QNAN64; \ return dt2; \ } \ \ -uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ +uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ + uint32_t fst0, uint32_t fst1) \ { \ uint32_t wt2; \ \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ - update_fcr31(); \ + update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ wt2 = FLOAT_QNAN32; \ return wt2; \ } \ \ -uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ +uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1) \ { \ uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ uint32_t fsth0 = fdt0 >> 32; \ @@ -2965,7 +3002,7 @@ uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ - update_fcr31(); \ + update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ wt2 = FLOAT_QNAN32; \ wth2 = FLOAT_QNAN32; \ @@ -2981,22 +3018,28 @@ FLOAT_BINOP(div) /* ternary operations */ #define FLOAT_TERNOP(name1, name2) \ -uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ +uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ } \ \ -uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ - uint32_t fst2) \ +uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env, \ + uint32_t fst0, \ + uint32_t fst1, \ + uint32_t fst2) \ { \ fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ } \ \ -uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ +uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ uint32_t fsth0 = fdt0 >> 32; \ @@ -3018,24 +3061,30 @@ FLOAT_TERNOP(mul, sub) /* negated ternary operations */ #define FLOAT_NTERNOP(name1, name2) \ -uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ +uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ return float64_chs(fdt2); \ } \ \ -uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ - uint32_t fst2) \ +uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env, \ + uint32_t fst0, \ + uint32_t fst1, \ + uint32_t fst2) \ { \ fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ return float32_chs(fst2); \ } \ \ -uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ - uint64_t fdt2) \ +uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1, \ + uint64_t fdt2) \ { \ uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ uint32_t fsth0 = fdt0 >> 32; \ @@ -3058,25 +3107,25 @@ FLOAT_NTERNOP(mul, sub) #undef FLOAT_NTERNOP /* MIPS specific binary operations */ -uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) +uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3088,31 +3137,31 @@ uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fdt2; } -uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) +uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return fst2; } -uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) +uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3126,11 +3175,11 @@ uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) +uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3142,11 +3191,11 @@ uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } -uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) +uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) { uint32_t fst0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; @@ -3158,31 +3207,33 @@ uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(); + update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } /* compare operations */ #define FOP_COND_D(op, cond) \ -void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ CLEAR_FP_COND(cc, env->active_fpu); \ } \ -void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ fdt0 = float64_abs(fdt0); \ fdt1 = float64_abs(fdt1); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3211,25 +3262,27 @@ FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) #define FOP_COND_S(op, cond) \ -void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ CLEAR_FP_COND(cc, env->active_fpu); \ } \ -void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ +void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1, int cc) \ { \ int c; \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ fst0 = float32_abs(fst0); \ fst1 = float32_abs(fst1); \ c = cond; \ - update_fcr31(); \ + update_fcr31(env); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3258,7 +3311,8 @@ FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) #define FOP_COND_PS(op, condl, condh) \ -void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ uint32_t fst0, fsth0, fst1, fsth1; \ int ch, cl; \ @@ -3269,7 +3323,7 @@ void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ fsth1 = fdt1 >> 32; \ cl = condl; \ ch = condh; \ - update_fcr31(); \ + update_fcr31(env); \ if (cl) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3279,7 +3333,8 @@ void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ else \ CLEAR_FP_COND(cc + 1, env->active_fpu); \ } \ -void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ +void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ { \ uint32_t fst0, fsth0, fst1, fsth1; \ int ch, cl; \ @@ -3289,7 +3344,7 @@ void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ fsth1 = float32_abs(fdt1 >> 32); \ cl = condl; \ ch = condh; \ - update_fcr31(); \ + update_fcr31(env); \ if (cl) \ SET_FP_COND(cc, env->active_fpu); \ else \ |