diff options
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/cpu-qom.h | 2 | ||||
| -rw-r--r-- | target-mips/cpu.h | 8 | ||||
| -rw-r--r-- | target-mips/dsp_helper.c | 55 | ||||
| -rw-r--r-- | target-mips/helper.h | 4 | ||||
| -rw-r--r-- | target-mips/op_helper.c | 19 | ||||
| -rw-r--r-- | target-mips/translate.c | 7 |
6 files changed, 39 insertions, 56 deletions
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 6e2237123a..2a4b812402 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -20,7 +20,7 @@ #ifndef QEMU_MIPS_CPU_QOM_H #define QEMU_MIPS_CPU_QOM_H -#include "qemu/cpu.h" +#include "qom/cpu.h" #ifdef TARGET_MIPS64 #define TYPE_MIPS_CPU "mips64-cpu" diff --git a/target-mips/cpu.h b/target-mips/cpu.h index aebb2d5b79..31602ac8ed 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -12,8 +12,8 @@ #include "config.h" #include "qemu-common.h" #include "mips-defs.h" -#include "cpu-defs.h" -#include "softfloat.h" +#include "exec/cpu-defs.h" +#include "fpu/softfloat.h" struct CPUMIPSState; @@ -560,7 +560,7 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) return r; } -#include "cpu-all.h" +#include "exec/cpu-all.h" /* Memory access type : * may be needed for precise access rights control and precise exceptions. @@ -738,7 +738,7 @@ static inline bool cpu_has_work(CPUState *cpu) return has_work; } -#include "exec-all.h" +#include "exec/exec-all.h" static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb) { diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 14daf91950..a33e2bf9fd 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -2,7 +2,7 @@ * MIPS ASE DSP Instruction emulation helpers for QEMU. * * Copyright (c) 2012 Jia Liu <proljc@gmail.com> - * Dongxue Zhang <elat.era@gmail.com> + * Dongxue Zhang <elta.era@gmail.com> * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either @@ -484,35 +484,6 @@ static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b) return (temp >> 1) & 0x00FF; } -static inline int64_t mipsdsp_rashift_short_acc(int32_t ac, - int32_t shift, - CPUMIPSState *env) -{ - int32_t sign, temp31; - int64_t temp, acc; - - sign = (env->active_tc.HI[ac] >> 31) & 0x01; - acc = ((int64_t)env->active_tc.HI[ac] << 32) | - ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF); - if (shift == 0) { - temp = acc; - } else { - if (sign == 0) { - temp = (((int64_t)0x01 << (32 - shift + 1)) - 1) & (acc >> shift); - } else { - temp = ((((int64_t)0x01 << (shift + 1)) - 1) << (32 - shift)) | - (acc >> shift); - } - } - - temp31 = (temp >> 31) & 0x01; - if (sign != temp31) { - set_DSPControl_overflow_flag(1, 23, env); - } - - return temp; -} - /* 128 bits long. p[0] is LO, p[1] is HI. */ static inline void mipsdsp_rndrashift_short_acc(int64_t *p, int32_t ac, @@ -3407,7 +3378,7 @@ target_ulong helper_extr_w(target_ulong ac, target_ulong shift, int32_t tempI; int64_t tempDL[2]; - shift = shift & 0x0F; + shift = shift & 0x1F; mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env); if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && @@ -3435,7 +3406,7 @@ target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift, { int64_t tempDL[2]; - shift = shift & 0x0F; + shift = shift & 0x1F; mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env); if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && @@ -3462,7 +3433,7 @@ target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift, int32_t tempI, temp64; int64_t tempDL[2]; - shift = shift & 0x0F; + shift = shift & 0x1F; mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env); if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && @@ -3645,11 +3616,15 @@ target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift, CPUMIPSState *env) { - int64_t temp; + int64_t temp, acc; - shift = shift & 0x0F; + shift = shift & 0x1F; + + acc = ((int64_t)env->active_tc.HI[ac] << 32) | + ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF); + + temp = acc >> shift; - temp = mipsdsp_rashift_short_acc(ac, shift, env); if (temp > (int64_t)0x7FFF) { temp = 0x00007FFF; set_DSPControl_overflow_flag(1, 23, env); @@ -3948,7 +3923,11 @@ void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env) if (mask[4] == 1) { overwrite &= 0x00FFFFFF; newbits &= 0x00FFFFFF; +#if defined(TARGET_MIPS64) newbits |= 0xFF000000 & rs; +#else + newbits |= 0x0F000000 & rs; +#endif } if (mask[5] == 1) { @@ -3999,7 +3978,11 @@ target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env) } if (mask[4] == 1) { +#if defined(TARGET_MIPS64) temp |= dsp & 0xFF000000; +#else + temp |= dsp & 0x0F000000; +#endif } if (mask[5] == 1) { diff --git a/target-mips/helper.h b/target-mips/helper.h index acf9ebd759..9ea60ec1bb 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -1,4 +1,4 @@ -#include "def-helper.h" +#include "exec/def-helper.h" DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) @@ -707,4 +707,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) -#include "def-helper.h" +#include "exec/def-helper.h" diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 2972ae3f0a..d833d78b4f 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -18,12 +18,12 @@ */ #include <stdlib.h> #include "cpu.h" -#include "host-utils.h" +#include "qemu/host-utils.h" #include "helper.h" #if !defined(CONFIG_USER_ONLY) -#include "softmmu_exec.h" +#include "exec/softmmu_exec.h" #endif /* !defined(CONFIG_USER_ONLY) */ #ifndef CONFIG_USER_ONLY @@ -38,10 +38,9 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, int error_code, uintptr_t pc) { -#if 1 - if (exception < 0x100) + if (exception < EXCP_SC) { qemu_log("%s: %d %d\n", __func__, exception, error_code); -#endif + } env->exception_index = exception; env->error_code = error_code; @@ -2116,16 +2115,16 @@ static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, #define ALIGNED_ONLY #define SHIFT 0 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #define SHIFT 1 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #define SHIFT 2 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #define SHIFT 3 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) @@ -2175,7 +2174,7 @@ static unsigned int ieee_rm[] = { set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) #define RESTORE_FLUSH_MODE \ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); + set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status) target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { diff --git a/target-mips/translate.c b/target-mips/translate.c index 65e6725cc9..6281e70471 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -22,7 +22,7 @@ */ #include "cpu.h" -#include "disas.h" +#include "disas/disas.h" #include "tcg-op.h" #include "helper.h" @@ -1017,7 +1017,7 @@ static TCGv_i64 fpu_f64[32]; static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; static target_ulong gen_opc_btarget[OPC_BUF_SIZE]; -#include "gen-icount.h" +#include "exec/gen-icount.h" #define gen_helper_0e0i(name, arg) do { \ TCGv_i32 helper_tmp = tcg_const_i32(arg); \ @@ -13769,9 +13769,10 @@ static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx, check_dsp(ctx); { imm = (ctx->opcode >> 16) & 0x03FF; + imm = (int16_t)(imm << 6) >> 6; tcg_gen_movi_tl(cpu_gpr[ret], \ (target_long)((int32_t)imm << 16 | \ - (uint32_t)(uint16_t)imm)); + (uint16_t)imm)); } break; case OPC_REPLV_PH: |