diff options
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 6 | ||||
| -rw-r--r-- | target-ppc/helper.c | 8 | ||||
| -rw-r--r-- | target-ppc/kvm.c | 2 | ||||
| -rw-r--r-- | target-ppc/kvm_ppc.c | 2 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 24 |
5 files changed, 21 insertions, 21 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index ca6f1cb58c..e7fb3641a7 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -233,10 +233,10 @@ enum { POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ /* EOL */ POWERPC_EXCP_NB = 96, - /* Qemu exceptions: used internally during code translation */ + /* QEMU exceptions: used internally during code translation */ POWERPC_EXCP_STOP = 0x200, /* stop translation */ POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ - /* Qemu exceptions: special cases we want to stop translation */ + /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ @@ -1041,7 +1041,7 @@ struct CPUPPCState { /* opcode handlers */ opc_handler_t *opcodes[0x40]; - /* Those resources are used only in Qemu core */ + /* Those resources are used only in QEMU core */ target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ int mmu_idx; /* precomputed MMU index to speed up mem accesses */ diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 39dcc273e5..e13b74993d 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -365,7 +365,7 @@ void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code, tlb = &env->tlb.tlb6[nr]; LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1); - /* Invalidate any pending reference in Qemu for this virtual address */ + /* Invalidate any pending reference in QEMU for this virtual address */ __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); tlb->pte0 = pte0; tlb->pte1 = pte1; @@ -729,7 +729,7 @@ void ppc_slb_invalidate_all (CPUPPCState *env) slb->esid &= ~SLB_ESID_V; /* XXX: given the fact that segment size is 256 MB or 1TB, * and we still don't have a tlb_flush_mask(env, n, mask) - * in Qemu, we just invalidate all TLBs + * in QEMU, we just invalidate all TLBs */ do_invalidate = 1; } @@ -752,7 +752,7 @@ void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) /* XXX: given the fact that segment size is 256 MB or 1TB, * and we still don't have a tlb_flush_mask(env, n, mask) - * in Qemu, we just invalidate all TLBs + * in QEMU, we just invalidate all TLBs */ tlb_flush(env, 1); } @@ -2319,7 +2319,7 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr) case POWERPC_MMU_2_06: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, - * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu, + * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * we just invalidate all TLBs */ tlb_flush(env, 1); diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 724f4c7815..d929213a04 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -470,7 +470,7 @@ void kvm_arch_pre_run(CPUPPCState *env, struct kvm_run *run) int r; unsigned irq; - /* PowerPC Qemu tracks the various core input pins (interrupt, critical + /* PowerPC QEMU tracks the various core input pins (interrupt, critical * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ if (!cap_interrupt_level && run->ready_for_interrupt_injection && diff --git a/target-ppc/kvm_ppc.c b/target-ppc/kvm_ppc.c index 24fc6bce3b..a2e49cd423 100644 --- a/target-ppc/kvm_ppc.c +++ b/target-ppc/kvm_ppc.c @@ -31,7 +31,7 @@ void kvmppc_init(void) { /* XXX The only reason KVM yields control back to qemu is device IO. Since * an idle guest does no IO, qemu's device model will never get a chance to - * run. So, until Qemu gains IO threads, we create this timer to ensure + * run. So, until QEMU gains IO threads, we create this timer to ensure * that the device model gets a chance to run. */ kvmppc_timer_rate = get_ticks_per_sec() / 10; kvmppc_timer = qemu_new_timer_ns(vm_clock, &kvmppc_timer_hack, NULL); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 367eefaf9e..b1f87854a0 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -1796,17 +1796,17 @@ static void gen_spr_440 (CPUPPCState *env) static void gen_spr_40x (CPUPPCState *env) { /* Cache */ - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_40x_DCCR, "DCCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_40x_ICCR, "ICCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, @@ -1974,7 +1974,7 @@ static void gen_spr_401_403 (CPUPPCState *env) SPR_NOACCESS, &spr_write_tbu, 0x00000000); /* Debug */ - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_403_CDBCR, "CDBCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -2012,12 +2012,12 @@ static void gen_spr_401 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_40x_sler, 0x00000000); - /* not emulated, as Qemu never does speculative access */ + /* not emulated, as QEMU never does speculative access */ spr_register(env, SPR_40x_SGR, "SGR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0xFFFFFFFF); - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_40x_DCWR, "DCWR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -3436,12 +3436,12 @@ static void init_proc_403GCX (CPUPPCState *env) gen_spr_403_real(env); gen_spr_403_mmu(env); /* Bus access control */ - /* not emulated, as Qemu never does speculative access */ + /* not emulated, as QEMU never does speculative access */ spr_register(env, SPR_40x_SGR, "SGR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0xFFFFFFFF); - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_40x_DCWR, "DCWR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -3488,12 +3488,12 @@ static void init_proc_405 (CPUPPCState *env) gen_spr_40x(env); gen_spr_405(env); /* Bus access control */ - /* not emulated, as Qemu never does speculative access */ + /* not emulated, as QEMU never does speculative access */ spr_register(env, SPR_40x_SGR, "SGR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0xFFFFFFFF); - /* not emulated, as Qemu do not emulate caches */ + /* not emulated, as QEMU do not emulate caches */ spr_register(env, SPR_40x_DCWR, "DCWR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -9442,13 +9442,13 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def) } if (env->irq_inputs == NULL) { fprintf(stderr, "WARNING: no internal IRQ controller registered.\n" - " Attempt Qemu to crash very soon !\n"); + " Attempt QEMU to crash very soon !\n"); } #endif if (env->check_pow == NULL) { fprintf(stderr, "WARNING: no power management check handler " "registered.\n" - " Attempt Qemu to crash very soon !\n"); + " Attempt QEMU to crash very soon !\n"); } } |