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-rw-r--r--target-ppc/excp_helper.c4
-rw-r--r--target-ppc/kvm.c2
-rw-r--r--target-ppc/mmu-hash32.h12
-rw-r--r--target-ppc/mmu-hash64.h14
4 files changed, 22 insertions, 10 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 26c57d9a34..d541929743 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -180,12 +180,14 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
         msr |= env->error_code;
         goto store_next;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
+        cs = CPU(cpu);
+
         if (lpes0 == 1) {
             new_msr |= (target_ulong)MSR_HVB;
         }
         if (env->mpic_proxy) {
             /* IACK the IRQ on delivery */
-            env->spr[SPR_BOOKE_EPR] = ldl_phys(env->mpic_iack);
+            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
         }
         goto store_next;
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 781b72f1ea..7af3fe277d 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1228,7 +1228,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 #endif
     case KVM_EXIT_EPR:
         DPRINTF("handle epr\n");
-        run->epr.epr = ldl_phys(env->mpic_iack);
+        run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
         ret = 0;
         break;
     case KVM_EXIT_WATCHDOG:
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 884786b97a..4671141a32 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -68,29 +68,33 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
 static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env,
                                                  hwaddr pte_offset)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     assert(!env->external_htab); /* Not supported on 32-bit for now */
-    return ldl_phys(env->htab_base + pte_offset);
+    return ldl_phys(cs->as, env->htab_base + pte_offset);
 }
 
 static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env,
                                                  hwaddr pte_offset)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     assert(!env->external_htab); /* Not supported on 32-bit for now */
-    return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
+    return ldl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2);
 }
 
 static inline void ppc_hash32_store_hpte0(CPUPPCState *env,
                                           hwaddr pte_offset, target_ulong pte0)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     assert(!env->external_htab); /* Not supported on 32-bit for now */
-    stl_phys(env->htab_base + pte_offset, pte0);
+    stl_phys(cs->as, env->htab_base + pte_offset, pte0);
 }
 
 static inline void ppc_hash32_store_hpte1(CPUPPCState *env,
                                           hwaddr pte_offset, target_ulong pte1)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     assert(!env->external_htab); /* Not supported on 32-bit for now */
-    stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
+    stl_phys(cs->as, env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1);
 }
 
 typedef struct {
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 55f5a230fd..a8da558ca2 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -78,40 +78,46 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
 static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
                                                  hwaddr pte_offset)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     if (env->external_htab) {
         return  ldq_p(env->external_htab + pte_offset);
     } else {
-        return ldq_phys(env->htab_base + pte_offset);
+        return ldq_phys(cs->as, env->htab_base + pte_offset);
     }
 }
 
 static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
                                                  hwaddr pte_offset)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     if (env->external_htab) {
         return ldq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2);
     } else {
-        return ldq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
+        return ldq_phys(cs->as,
+                        env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
     }
 }
 
 static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
                                           hwaddr pte_offset, target_ulong pte0)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     if (env->external_htab) {
         stq_p(env->external_htab + pte_offset, pte0);
     } else {
-        stq_phys(env->htab_base + pte_offset, pte0);
+        stq_phys(cs->as, env->htab_base + pte_offset, pte0);
     }
 }
 
 static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
                                           hwaddr pte_offset, target_ulong pte1)
 {
+    CPUState *cs = ENV_GET_CPU(env);
     if (env->external_htab) {
         stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
     } else {
-        stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
+        stq_phys(cs->as,
+                 env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
     }
 }