diff options
Diffstat (limited to 'target-sh4/translate.c')
| -rw-r--r-- | target-sh4/translate.c | 327 |
1 files changed, 157 insertions, 170 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 41aa928321..28259f9e14 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -18,7 +18,6 @@ */ #define DEBUG_DISAS -//#define SH4_SINGLE_STEP #include "cpu.h" #include "disas/disas.h" @@ -47,7 +46,7 @@ typedef struct DisasContext { #if defined(CONFIG_USER_ONLY) #define IS_USER(ctx) 1 #else -#define IS_USER(ctx) (!(ctx->flags & SR_MD)) +#define IS_USER(ctx) (!(ctx->flags & (1u << SR_MD))) #endif enum { @@ -62,7 +61,8 @@ enum { /* global register indexes */ static TCGv_ptr cpu_env; static TCGv cpu_gregs[24]; -static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; +static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; +static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; static TCGv cpu_fregs[32]; @@ -110,6 +110,12 @@ void sh4_translate_init(void) offsetof(CPUSH4State, pc), "PC"); cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSH4State, sr), "SR"); + cpu_sr_m = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUSH4State, sr_m), "SR_M"); + cpu_sr_q = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUSH4State, sr_q), "SR_Q"); + cpu_sr_t = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUSH4State, sr_t), "SR_T"); cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUSH4State, ssr), "SSR"); cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, @@ -156,7 +162,7 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, CPUSH4State *env = &cpu->env; int i; cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", - env->pc, env->sr, env->pr, env->fpscr); + env->pc, cpu_read_sr(env), env->pr, env->fpscr); cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", env->spc, env->ssr, env->gbr, env->vbr); cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", @@ -175,6 +181,30 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, } } +static void gen_read_sr(TCGv dst) +{ + TCGv t0 = tcg_temp_new(); + tcg_gen_shli_i32(t0, cpu_sr_q, SR_Q); + tcg_gen_or_i32(dst, dst, t0); + tcg_gen_shli_i32(t0, cpu_sr_m, SR_M); + tcg_gen_or_i32(dst, dst, t0); + tcg_gen_shli_i32(t0, cpu_sr_t, SR_T); + tcg_gen_or_i32(dst, cpu_sr, t0); + tcg_temp_free_i32(t0); +} + +static void gen_write_sr(TCGv src) +{ + tcg_gen_andi_i32(cpu_sr, src, + ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); + tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); + tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); + tcg_gen_shri_i32(cpu_sr_m, src, SR_M); + tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); + tcg_gen_shri_i32(cpu_sr_t, src, SR_T); + tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); +} + static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) { TranslationBlock *tb; @@ -210,12 +240,9 @@ static void gen_jump(DisasContext * ctx) static inline void gen_branch_slot(uint32_t delayed_pc, int t) { - TCGv sr; TCGLabel *label = gen_new_label(); tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); - sr = tcg_temp_new(); - tcg_gen_andi_i32(sr, cpu_sr, SR_T); - tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label); + tcg_gen_brcondi_i32(t ? TCG_COND_EQ : TCG_COND_NE, cpu_sr_t, 0, label); tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); gen_set_label(label); } @@ -224,13 +251,8 @@ static inline void gen_branch_slot(uint32_t delayed_pc, int t) static void gen_conditional_jump(DisasContext * ctx, target_ulong ift, target_ulong ifnott) { - TCGLabel *l1; - TCGv sr; - - l1 = gen_new_label(); - sr = tcg_temp_new(); - tcg_gen_andi_i32(sr, cpu_sr, SR_T); - tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1); + TCGLabel *l1 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_sr_t, 0, l1); gen_goto_tb(ctx, 0, ifnott); gen_set_label(l1); gen_goto_tb(ctx, 1, ift); @@ -252,54 +274,12 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) gen_jump(ctx); } -static inline void gen_cmp(int cond, TCGv t0, TCGv t1) -{ - TCGv t; - - t = tcg_temp_new(); - tcg_gen_setcond_i32(cond, t, t1, t0); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, t); - - tcg_temp_free(t); -} - -static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) -{ - TCGv t; - - t = tcg_temp_new(); - tcg_gen_setcondi_i32(cond, t, t0, imm); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, t); - - tcg_temp_free(t); -} - static inline void gen_store_flags(uint32_t flags) { tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); } -static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) -{ - TCGv tmp = tcg_temp_new(); - - p0 &= 0x1f; - p1 &= 0x1f; - - tcg_gen_andi_i32(tmp, t1, (1 << p1)); - tcg_gen_andi_i32(t0, t0, ~(1 << p0)); - if (p0 < p1) - tcg_gen_shri_i32(tmp, tmp, p1 - p0); - else if (p0 > p1) - tcg_gen_shli_i32(tmp, tmp, p0 - p1); - tcg_gen_or_i32(t0, t0, tmp); - - tcg_temp_free(tmp); -} - static inline void gen_load_fpr64(TCGv_i64 t, int reg) { tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); @@ -326,10 +306,12 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) #define B11_8 ((ctx->opcode >> 8) & 0xf) #define B15_12 ((ctx->opcode >> 12) & 0xf) -#define REG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) == (SR_MD | SR_RB) \ +#define REG(x) ((x) < 8 && (ctx->flags & (1u << SR_MD))\ + && (ctx->flags & (1u << SR_RB))\ ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) -#define ALTREG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) != (SR_MD | SR_RB)\ +#define ALTREG(x) ((x) < 8 && (!(ctx->flags & (1u << SR_MD))\ + || !(ctx->flags & (1u << SR_RB)))\ ? (cpu_gregs[x + 16]) : (cpu_gregs[x])) #define FREG(x) (ctx->flags & FPSCR_FR ? (x) ^ 0x10 : (x)) @@ -359,7 +341,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) } #define CHECK_FPU_ENABLED \ - if (ctx->flags & SR_FD) { \ + if (ctx->flags & (1u << SR_FD)) { \ tcg_gen_movi_i32(cpu_pc, ctx->pc); \ if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \ gen_helper_raise_slot_fpu_disable(cpu_env); \ @@ -409,7 +391,9 @@ static void _decode_opc(DisasContext * ctx) switch (ctx->opcode) { case 0x0019: /* div0u */ - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); + tcg_gen_movi_i32(cpu_sr_m, 0); + tcg_gen_movi_i32(cpu_sr_q, 0); + tcg_gen_movi_i32(cpu_sr_t, 0); return; case 0x000b: /* rts */ CHECK_NOT_DELAY_SLOT @@ -422,10 +406,10 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_movi_i32(cpu_macl, 0); return; case 0x0048: /* clrs */ - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_S)); return; case 0x0008: /* clrt */ - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); + tcg_gen_movi_i32(cpu_sr_t, 0); return; case 0x0038: /* ldtlb */ CHECK_PRIVILEGED @@ -434,16 +418,16 @@ static void _decode_opc(DisasContext * ctx) case 0x002b: /* rte */ CHECK_PRIVILEGED CHECK_NOT_DELAY_SLOT - tcg_gen_mov_i32(cpu_sr, cpu_ssr); + gen_write_sr(cpu_ssr); tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); ctx->flags |= DELAY_SLOT; ctx->delayed_pc = (uint32_t) - 1; return; case 0x0058: /* sets */ - tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); + tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); return; case 0x0018: /* sett */ - tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); + tcg_gen_movi_i32(cpu_sr_t, 1); return; case 0xfbfd: /* frchg */ tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); @@ -659,22 +643,14 @@ static void _decode_opc(DisasContext * ctx) return; case 0x300e: /* addc Rm,Rn */ { - TCGv t0, t1, t2; - t0 = tcg_temp_new(); - tcg_gen_andi_i32(t0, cpu_sr, SR_T); + TCGv t0, t1; + t0 = tcg_const_tl(0); t1 = tcg_temp_new(); - tcg_gen_add_i32(t1, REG(B7_4), REG(B11_8)); - tcg_gen_add_i32(t0, t0, t1); - t2 = tcg_temp_new(); - tcg_gen_setcond_i32(TCG_COND_GTU, t2, REG(B11_8), t1); - tcg_gen_setcond_i32(TCG_COND_GTU, t1, t1, t0); - tcg_gen_or_i32(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); - tcg_temp_free(t1); - tcg_gen_mov_i32(REG(B11_8), t0); + tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); + tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, + REG(B11_8), t0, t1, cpu_sr_t); tcg_temp_free(t0); + tcg_temp_free(t1); } return; case 0x300f: /* addv Rm,Rn */ @@ -686,11 +662,9 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_xor_i32(t1, t0, REG(B11_8)); t2 = tcg_temp_new(); tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8)); - tcg_gen_andc_i32(t1, t1, t2); + tcg_gen_andc_i32(cpu_sr_t, t1, t2); tcg_temp_free(t2); - tcg_gen_shri_i32(t1, t1, 31); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31); tcg_temp_free(t1); tcg_gen_mov_i32(REG(B7_4), t0); tcg_temp_free(t0); @@ -700,54 +674,79 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); return; case 0x3000: /* cmp/eq Rm,Rn */ - gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3003: /* cmp/ge Rm,Rn */ - gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3007: /* cmp/gt Rm,Rn */ - gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3006: /* cmp/hi Rm,Rn */ - gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x3002: /* cmp/hs Rm,Rn */ - gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4)); return; case 0x200c: /* cmp/str Rm,Rn */ { TCGv cmp1 = tcg_temp_new(); TCGv cmp2 = tcg_temp_new(); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); tcg_gen_andi_i32(cmp2, cmp1, 0xff000000); - tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cmp2, 0); tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000); tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2); tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00); tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2); tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff); tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); + tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2); tcg_temp_free(cmp2); tcg_temp_free(cmp1); } return; case 0x2007: /* div0s Rm,Rn */ - { - gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ - gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ - TCGv val = tcg_temp_new(); - tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); - gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ - tcg_temp_free(val); - } + tcg_gen_shri_i32(cpu_sr_q, REG(B11_8), 31); /* SR_Q */ + tcg_gen_shri_i32(cpu_sr_m, REG(B7_4), 31); /* SR_M */ + tcg_gen_xor_i32(cpu_sr_t, cpu_sr_q, cpu_sr_m); /* SR_T */ return; case 0x3004: /* div1 Rm,Rn */ - gen_helper_div1(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8)); + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGv zero = tcg_const_i32(0); + + /* shift left arg1, saving the bit being pushed out and inserting + T on the right */ + tcg_gen_shri_i32(t0, REG(B11_8), 31); + tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); + tcg_gen_or_i32(REG(B11_8), REG(B11_8), cpu_sr_t); + + /* Add or subtract arg0 from arg1 depending if Q == M. To avoid + using 64-bit temps, we compute arg0's high part from q ^ m, so + that it is 0x00000000 when adding the value or 0xffffffff when + subtracting it. */ + tcg_gen_xor_i32(t1, cpu_sr_q, cpu_sr_m); + tcg_gen_subi_i32(t1, t1, 1); + tcg_gen_neg_i32(t2, REG(B7_4)); + tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, zero, REG(B7_4), t2); + tcg_gen_add2_i32(REG(B11_8), t1, REG(B11_8), zero, t2, t1); + + /* compute T and Q depending on carry */ + tcg_gen_andi_i32(t1, t1, 1); + tcg_gen_xor_i32(t1, t1, t0); + tcg_gen_xori_i32(cpu_sr_t, t1, 1); + tcg_gen_xor_i32(cpu_sr_q, cpu_sr_m, t1); + + tcg_temp_free(zero); + tcg_temp_free(t2); + tcg_temp_free(t1); + tcg_temp_free(t0); + } return; case 0x300d: /* dmuls.l Rm,Rn */ tcg_gen_muls2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8)); @@ -827,19 +826,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0x600a: /* negc Rm,Rn */ { - TCGv t0, t1; - t0 = tcg_temp_new(); - tcg_gen_neg_i32(t0, REG(B7_4)); - t1 = tcg_temp_new(); - tcg_gen_andi_i32(t1, cpu_sr, SR_T); - tcg_gen_sub_i32(REG(B11_8), t0, t1); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_setcondi_i32(TCG_COND_GTU, t1, t0, 0); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); - tcg_gen_setcond_i32(TCG_COND_GTU, t1, REG(B11_8), t0); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + TCGv t0 = tcg_const_i32(0); + tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, + REG(B7_4), t0, cpu_sr_t, t0); + tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, + t0, t0, REG(B11_8), cpu_sr_t); + tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); tcg_temp_free(t0); - tcg_temp_free(t1); } return; case 0x6007: /* not Rm,Rn */ @@ -918,22 +911,15 @@ static void _decode_opc(DisasContext * ctx) return; case 0x300a: /* subc Rm,Rn */ { - TCGv t0, t1, t2; - t0 = tcg_temp_new(); - tcg_gen_andi_i32(t0, cpu_sr, SR_T); + TCGv t0, t1; + t0 = tcg_const_tl(0); t1 = tcg_temp_new(); - tcg_gen_sub_i32(t1, REG(B11_8), REG(B7_4)); - tcg_gen_sub_i32(t0, t1, t0); - t2 = tcg_temp_new(); - tcg_gen_setcond_i32(TCG_COND_LTU, t2, REG(B11_8), t1); - tcg_gen_setcond_i32(TCG_COND_LTU, t1, t1, t0); - tcg_gen_or_i32(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); - tcg_temp_free(t1); - tcg_gen_mov_i32(REG(B11_8), t0); + tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); + tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, + REG(B11_8), t0, t1, cpu_sr_t); + tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); tcg_temp_free(t0); + tcg_temp_free(t1); } return; case 0x300b: /* subv Rm,Rn */ @@ -947,9 +933,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4)); tcg_gen_and_i32(t1, t1, t2); tcg_temp_free(t2); - tcg_gen_shri_i32(t1, t1, 31); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_gen_shri_i32(cpu_sr_t, t1, 31); tcg_temp_free(t1); tcg_gen_mov_i32(REG(B11_8), t0); tcg_temp_free(t0); @@ -959,7 +943,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv val = tcg_temp_new(); tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_temp_free(val); } return; @@ -1025,24 +1009,19 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED + TCGv addr = tcg_temp_new_i32(); + tcg_gen_subi_i32(addr, REG(B11_8), 4); if (ctx->flags & FPSCR_SZ) { - TCGv addr = tcg_temp_new_i32(); int fr = XREG(B7_4); - tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL); tcg_gen_subi_i32(addr, addr, 4); tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL); - tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); } else { - TCGv addr; - addr = tcg_temp_new_i32(); - tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx, MO_TEUL); - tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); } + tcg_gen_mov_i32(REG(B11_8), addr); + tcg_temp_free(addr); return; case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ CHECK_FPU_ENABLED @@ -1210,7 +1189,7 @@ static void _decode_opc(DisasContext * ctx) ctx->flags |= DELAY_SLOT_CONDITIONAL; return; case 0x8800: /* cmp/eq #imm,R0 */ - gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); return; case 0xc400: /* mov.b @(disp,GBR),R0 */ { @@ -1326,7 +1305,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv val = tcg_temp_new(); tcg_gen_andi_i32(val, REG(0), B7_0); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_temp_free(val); } return; @@ -1336,7 +1315,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(val, REG(0), cpu_gbr); tcg_gen_qemu_ld_i32(val, val, ctx->memidx, MO_UB); tcg_gen_andi_i32(val, val, B7_0); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_temp_free(val); } return; @@ -1399,14 +1378,14 @@ static void _decode_opc(DisasContext * ctx) ctx->delayed_pc = (uint32_t) - 1; return; case 0x4015: /* cmp/pl Rn */ - gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0); + tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); return; case 0x4011: /* cmp/pz Rn */ - gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0); + tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); return; case 0x4010: /* dt Rn */ tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); - gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); return; case 0x402b: /* jmp @Rn */ CHECK_NOT_DELAY_SLOT @@ -1423,15 +1402,21 @@ static void _decode_opc(DisasContext * ctx) return; case 0x400e: /* ldc Rm,SR */ CHECK_PRIVILEGED - tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3); - ctx->bstate = BS_STOP; + { + TCGv val = tcg_temp_new(); + tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); + gen_write_sr(val); + tcg_temp_free(val); + ctx->bstate = BS_STOP; + } return; case 0x4007: /* ldc.l @Rm+,SR */ CHECK_PRIVILEGED { TCGv val = tcg_temp_new(); tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL); - tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); + tcg_gen_andi_i32(val, val, 0x700083f3); + gen_write_sr(val); tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); ctx->bstate = BS_STOP; @@ -1439,15 +1424,18 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0002: /* stc SR,Rn */ CHECK_PRIVILEGED - tcg_gen_mov_i32(REG(B11_8), cpu_sr); + gen_read_sr(REG(B11_8)); return; case 0x4003: /* stc SR,@-Rn */ CHECK_PRIVILEGED { TCGv addr = tcg_temp_new(); + TCGv val = tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(cpu_sr, addr, ctx->memidx, MO_TEUL); + gen_read_sr(val); + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL); tcg_gen_mov_i32(REG(B11_8), addr); + tcg_temp_free(val); tcg_temp_free(addr); } return; @@ -1545,7 +1533,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); return; case 0x0029: /* movt Rn */ - tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); + tcg_gen_mov_i32(REG(B11_8), cpu_sr_t); return; case 0x0073: /* MOVCO.L @@ -1555,8 +1543,7 @@ static void _decode_opc(DisasContext * ctx) */ if (ctx->features & SH_FEATURE_SH4A) { TCGLabel *label = gen_new_label(); - tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); - tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst); + tcg_gen_mov_i32(cpu_sr_t, cpu_ldst); tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); gen_set_label(label); @@ -1609,42 +1596,42 @@ static void _decode_opc(DisasContext * ctx) case 0x4024: /* rotcl Rn */ { TCGv tmp = tcg_temp_new(); - tcg_gen_mov_i32(tmp, cpu_sr); - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); + tcg_gen_mov_i32(tmp, cpu_sr_t); + tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); - gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); + tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); tcg_temp_free(tmp); } return; case 0x4025: /* rotcr Rn */ { TCGv tmp = tcg_temp_new(); - tcg_gen_mov_i32(tmp, cpu_sr); - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); + tcg_gen_shli_i32(tmp, cpu_sr_t, 31); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); - gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); + tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); tcg_temp_free(tmp); } return; case 0x4004: /* rotl Rn */ tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1); - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); return; case 0x4005: /* rotr Rn */ - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4000: /* shll Rn */ case 0x4020: /* shal Rn */ - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); + tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4021: /* shar Rn */ - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4001: /* shlr Rn */ - gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); + tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); return; case 0x4008: /* shll2 Rn */ @@ -1672,7 +1659,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(addr, REG(B11_8)); val = tcg_temp_local_new(); tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); - gen_cmp_imm(TCG_COND_EQ, val, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); tcg_gen_ori_i32(val, val, 0x80); tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); tcg_temp_free(val); @@ -1874,7 +1861,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, ctx.pc = pc_start; ctx.flags = (uint32_t)tb->flags; ctx.bstate = BS_NONE; - ctx.memidx = (ctx.flags & SR_MD) == 0 ? 1 : 0; + ctx.memidx = (ctx.flags & (1u << SR_MD)) == 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branch, so assume it is a dynamic branch. */ ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |