diff options
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 75 |
1 files changed, 41 insertions, 34 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 38a707466c..1025752e8f 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -23,7 +23,7 @@ # endif #endif -#define CPUState struct CPUSPARCState +#define CPUArchState struct CPUSPARCState #include "cpu-defs.h" @@ -378,7 +378,9 @@ struct QEMUFile; void cpu_put_timer(struct QEMUFile *f, CPUTimer *s); void cpu_get_timer(struct QEMUFile *f, CPUTimer *s); -typedef struct CPUSPARCState { +typedef struct CPUSPARCState CPUSPARCState; + +struct CPUSPARCState { target_ulong gregs[8]; /* general registers */ target_ulong *regwptr; /* pointer to current register window */ target_ulong pc; /* program counter */ @@ -413,14 +415,15 @@ typedef struct CPUSPARCState { #if !defined(TARGET_SPARC64) int psref; /* enable fpu */ #endif - target_ulong version; int interrupt_index; - uint32_t nwindows; /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[MAX_NWINDOWS * 16 + 8]; CPU_COMMON + target_ulong version; + uint32_t nwindows; + /* MMU regs */ #if defined(TARGET_SPARC64) uint64_t lsu; @@ -490,6 +493,9 @@ typedef struct CPUSPARCState { /* UA 2005 hyperprivileged registers */ uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; CPUTimer *hstick; // UA 2005 + /* Interrupt vector registers */ + uint64_t ivec_status; + uint64_t ivec_data[3]; uint32_t softint; #define SOFTINT_TIMER 1 #define SOFTINT_STIMER (1 << 16) @@ -499,11 +505,11 @@ typedef struct CPUSPARCState { sparc_def_t *def; void *irq_manager; - void (*qemu_irq_ack)(CPUState *env, void *irq_manager, int intno); + void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); /* Leon3 cache control */ uint32_t cache_control; -} CPUSPARCState; +}; #ifndef NO_CPU_IO_DEFS /* cpu_init.c */ @@ -515,10 +521,10 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw int mmu_idx); #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); -void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env); +void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) -int target_memory_rw_debug(CPUState *env, target_ulong addr, +int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr, uint8_t *buf, int len, int is_write); #define TARGET_CPU_MEMORY_RW_DEBUG #endif @@ -531,22 +537,22 @@ void gen_intermediate_code_init(CPUSPARCState *env); int cpu_sparc_exec(CPUSPARCState *s); /* win_helper.c */ -target_ulong cpu_get_psr(CPUState *env1); -void cpu_put_psr(CPUState *env1, target_ulong val); +target_ulong cpu_get_psr(CPUSPARCState *env1); +void cpu_put_psr(CPUSPARCState *env1, target_ulong val); #ifdef TARGET_SPARC64 -target_ulong cpu_get_ccr(CPUState *env1); -void cpu_put_ccr(CPUState *env1, target_ulong val); -target_ulong cpu_get_cwp64(CPUState *env1); -void cpu_put_cwp64(CPUState *env1, int cwp); -void cpu_change_pstate(CPUState *env1, uint32_t new_pstate); +target_ulong cpu_get_ccr(CPUSPARCState *env1); +void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); +target_ulong cpu_get_cwp64(CPUSPARCState *env1); +void cpu_put_cwp64(CPUSPARCState *env1, int cwp); +void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); #endif -int cpu_cwp_inc(CPUState *env1, int cwp); -int cpu_cwp_dec(CPUState *env1, int cwp); -void cpu_set_cwp(CPUState *env1, int new_cwp); +int cpu_cwp_inc(CPUSPARCState *env1, int cwp); +int cpu_cwp_dec(CPUSPARCState *env1, int cwp); +void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); /* int_helper.c */ -void do_interrupt(CPUState *env); -void leon3_irq_manager(CPUState *env, void *irq_manager, int intno); +void do_interrupt(CPUSPARCState *env); +void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); /* sun4m.c, sun4u.c */ void cpu_check_irqs(CPUSPARCState *env); @@ -575,12 +581,11 @@ static inline int tlb_compare_context(const SparcTLBEntry *tlb, /* cpu-exec.c */ #if !defined(CONFIG_USER_ONLY) -void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr, +void cpu_unassigned_access(CPUSPARCState *env1, target_phys_addr_t addr, int is_write, int is_exec, int is_asi, int size); #if defined(TARGET_SPARC64) -target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, +target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, int mmu_idx); - #endif #endif int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); @@ -615,23 +620,23 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #endif #if defined (TARGET_SPARC64) -static inline int cpu_has_hypervisor(CPUState *env1) +static inline int cpu_has_hypervisor(CPUSPARCState *env1) { return env1->def->features & CPU_FEATURE_HYPV; } -static inline int cpu_hypervisor_mode(CPUState *env1) +static inline int cpu_hypervisor_mode(CPUSPARCState *env1) { return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); } -static inline int cpu_supervisor_mode(CPUState *env1) +static inline int cpu_supervisor_mode(CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } #endif -static inline int cpu_mmu_index(CPUState *env1) +static inline int cpu_mmu_index(CPUSPARCState *env1) { #if defined(CONFIG_USER_ONLY) return MMU_USER_IDX; @@ -650,7 +655,7 @@ static inline int cpu_mmu_index(CPUState *env1) #endif } -static inline int cpu_interrupts_enabled(CPUState *env1) +static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) if (env1->psret != 0) @@ -663,7 +668,7 @@ static inline int cpu_interrupts_enabled(CPUState *env1) return 0; } -static inline int cpu_pil_allowed(CPUState *env1, int pil) +static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) /* level 15 is non-maskable on sparc v8 */ @@ -674,7 +679,7 @@ static inline int cpu_pil_allowed(CPUState *env1, int pil) } #if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp) { if (newsp) env->regwptr[22] = newsp; @@ -692,13 +697,15 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) void cpu_tick_set_count(CPUTimer *timer, uint64_t count); uint64_t cpu_tick_get_count(CPUTimer *timer); void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); -trap_state* cpu_tsptr(CPUState* env); +trap_state* cpu_tsptr(CPUSPARCState* env); #endif +void do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write, + int is_user, void *retaddr); #define TB_FLAG_FPU_ENABLED (1 << 4) #define TB_FLAG_AM_ENABLED (1 << 5) -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { *pc = env->pc; @@ -743,7 +750,7 @@ static inline bool tb_am_enabled(int tb_flags) #endif } -static inline bool cpu_has_work(CPUState *env1) +static inline bool cpu_has_work(CPUSPARCState *env1) { return (env1->interrupt_request & CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(env1); @@ -751,7 +758,7 @@ static inline bool cpu_has_work(CPUState *env1) #include "exec-all.h" -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUSPARCState *env, TranslationBlock *tb) { env->pc = tb->pc; env->npc = tb->cs_base; |