diff options
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/helper.c | 10 | ||||
| -rw-r--r-- | target-sparc/int32_helper.c | 8 | ||||
| -rw-r--r-- | target-sparc/int64_helper.c | 6 | ||||
| -rw-r--r-- | target-sparc/ldst_helper.c | 2 | ||||
| -rw-r--r-- | target-sparc/mmu_helper.c | 22 |
5 files changed, 26 insertions, 22 deletions
diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 57c20af478..a393ef0a48 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -24,13 +24,17 @@ void helper_raise_exception(CPUSPARCState *env, int tt) { - env->exception_index = tt; + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = tt; cpu_loop_exit(env); } void helper_debug(CPUSPARCState *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } @@ -232,7 +236,7 @@ void helper_power_down(CPUSPARCState *env) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; env->pc = env->npc; env->npc = env->pc + 4; cpu_loop_exit(env); diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index d5322380cd..f350a903e0 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -62,7 +62,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int cwp, intno = env->exception_index; + int cwp, intno = cs->exception_index; /* Compute PSR before exposing state. */ if (env->cc_op != CC_OP_FLAGS) { @@ -105,12 +105,12 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { - if (env->exception_index == 0x80 && + if (cs->exception_index == 0x80 && env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", - env->exception_index); + cs->exception_index); } return; } @@ -125,7 +125,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) /* IRQ acknowledgment */ diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index bf7dd86ab8..1744245f70 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -63,7 +63,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int intno = env->exception_index; + int intno = cs->exception_index; trap_state *tsptr; /* Compute PSR before exposing state. */ @@ -112,7 +112,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," - " Error state", env->exception_index, env->tl, env->maxtl); + " Error state", cs->exception_index, env->tl, env->maxtl); return; } #endif @@ -160,7 +160,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; } trap_state *cpu_tsptr(CPUSPARCState* env) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index c2482454ac..e1475d0b0f 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -1325,7 +1325,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, dump_asi("read ", last_addr, asi, size, ret); #endif /* env->exception_index is set in get_physical_address_data(). */ - helper_raise_exception(env, env->exception_index); + helper_raise_exception(env, cs->exception_index); } /* convert nonfaulting load ASIs to normal load ASIs */ diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 5a9748e347..1571c6a026 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -28,12 +28,10 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - SPARCCPU *cpu = SPARC_CPU(cs); - if (rw & 2) { - cpu->env.exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - cpu->env.exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -239,9 +237,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, return 0; } else { if (rw & 2) { - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -491,6 +489,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; uint64_t sfsr = 0; @@ -555,10 +554,10 @@ static int get_physical_address_data(CPUSPARCState *env, if (do_fault) { /* faults above are reported with TT_DFAULT. */ - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { do_fault = 1; - env->exception_index = TT_DPROT; + cs->exception_index = TT_DPROT; trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); } @@ -602,7 +601,7 @@ static int get_physical_address_data(CPUSPARCState *env, * - JPS1: SFAR updated and some fields of SFSR updated */ env->dmmu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_DMISS; + cs->exception_index = TT_DMISS; return 1; } @@ -610,6 +609,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; @@ -653,7 +653,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* FIXME: ASI field in SFSR must be set */ env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; env->immu.tag_access = (address & ~0x1fffULL) | context; @@ -671,7 +671,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ env->immu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_TMISS; + cs->exception_index = TT_TMISS; return 1; } |