diff options
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/cpu.h | 94 | ||||
| -rw-r--r-- | target-sparc/exec.h | 32 | ||||
| -rw-r--r-- | target-sparc/fbranch_template.h | 89 | ||||
| -rw-r--r-- | target-sparc/fop_template.h | 28 | ||||
| -rw-r--r-- | target-sparc/helper.c | 189 | ||||
| -rw-r--r-- | target-sparc/op.c | 826 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 432 | ||||
| -rw-r--r-- | target-sparc/op_mem.h | 59 | ||||
| -rw-r--r-- | target-sparc/translate.c | 1253 |
9 files changed, 2636 insertions, 366 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index b556e23e4a..2eb900dfe4 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -6,12 +6,11 @@ #if !defined(TARGET_SPARC64) #define TARGET_LONG_BITS 32 #define TARGET_FPREGS 32 -#define TARGET_FPREG_T float #else #define TARGET_LONG_BITS 64 #define TARGET_FPREGS 64 -#define TARGET_FPREG_T double #endif +#define TARGET_FPREG_T float #include "cpu-defs.h" @@ -22,6 +21,7 @@ /*#define EXCP_INTERRUPT 0x100*/ /* trap definitions */ +#ifndef TARGET_SPARC64 #define TT_TFAULT 0x01 #define TT_ILL_INSN 0x02 #define TT_PRIV_INSN 0x03 @@ -33,6 +33,21 @@ #define TT_EXTINT 0x10 #define TT_DIV_ZERO 0x2a #define TT_TRAP 0x80 +#else +#define TT_TFAULT 0x08 +#define TT_ILL_INSN 0x10 +#define TT_PRIV_INSN 0x11 +#define TT_NFPU_INSN 0x20 +#define TT_FP_EXCP 0x21 +#define TT_CLRWIN 0x24 +#define TT_DIV_ZERO 0x28 +#define TT_DFAULT 0x30 +#define TT_EXTINT 0x40 +#define TT_SPILL 0x80 +#define TT_FILL 0xc0 +#define TT_WOTHER 0x10 +#define TT_TRAP 0x100 +#endif #define PSR_NEG (1<<23) #define PSR_ZERO (1<<22) @@ -49,6 +64,13 @@ /* Trap base register */ #define TBR_BASE_MASK 0xfffff000 +#if defined(TARGET_SPARC64) +#define PS_PEF (1<<4) +#define PS_AM (1<<3) +#define PS_PRIV (1<<2) +#define PS_IE (1<<1) +#endif + /* Fcc */ #define FSR_RD1 (1<<31) #define FSR_RD0 (1<<30) @@ -119,15 +141,15 @@ typedef struct CPUSPARCState { target_ulong npc; /* next program counter */ target_ulong y; /* multiply/divide register */ uint32_t psr; /* processor state register */ - uint32_t fsr; /* FPU state register */ + target_ulong fsr; /* FPU state register */ uint32_t cwp; /* index of current register window (extracted from PSR) */ uint32_t wim; /* window invalid mask */ - uint32_t tbr; /* trap base register */ + target_ulong tbr; /* trap base register */ int psrs; /* supervisor mode (extracted from PSR) */ int psrps; /* previous supervisor mode */ int psret; /* enable traps */ - int psrpil; /* interrupt level */ + uint32_t psrpil; /* interrupt level */ int psref; /* enable fpu */ jmp_buf jmp_env; int user_mode_only; @@ -150,13 +172,43 @@ typedef struct CPUSPARCState { CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; /* MMU regs */ +#if defined(TARGET_SPARC64) + uint64_t lsu; +#define DMMU_E 0x8 +#define IMMU_E 0x4 + uint64_t immuregs[16]; + uint64_t dmmuregs[16]; + uint64_t itlb_tag[64]; + uint64_t itlb_tte[64]; + uint64_t dtlb_tag[64]; + uint64_t dtlb_tte[64]; +#else uint32_t mmuregs[16]; +#endif /* temporary float registers */ - float ft0, ft1, ft2; - double dt0, dt1, dt2; + float ft0, ft1; + double dt0, dt1; float_status fp_status; #if defined(TARGET_SPARC64) - target_ulong t0, t1, t2; +#define MAXTL 4 + uint64_t t0, t1, t2; + uint64_t tpc[MAXTL]; + uint64_t tnpc[MAXTL]; + uint64_t tstate[MAXTL]; + uint32_t tt[MAXTL]; + uint32_t xcc; /* Extended integer condition codes */ + uint32_t asi; + uint32_t pstate; + uint32_t tl; + uint32_t cansave, canrestore, otherwin, wstate, cleanwin; + target_ulong agregs[8]; /* alternate general registers */ + target_ulong igregs[8]; /* interrupt general registers */ + target_ulong mgregs[8]; /* mmu general registers */ + uint64_t version; + uint64_t fprs; +#endif +#if !defined(TARGET_SPARC64) && !defined(reg_T2) + target_ulong t2; #endif /* ice debug support */ @@ -165,6 +217,24 @@ typedef struct CPUSPARCState { int singlestep_enabled; /* XXX: should use CPU single step mode instead */ } CPUSPARCState; +#if defined(TARGET_SPARC64) +#define GET_FSR32(env) (env->fsr & 0xcfc1ffff) +#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ + env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \ + } while (0) +#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL) +#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \ + env->fsr = _tmp & 0x3fcfc1c3ffULL; \ + } while (0) +// Manuf 0x17, version 0x11, mask 0 (UltraSparc-II) +#define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \ + (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1)) +#else +#define GET_FSR32(env) (env->fsr) +#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \ + env->fsr = _tmp & 0xcfc1ffff; \ + } while (0) +#endif CPUSPARCState *cpu_sparc_init(void); int cpu_sparc_exec(CPUSPARCState *s); @@ -194,6 +264,14 @@ void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \ } while (0) +#ifdef TARGET_SPARC64 +#define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC)) +#define PUT_CCR(env, val) do { int _tmp = val; \ + env->xcc = _tmp >> 4; \ + env->psr = (_tmp & 0xf) << 20; \ + } while (0) +#endif + struct siginfo; int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); diff --git a/target-sparc/exec.h b/target-sparc/exec.h index 5e6c06214b..cbfcb14d2b 100644 --- a/target-sparc/exec.h +++ b/target-sparc/exec.h @@ -1,23 +1,41 @@ #ifndef EXEC_SPARC_H #define EXEC_SPARC_H 1 #include "dyngen-exec.h" +#include "config.h" register struct CPUSPARCState *env asm(AREG0); #ifdef TARGET_SPARC64 #define T0 (env->t0) #define T1 (env->t1) #define T2 (env->t2) +#define REGWPTR env->regwptr #else register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); + +#undef REG_REGWPTR // Broken +#ifdef REG_REGWPTR +register uint32_t *REGWPTR asm(AREG3); +#define reg_REGWPTR + +#ifdef AREG4 +register uint32_t T2 asm(AREG4); +#define reg_T2 +#else +#define T2 (env->t2) +#endif + +#else +#define REGWPTR env->regwptr register uint32_t T2 asm(AREG3); +#define reg_T2 +#endif #endif + #define FT0 (env->ft0) #define FT1 (env->ft1) -#define FT2 (env->ft2) #define DT0 (env->dt0) #define DT1 (env->dt1) -#define DT2 (env->dt2) #include "cpu.h" #include "exec-all.h" @@ -38,6 +56,16 @@ void do_fsqrts(void); void do_fsqrtd(void); void do_fcmps(void); void do_fcmpd(void); +#ifdef TARGET_SPARC64 +void do_fabsd(void); +void do_fcmps_fcc1(void); +void do_fcmpd_fcc1(void); +void do_fcmps_fcc2(void); +void do_fcmpd_fcc2(void); +void do_fcmps_fcc3(void); +void do_fcmpd_fcc3(void); +void do_popc(); +#endif void do_ldd_kernel(target_ulong addr); void do_ldd_user(target_ulong addr); void do_ldd_raw(target_ulong addr); diff --git a/target-sparc/fbranch_template.h b/target-sparc/fbranch_template.h new file mode 100644 index 0000000000..e6bf9a269a --- /dev/null +++ b/target-sparc/fbranch_template.h @@ -0,0 +1,89 @@ +/* FCC1:FCC0: 0 =, 1 <, 2 >, 3 u */ + +void OPPROTO glue(op_eval_fbne, FCC)(void) +{ +// !0 + T2 = FFLAG_SET(FSR_FCC0) | FFLAG_SET(FSR_FCC1); /* L or G or U */ +} + +void OPPROTO glue(op_eval_fblg, FCC)(void) +{ +// 1 or 2 + T2 = FFLAG_SET(FSR_FCC0) ^ FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbul, FCC)(void) +{ +// 1 or 3 + T2 = FFLAG_SET(FSR_FCC0); +} + +void OPPROTO glue(op_eval_fbl, FCC)(void) +{ +// 1 + T2 = FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbug, FCC)(void) +{ +// 2 or 3 + T2 = FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbg, FCC)(void) +{ +// 2 + T2 = !FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbu, FCC)(void) +{ +// 3 + T2 = FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbe, FCC)(void) +{ +// 0 + T2 = !FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbue, FCC)(void) +{ +// 0 or 3 + T2 = !(FFLAG_SET(FSR_FCC1) ^ FFLAG_SET(FSR_FCC0)); + FORCE_RET(); +} + +void OPPROTO glue(op_eval_fbge, FCC)(void) +{ +// 0 or 2 + T2 = !FFLAG_SET(FSR_FCC0); +} + +void OPPROTO glue(op_eval_fbuge, FCC)(void) +{ +// !1 + T2 = !(FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1)); +} + +void OPPROTO glue(op_eval_fble, FCC)(void) +{ +// 0 or 1 + T2 = !FFLAG_SET(FSR_FCC1); +} + +void OPPROTO glue(op_eval_fbule, FCC)(void) +{ +// !2 + T2 = !(!FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1)); +} + +void OPPROTO glue(op_eval_fbo, FCC)(void) +{ +// !3 + T2 = !(FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1)); +} + +#undef FCC +#undef FFLAG_SET diff --git a/target-sparc/fop_template.h b/target-sparc/fop_template.h index eb1e1e3112..74988f7df1 100644 --- a/target-sparc/fop_template.h +++ b/target-sparc/fop_template.h @@ -40,16 +40,6 @@ void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void) REG = FT1; } -void OPPROTO glue(op_load_fpr_FT2_fpr, REGNAME)(void) -{ - FT2 = REG; -} - -void OPPROTO glue(op_store_FT2_fpr_fpr, REGNAME)(void) -{ - REG = FT2; -} - /* double floating point registers moves */ void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void) { @@ -87,23 +77,5 @@ void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void) *p = u.l.upper; } -void OPPROTO glue(op_load_fpr_DT2_fpr, REGNAME)(void) -{ - CPU_DoubleU u; - uint32_t *p = (uint32_t *)® - u.l.lower = *(p +1); - u.l.upper = *p; - DT2 = u.d; -} - -void OPPROTO glue(op_store_DT2_fpr_fpr, REGNAME)(void) -{ - CPU_DoubleU u; - uint32_t *p = (uint32_t *)® - u.d = DT2; - *(p +1) = u.l.lower; - *p = u.l.upper; -} - #undef REG #undef REGNAME diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 9fd5f214b3..a281e8d63b 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -43,7 +43,6 @@ void cpu_unlock(void) int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, int is_user, int is_softmmu) { - env->mmuregs[4] = address; if (rw & 2) env->exception_index = TT_TFAULT; else @@ -102,6 +101,7 @@ void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) env = saved_env; } +#ifndef TARGET_SPARC64 static const int access_table[8][8] = { { 0, 0, 0, 0, 2, 0, 3, 3 }, { 0, 0, 0, 0, 2, 0, 0, 0 }, @@ -268,6 +268,136 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return 1; } } +#else +static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, + int *access_index, target_ulong address, int rw, + int is_user) +{ + target_ulong mask; + unsigned int i; + + if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ + *physical = address & 0xffffffff; + *prot = PAGE_READ | PAGE_WRITE; + return 0; + } + + for (i = 0; i < 64; i++) { + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { + switch (env->dtlb_tte[i] >> 60) { + default: + case 0x4: // 8k + mask = 0xffffffffffffe000ULL; + break; + case 0x5: // 64k + mask = 0xffffffffffff0000ULL; + break; + case 0x6: // 512k + mask = 0xfffffffffff80000ULL; + break; + case 0x7: // 4M + mask = 0xffffffffffc00000ULL; + break; + } + // ctx match, vaddr match? + if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && + (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) { + // access ok? + if (((env->dtlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) || + (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { + env->exception_index = TT_DFAULT; + return 1; + } + *physical = env->dtlb_tte[i] & 0xffffe000; + *prot = PAGE_READ; + if (env->dtlb_tte[i] & 0x2) + *prot |= PAGE_WRITE; + return 0; + } + } + } + env->exception_index = TT_DFAULT; + return 1; +} + +static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, + int *access_index, target_ulong address, int rw, + int is_user) +{ + target_ulong mask; + unsigned int i; + + if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ + *physical = address & 0xffffffff; + *prot = PAGE_READ; + return 0; + } + for (i = 0; i < 64; i++) { + if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { + switch (env->itlb_tte[i] >> 60) { + default: + case 0x4: // 8k + mask = 0xffffffffffffe000ULL; + break; + case 0x5: // 64k + mask = 0xffffffffffff0000ULL; + break; + case 0x6: // 512k + mask = 0xfffffffffff80000ULL; + break; + case 0x7: // 4M + mask = 0xffffffffffc00000ULL; + break; + } + // ctx match, vaddr match? + if (env->immuregs[1] == (env->itlb_tag[i] & 0x1fff) && + (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) { + // access ok? + if ((env->itlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) { + env->exception_index = TT_TFAULT; + return 1; + } + *physical = env->itlb_tte[i] & 0xffffe000; + *prot = PAGE_READ; + return 0; + } + } + } + env->exception_index = TT_TFAULT; + return 1; +} + +int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot, + int *access_index, target_ulong address, int rw, + int is_user) +{ + if (rw == 2) + return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user); + else + return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user); +} + +/* Perform address translation */ +int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, + int is_user, int is_softmmu) +{ + target_ulong virt_addr; + target_phys_addr_t paddr; + unsigned long vaddr; + int error_code = 0, prot, ret = 0, access_index; + + error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); + if (error_code == 0) { + virt_addr = address & TARGET_PAGE_MASK; + vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); + ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); + return ret; + } + // XXX + return 1; +} + +#endif #endif void memcpy32(target_ulong *dst, const target_ulong *src) @@ -292,17 +422,73 @@ void set_cwp(int new_cwp) if (new_cwp == (NWINDOWS - 1)) memcpy32(env->regbase + NWINDOWS * 16, env->regbase); env->regwptr = env->regbase + (new_cwp * 16); + REGWPTR = env->regwptr; } void cpu_set_cwp(CPUState *env1, int new_cwp) { CPUState *saved_env; +#ifdef reg_REGWPTR + target_ulong *saved_regwptr; +#endif + saved_env = env; +#ifdef reg_REGWPTR + saved_regwptr = REGWPTR; +#endif env = env1; set_cwp(new_cwp); env = saved_env; +#ifdef reg_REGWPTR + REGWPTR = saved_regwptr; +#endif } +#ifdef TARGET_SPARC64 +void do_interrupt(int intno) +{ +#ifdef DEBUG_PCALL + if (loglevel & CPU_LOG_INT) { + static int count; + fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n", + count, intno, + env->pc, + env->npc, env->regwptr[6]); + cpu_dump_state(env, logfile, fprintf, 0); +#if 0 + { + int i; + uint8_t *ptr; + + fprintf(logfile, " code="); + ptr = (uint8_t *)env->pc; + for(i = 0; i < 16; i++) { + fprintf(logfile, " %02x", ldub(ptr + i)); + } + fprintf(logfile, "\n"); + } +#endif + count++; + } +#endif +#if !defined(CONFIG_USER_ONLY) + if (env->pstate & PS_IE) { + cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index); + return; + } +#endif + env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | + ((env->pstate & 0xfff) << 8) | (env->cwp & 0xff); + env->tpc[env->tl] = env->pc; + env->tnpc[env->tl] = env->npc; + env->tt[env->tl] = intno; + env->tbr = env->tbr | (env->tl > 1) ? 1 << 14 : 0 | (intno << 4); + env->tl++; + env->pc = env->tbr; + env->npc = env->pc + 4; + env->exception_index = 0; +} +#else void do_interrupt(int intno) { int cwp; @@ -448,3 +634,4 @@ void dump_mmu(void) printf("MMU dump ends\n"); } #endif +#endif diff --git a/target-sparc/op.c b/target-sparc/op.c index 281917a7f1..86c45c7093 100644 --- a/target-sparc/op.c +++ b/target-sparc/op.c @@ -46,76 +46,76 @@ #define REG (env->gregs[7]) #include "op_template.h" #define REGNAME i0 -#define REG (env->regwptr[16]) +#define REG (REGWPTR[16]) #include "op_template.h" #define REGNAME i1 -#define REG (env->regwptr[17]) +#define REG (REGWPTR[17]) #include "op_template.h" #define REGNAME i2 -#define REG (env->regwptr[18]) +#define REG (REGWPTR[18]) #include "op_template.h" #define REGNAME i3 -#define REG (env->regwptr[19]) +#define REG (REGWPTR[19]) #include "op_template.h" #define REGNAME i4 -#define REG (env->regwptr[20]) +#define REG (REGWPTR[20]) #include "op_template.h" #define REGNAME i5 -#define REG (env->regwptr[21]) +#define REG (REGWPTR[21]) #include "op_template.h" #define REGNAME i6 -#define REG (env->regwptr[22]) +#define REG (REGWPTR[22]) #include "op_template.h" #define REGNAME i7 -#define REG (env->regwptr[23]) +#define REG (REGWPTR[23]) #include "op_template.h" #define REGNAME l0 -#define REG (env->regwptr[8]) +#define REG (REGWPTR[8]) #include "op_template.h" #define REGNAME l1 -#define REG (env->regwptr[9]) +#define REG (REGWPTR[9]) #include "op_template.h" #define REGNAME l2 -#define REG (env->regwptr[10]) +#define REG (REGWPTR[10]) #include "op_template.h" #define REGNAME l3 -#define REG (env->regwptr[11]) +#define REG (REGWPTR[11]) #include "op_template.h" #define REGNAME l4 -#define REG (env->regwptr[12]) +#define REG (REGWPTR[12]) #include "op_template.h" #define REGNAME l5 -#define REG (env->regwptr[13]) +#define REG (REGWPTR[13]) #include "op_template.h" #define REGNAME l6 -#define REG (env->regwptr[14]) +#define REG (REGWPTR[14]) #include "op_template.h" #define REGNAME l7 -#define REG (env->regwptr[15]) +#define REG (REGWPTR[15]) #include "op_template.h" #define REGNAME o0 -#define REG (env->regwptr[0]) +#define REG (REGWPTR[0]) #include "op_template.h" #define REGNAME o1 -#define REG (env->regwptr[1]) +#define REG (REGWPTR[1]) #include "op_template.h" #define REGNAME o2 -#define REG (env->regwptr[2]) +#define REG (REGWPTR[2]) #include "op_template.h" #define REGNAME o3 -#define REG (env->regwptr[3]) +#define REG (REGWPTR[3]) #include "op_template.h" #define REGNAME o4 -#define REG (env->regwptr[4]) +#define REG (REGWPTR[4]) #include "op_template.h" #define REGNAME o5 -#define REG (env->regwptr[5]) +#define REG (REGWPTR[5]) #include "op_template.h" #define REGNAME o6 -#define REG (env->regwptr[6]) +#define REG (REGWPTR[6]) #include "op_template.h" #define REGNAME o7 -#define REG (env->regwptr[7]) +#define REG (REGWPTR[7]) #include "op_template.h" #define REGNAME f0 @@ -215,10 +215,106 @@ #define REG (env->fpr[31]) #include "fop_template.h" +#ifdef TARGET_SPARC64 +#define REGNAME f32 +#define REG (env->fpr[32]) +#include "fop_template.h" +#define REGNAME f34 +#define REG (env->fpr[34]) +#include "fop_template.h" +#define REGNAME f36 +#define REG (env->fpr[36]) +#include "fop_template.h" +#define REGNAME f38 +#define REG (env->fpr[38]) +#include "fop_template.h" +#define REGNAME f40 +#define REG (env->fpr[40]) +#include "fop_template.h" +#define REGNAME f42 +#define REG (env->fpr[42]) +#include "fop_template.h" +#define REGNAME f44 +#define REG (env->fpr[44]) +#include "fop_template.h" +#define REGNAME f46 +#define REG (env->fpr[46]) +#include "fop_template.h" +#define REGNAME f48 +#define REG (env->fpr[47]) +#include "fop_template.h" +#define REGNAME f50 +#define REG (env->fpr[50]) +#include "fop_template.h" +#define REGNAME f52 +#define REG (env->fpr[52]) +#include "fop_template.h" +#define REGNAME f54 +#define REG (env->fpr[54]) +#include "fop_template.h" +#define REGNAME f56 +#define REG (env->fpr[56]) +#include "fop_template.h" +#define REGNAME f58 +#define REG (env->fpr[58]) +#include "fop_template.h" +#define REGNAME f60 +#define REG (env->fpr[60]) +#include "fop_template.h" +#define REGNAME f62 +#define REG (env->fpr[62]) +#include "fop_template.h" +#endif + +#ifdef TARGET_SPARC64 +#undef JUMP_TB +#define JUMP_TB(opname, tbparam, n, eip) \ + do { \ + GOTO_TB(opname, tbparam, n); \ + T0 = (long)(tbparam) + (n); \ + env->pc = (eip) & 0xffffffff; \ + EXIT_TB(); \ + } while (0) + +#ifdef WORDS_BIGENDIAN +typedef union UREG64 { + struct { uint16_t v3, v2, v1, v0; } w; + struct { uint32_t v1, v0; } l; + uint64_t q; +} UREG64; +#else +typedef union UREG64 { + struct { uint16_t v0, v1, v2, v3; } w; + struct { uint32_t v0, v1; } l; + uint64_t q; +} UREG64; +#endif + +#define PARAMQ1 \ +({\ + UREG64 __p;\ + __p.l.v1 = PARAM1;\ + __p.l.v0 = PARAM2;\ + __p.q;\ +}) + +void OPPROTO op_movq_T0_im64(void) +{ + T0 = PARAMQ1; +} + +void OPPROTO op_movq_T1_im64(void) +{ + T1 = PARAMQ1; +} + +#define XFLAG_SET(x) ((env->xcc&x)?1:0) + +#else #define EIP (env->pc) +#endif #define FLAG_SET(x) ((env->psr&x)?1:0) -#define FFLAG_SET(x) ((env->fsr&x)?1:0) void OPPROTO op_movl_T0_0(void) { @@ -227,17 +323,52 @@ void OPPROTO op_movl_T0_0(void) void OPPROTO op_movl_T0_im(void) { - T0 = PARAM1; + T0 = (uint32_t)PARAM1; } void OPPROTO op_movl_T1_im(void) { - T1 = PARAM1; + T1 = (uint32_t)PARAM1; } void OPPROTO op_movl_T2_im(void) { - T2 = PARAM1; + T2 = (uint32_t)PARAM1; +} + +void OPPROTO op_movl_T0_sim(void) +{ + T0 = (int32_t)PARAM1; +} + +void OPPROTO op_movl_T1_sim(void) +{ + T1 = (int32_t)PARAM1; +} + +void OPPROTO op_movl_T2_sim(void) +{ + T2 = (int32_t)PARAM1; +} + +void OPPROTO op_movl_T0_env(void) +{ + T0 = *(uint32_t *)((char *)env + PARAM1); +} + +void OPPROTO op_movl_env_T0(void) +{ + *(uint32_t *)((char *)env + PARAM1) = T0; +} + +void OPPROTO op_movtl_T0_env(void) +{ + T0 = *(target_ulong *)((char *)env + PARAM1); +} + +void OPPROTO op_movtl_env_T0(void) +{ + *(target_ulong *)((char *)env + PARAM1) = T0; } void OPPROTO op_add_T1_T0(void) @@ -252,6 +383,27 @@ void OPPROTO op_add_T1_T0_cc(void) src1 = T0; T0 += T1; env->psr = 0; +#ifdef TARGET_SPARC64 + if (!(T0 & 0xffffffff)) + env->psr |= PSR_ZERO; + if ((int32_t) T0 < 0) + env->psr |= PSR_NEG; + if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) + env->psr |= PSR_CARRY; + if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) + env->psr |= PSR_OVF; + + env->xcc = 0; + if (!T0) + env->xcc |= PSR_ZERO; + if ((int64_t) T0 < 0) + env->xcc |= PSR_NEG; + if (T0 < src1) + env->xcc |= PSR_CARRY; + if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) + env->xcc |= PSR_OVF; +#else if (!T0) env->psr |= PSR_ZERO; if ((int32_t) T0 < 0) @@ -260,7 +412,7 @@ void OPPROTO op_add_T1_T0_cc(void) env->psr |= PSR_CARRY; if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) env->psr |= PSR_OVF; - /* V9 xcc */ +#endif FORCE_RET(); } @@ -276,6 +428,27 @@ void OPPROTO op_addx_T1_T0_cc(void) src1 = T0; T0 += T1 + FLAG_SET(PSR_CARRY); env->psr = 0; +#ifdef TARGET_SPARC64 + if (!(T0 & 0xffffffff)) + env->psr |= PSR_ZERO; + if ((int32_t) T0 < 0) + env->psr |= PSR_NEG; + if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) + env->psr |= PSR_CARRY; + if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) & + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) + env->psr |= PSR_OVF; + + env->xcc = 0; + if (!T0) + env->xcc |= PSR_ZERO; + if ((int64_t) T0 < 0) + env->xcc |= PSR_NEG; + if (T0 < src1) + env->xcc |= PSR_CARRY; + if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63)) + env->xcc |= PSR_OVF; +#else if (!T0) env->psr |= PSR_ZERO; if ((int32_t) T0 < 0) @@ -284,7 +457,7 @@ void OPPROTO op_addx_T1_T0_cc(void) env->psr |= PSR_CARRY; if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) env->psr |= PSR_OVF; - /* V9 xcc */ +#endif FORCE_RET(); } @@ -300,6 +473,27 @@ void OPPROTO op_sub_T1_T0_cc(void) src1 = T0; T0 -= T1; env->psr = 0; +#ifdef TARGET_SPARC64 + if (!(T0 & 0xffffffff)) + env->psr |= PSR_ZERO; + if ((int32_t) T0 < 0) + env->psr |= PSR_NEG; + if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) + env->psr |= PSR_CARRY; + if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) + env->psr |= PSR_OVF; + + env->xcc = 0; + if (!T0) + env->xcc |= PSR_ZERO; + if ((int64_t) T0 < 0) + env->xcc |= PSR_NEG; + if (T0 < src1) + env->xcc |= PSR_CARRY; + if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) + env->xcc |= PSR_OVF; +#else if (!T0) env->psr |= PSR_ZERO; if ((int32_t) T0 < 0) @@ -308,7 +502,7 @@ void OPPROTO op_sub_T1_T0_cc(void) env->psr |= PSR_CARRY; if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) env->psr |= PSR_OVF; - /* V9 xcc */ +#endif FORCE_RET(); } @@ -324,6 +518,27 @@ void OPPROTO op_subx_T1_T0_cc(void) src1 = T0; T0 -= T1 + FLAG_SET(PSR_CARRY); env->psr = 0; +#ifdef TARGET_SPARC64 + if (!(T0 & 0xffffffff)) + env->psr |= PSR_ZERO; + if ((int32_t) T0 < 0) + env->psr |= PSR_NEG; + if ((T0 & 0xffffffff) < (src1 & 0xffffffff)) + env->psr |= PSR_CARRY; + if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) & + ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31)) + env->psr |= PSR_OVF; + + env->xcc = 0; + if (!T0) + env->xcc |= PSR_ZERO; + if ((int64_t) T0 < 0) + env->xcc |= PSR_NEG; + if (T0 < src1) + env->xcc |= PSR_CARRY; + if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63)) + env->xcc |= PSR_OVF; +#else if (!T0) env->psr |= PSR_ZERO; if ((int32_t) T0 < 0) @@ -332,7 +547,7 @@ void OPPROTO op_subx_T1_T0_cc(void) env->psr |= PSR_CARRY; if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) env->psr |= PSR_OVF; - /* V9 xcc */ +#endif FORCE_RET(); } @@ -449,24 +664,73 @@ void OPPROTO op_sdiv_T1_T0(void) void OPPROTO op_div_cc(void) { env->psr = 0; +#ifdef TARGET_SPARC64 + if (!T0) + env->psr |= PSR_ZERO; + if ((int32_t) T0 < 0) + env->psr |= PSR_NEG; + if (T1) + env->psr |= PSR_OVF; + + env->xcc = 0; + if (!T0) + env->xcc |= PSR_ZERO; + if ((int64_t) T0 < 0) + env->xcc |= PSR_NEG; +#else if (!T0) env->psr |= PSR_ZERO; if ((int32_t) T0 < 0) env->psr |= PSR_NEG; if (T1) env->psr |= PSR_OVF; - /* V9 xcc */ +#endif FORCE_RET(); } +#ifdef TARGET_SPARC64 +void OPPROTO op_mulx_T1_T0(void) +{ + T0 *= T1; + FORCE_RET(); +} + +void OPPROTO op_udivx_T1_T0(void) +{ + T0 /= T1; + FORCE_RET(); +} + +void OPPROTO op_sdivx_T1_T0(void) +{ + if (T0 == INT64_MIN && T1 == -1) + T0 = INT64_MIN; + else + T0 /= (target_long) T1; + FORCE_RET(); +} +#endif + void OPPROTO op_logic_T0_cc(void) { env->psr = 0; +#ifdef TARGET_SPARC64 + if (!(T0 & 0xffffffff)) + env->psr |= PSR_ZERO; + if ((int32_t) T0 < 0) + env->psr |= PSR_NEG; + + env->xcc = 0; + if (!T0) + env->xcc |= PSR_ZERO; + if ((int64_t) T0 < 0) + env->xcc |= PSR_NEG; +#else if (!T0) env->psr |= PSR_ZERO; if ((int32_t) T0 < 0) env->psr |= PSR_NEG; - /* V9 xcc */ +#endif FORCE_RET(); } @@ -475,6 +739,27 @@ void OPPROTO op_sll(void) T0 <<= T1; } +#ifdef TARGET_SPARC64 +void OPPROTO op_srl(void) +{ + T0 = (T0 & 0xffffffff) >> T1; +} + +void OPPROTO op_srlx(void) +{ + T0 >>= T1; +} + +void OPPROTO op_sra(void) +{ + T0 = ((int32_t) (T0 & 0xffffffff)) >> T1; +} + +void OPPROTO op_srax(void) +{ + T0 = ((int64_t) T0) >> T1; +} +#else void OPPROTO op_srl(void) { T0 >>= T1; @@ -484,6 +769,7 @@ void OPPROTO op_sra(void) { T0 = ((int32_t) T0) >> T1; } +#endif /* Load and store */ #define MEMSUFFIX _raw @@ -498,62 +784,137 @@ void OPPROTO op_sra(void) void OPPROTO op_ldfsr(void) { - env->fsr = *((uint32_t *) &FT0); + PUT_FSR32(env, *((uint32_t *) &FT0)); helper_ldfsr(); } void OPPROTO op_stfsr(void) { - *((uint32_t *) &FT0) = env->fsr; + *((uint32_t *) &FT0) = GET_FSR32(env); } -void OPPROTO op_wry(void) +#ifndef TARGET_SPARC64 +void OPPROTO op_rdpsr(void) { - env->y = T0; + do_rdpsr(); } -void OPPROTO op_rdy(void) +void OPPROTO op_wrpsr(void) { - T0 = env->y; + do_wrpsr(); + FORCE_RET(); } -void OPPROTO op_rdwim(void) +void OPPROTO op_rett(void) { - T0 = env->wim; + helper_rett(); + FORCE_RET(); } -void OPPROTO op_wrwim(void) +/* XXX: use another pointer for %iN registers to avoid slow wrapping + handling ? */ +void OPPROTO op_save(void) { - env->wim = T0; + uint32_t cwp; + cwp = (env->cwp - 1) & (NWINDOWS - 1); + if (env->wim & (1 << cwp)) { + raise_exception(TT_WIN_OVF); + } + set_cwp(cwp); FORCE_RET(); } -void OPPROTO op_rdpsr(void) +void OPPROTO op_restore(void) { - do_rdpsr(); + uint32_t cwp; + cwp = (env->cwp + 1) & (NWINDOWS - 1); + if (env->wim & (1 << cwp)) { + raise_exception(TT_WIN_UNF); + } + set_cwp(cwp); + FORCE_RET(); +} +#else +void OPPROTO op_rdccr(void) +{ + T0 = GET_CCR(env); } -void OPPROTO op_wrpsr(void) +void OPPROTO op_wrccr(void) { - do_wrpsr(); - FORCE_RET(); + PUT_CCR(env, T0); } -void OPPROTO op_rdtbr(void) +void OPPROTO op_rdtick(void) { - T0 = env->tbr; + T0 = 0; // XXX read cycle counter and bit 31 } -void OPPROTO op_wrtbr(void) +void OPPROTO op_wrtick(void) { - env->tbr = T0; - FORCE_RET(); + // XXX write cycle counter and bit 31 } -void OPPROTO op_rett(void) +void OPPROTO op_rdtpc(void) { - helper_rett(); - FORCE_RET(); + T0 = env->tpc[env->tl]; +} + +void OPPROTO op_wrtpc(void) +{ + env->tpc[env->tl] = T0; +} + +void OPPROTO op_rdtnpc(void) +{ + T0 = env->tnpc[env->tl]; +} + +void OPPROTO op_wrtnpc(void) +{ + env->tnpc[env->tl] = T0; +} + +void OPPROTO op_rdtstate(void) +{ + T0 = env->tstate[env->tl]; +} + +void OPPROTO op_wrtstate(void) +{ + env->tstate[env->tl] = T0; +} + +void OPPROTO op_rdtt(void) +{ + T0 = env->tt[env->tl]; +} + +void OPPROTO op_wrtt(void) +{ + env->tt[env->tl] = T0; +} + +void OPPROTO op_rdpstate(void) +{ + T0 = env->pstate; +} + +void OPPROTO op_wrpstate(void) +{ + env->pstate = T0 & 0x1f; +} + +// CWP handling is reversed in V9, but we still use the V8 register +// order. +void OPPROTO op_rdcwp(void) +{ + T0 = NWINDOWS - 1 - env->cwp; +} + +void OPPROTO op_wrcwp(void) +{ + env->cwp = NWINDOWS - 1 - T0; } /* XXX: use another pointer for %iN registers to avoid slow wrapping @@ -562,10 +923,20 @@ void OPPROTO op_save(void) { uint32_t cwp; cwp = (env->cwp - 1) & (NWINDOWS - 1); - if (env->wim & (1 << cwp)) { - raise_exception(TT_WIN_OVF); + if (env->cansave == 0) { + raise_exception(TT_SPILL | (env->otherwin != 0 ? + (TT_WOTHER | ((env->wstate & 0x38) >> 1)): + ((env->wstate & 0x7) << 2))); + } else { + if (env->cleanwin - env->canrestore == 0) { + // XXX Clean windows without trap + raise_exception(TT_CLRWIN); + } else { + env->cansave--; + env->canrestore++; + set_cwp(cwp); + } } - set_cwp(cwp); FORCE_RET(); } @@ -573,12 +944,18 @@ void OPPROTO op_restore(void) { uint32_t cwp; cwp = (env->cwp + 1) & (NWINDOWS - 1); - if (env->wim & (1 << cwp)) { - raise_exception(TT_WIN_UNF); + if (env->canrestore == 0) { + raise_exception(TT_FILL | (env->otherwin != 0 ? + (TT_WOTHER | ((env->wstate & 0x38) >> 1)): + ((env->wstate & 0x7) << 2))); + } else { + env->cansave++; + env->canrestore--; + set_cwp(cwp); } - set_cwp(cwp); FORCE_RET(); } +#endif void OPPROTO op_exception(void) { @@ -629,6 +1006,11 @@ void OPPROTO op_exit_tb(void) EXIT_TB(); } +void OPPROTO op_eval_ba(void) +{ + T2 = 1; +} + void OPPROTO op_eval_be(void) { T2 = FLAG_SET(PSR_ZERO); @@ -665,6 +1047,11 @@ void OPPROTO op_eval_bvs(void) T2 = FLAG_SET(PSR_OVF); } +void OPPROTO op_eval_bn(void) +{ + T2 = 0; +} + void OPPROTO op_eval_bneg(void) { T2 = FLAG_SET(PSR_NEG); @@ -711,101 +1098,156 @@ void OPPROTO op_eval_bvc(void) T2 = !FLAG_SET(PSR_OVF); } -/* FCC1:FCC0: 0 =, 1 <, 2 >, 3 u */ +#ifdef TARGET_SPARC64 +void OPPROTO op_eval_xbe(void) +{ + T2 = XFLAG_SET(PSR_ZERO); +} -void OPPROTO op_eval_fbne(void) +void OPPROTO op_eval_xble(void) { -// !0 - T2 = (env->fsr & (FSR_FCC1 | FSR_FCC0)); /* L or G or U */ + target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); + + T2 = Z | (N ^ V); } -void OPPROTO op_eval_fblg(void) +void OPPROTO op_eval_xbl(void) { -// 1 or 2 - T2 = FFLAG_SET(FSR_FCC0) ^ FFLAG_SET(FSR_FCC1); + target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); + + T2 = N ^ V; } -void OPPROTO op_eval_fbul(void) +void OPPROTO op_eval_xbleu(void) { -// 1 or 3 - T2 = FFLAG_SET(FSR_FCC0); + target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY); + + T2 = C | Z; } -void OPPROTO op_eval_fbl(void) +void OPPROTO op_eval_xbcs(void) { -// 1 - T2 = FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1); + T2 = XFLAG_SET(PSR_CARRY); } -void OPPROTO op_eval_fbug(void) +void OPPROTO op_eval_xbvs(void) { -// 2 or 3 - T2 = FFLAG_SET(FSR_FCC1); + T2 = XFLAG_SET(PSR_OVF); } -void OPPROTO op_eval_fbg(void) +void OPPROTO op_eval_xbneg(void) { -// 2 - T2 = !FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1); + T2 = XFLAG_SET(PSR_NEG); } -void OPPROTO op_eval_fbu(void) +void OPPROTO op_eval_xbne(void) { -// 3 - T2 = FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1); + T2 = !XFLAG_SET(PSR_ZERO); } -void OPPROTO op_eval_fbe(void) +void OPPROTO op_eval_xbg(void) { -// 0 - T2 = !FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1); + target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); + + T2 = !(Z | (N ^ V)); } -void OPPROTO op_eval_fbue(void) +void OPPROTO op_eval_xbge(void) { -// 0 or 3 - T2 = !(FFLAG_SET(FSR_FCC1) ^ FFLAG_SET(FSR_FCC0)); - FORCE_RET(); + target_ulong N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF); + + T2 = !(N ^ V); +} + +void OPPROTO op_eval_xbgu(void) +{ + target_ulong Z = XFLAG_SET(PSR_ZERO), C = XFLAG_SET(PSR_CARRY); + + T2 = !(C | Z); +} + +void OPPROTO op_eval_xbcc(void) +{ + T2 = !XFLAG_SET(PSR_CARRY); +} + +void OPPROTO op_eval_xbpos(void) +{ + T2 = !XFLAG_SET(PSR_NEG); +} + +void OPPROTO op_eval_xbvc(void) +{ + T2 = !XFLAG_SET(PSR_OVF); +} +#endif + +#define FCC +#define FFLAG_SET(x) (env->fsr & x? 1: 0) +#include "fbranch_template.h" + +#ifdef TARGET_SPARC64 +#define FCC _fcc1 +#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 32))? 1: 0) +#include "fbranch_template.h" +#define FCC _fcc2 +#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 34))? 1: 0) +#include "fbranch_template.h" +#define FCC _fcc3 +#define FFLAG_SET(x) ((env->fsr & ((uint64_t)x >> 36))? 1: 0) +#include "fbranch_template.h" +#endif + +#ifdef TARGET_SPARC64 +void OPPROTO op_eval_brz(void) +{ + T2 = T0; } -void OPPROTO op_eval_fbge(void) +void OPPROTO op_eval_brnz(void) { -// 0 or 2 - T2 = !FFLAG_SET(FSR_FCC0); + T2 = !T0; } -void OPPROTO op_eval_fbuge(void) +void OPPROTO op_eval_brlz(void) { -// !1 - T2 = !(FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1)); + T2 = ((int64_t)T0 < 0); } -void OPPROTO op_eval_fble(void) +void OPPROTO op_eval_brlez(void) { -// 0 or 1 - T2 = !FFLAG_SET(FSR_FCC1); + T2 = ((int64_t)T0 <= 0); } -void OPPROTO op_eval_fbule(void) +void OPPROTO op_eval_brgz(void) { -// !2 - T2 = !(!FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1)); + T2 = ((int64_t)T0 > 0); } -void OPPROTO op_eval_fbo(void) +void OPPROTO op_eval_brgez(void) { -// !3 - T2 = !(FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1)); + T2 = ((int64_t)T0 >= 0); } +void OPPROTO op_jmp_im64(void) +{ + env->pc = PARAMQ1; +} + +void OPPROTO op_movq_npc_im64(void) +{ + env->npc = PARAMQ1; +} +#endif + void OPPROTO op_jmp_im(void) { - env->pc = PARAM1; + env->pc = (uint32_t)PARAM1; } void OPPROTO op_movl_npc_im(void) { - env->npc = PARAM1; + env->npc = (uint32_t)PARAM1; } void OPPROTO op_movl_npc_T0(void) @@ -826,17 +1268,17 @@ void OPPROTO op_next_insn(void) void OPPROTO op_branch(void) { - env->npc = PARAM3; /* XXX: optimize */ + env->npc = (uint32_t)PARAM3; /* XXX: optimize */ JUMP_TB(op_branch, PARAM1, 0, PARAM2); } void OPPROTO op_branch2(void) { if (T2) { - env->npc = PARAM2 + 4; + env->npc = (uint32_t)PARAM2 + 4; JUMP_TB(op_branch2, PARAM1, 0, PARAM2); } else { - env->npc = PARAM3 + 4; + env->npc = (uint32_t)PARAM3 + 4; JUMP_TB(op_branch2, PARAM1, 1, PARAM3); } FORCE_RET(); @@ -845,10 +1287,10 @@ void OPPROTO op_branch2(void) void OPPROTO op_branch_a(void) { if (T2) { - env->npc = PARAM2; /* XXX: optimize */ + env->npc = (uint32_t)PARAM2; /* XXX: optimize */ JUMP_TB(op_branch_a, PARAM1, 0, PARAM3); } else { - env->npc = PARAM3 + 8; /* XXX: optimize */ + env->npc = (uint32_t)PARAM3 + 8; /* XXX: optimize */ JUMP_TB(op_branch_a, PARAM1, 1, PARAM3 + 4); } FORCE_RET(); @@ -857,9 +1299,9 @@ void OPPROTO op_branch_a(void) void OPPROTO op_generic_branch(void) { if (T2) { - env->npc = PARAM1; + env->npc = (uint32_t)PARAM1; } else { - env->npc = PARAM2; + env->npc = (uint32_t)PARAM2; } FORCE_RET(); } @@ -879,6 +1321,18 @@ void OPPROTO op_fabss(void) do_fabss(); } +#ifdef TARGET_SPARC64 +void OPPROTO op_fnegd(void) +{ + DT0 = -DT1; +} + +void OPPROTO op_fabsd(void) +{ + do_fabsd(); +} +#endif + void OPPROTO op_fsqrts(void) { do_fsqrts(); @@ -944,6 +1398,38 @@ void OPPROTO op_fcmpd(void) do_fcmpd(); } +#ifdef TARGET_SPARC64 +void OPPROTO op_fcmps_fcc1(void) +{ + do_fcmps_fcc1(); +} + +void OPPROTO op_fcmpd_fcc1(void) +{ + do_fcmpd_fcc1(); +} + +void OPPROTO op_fcmps_fcc2(void) +{ + do_fcmps_fcc2(); +} + +void OPPROTO op_fcmpd_fcc2(void) +{ + do_fcmpd_fcc2(); +} + +void OPPROTO op_fcmps_fcc3(void) +{ + do_fcmps_fcc3(); +} + +void OPPROTO op_fcmpd_fcc3(void) +{ + do_fcmpd_fcc3(); +} +#endif + #ifdef USE_INT_TO_FLOAT_HELPERS void OPPROTO op_fitos(void) { @@ -964,6 +1450,18 @@ void OPPROTO op_fitod(void) { DT0 = (double) *((int32_t *)&FT1); } + +#ifdef TARGET_SPARC64 +void OPPROTO op_fxtos(void) +{ + FT0 = (float) *((int64_t *)&DT1); +} + +void OPPROTO op_fxtod(void) +{ + DT0 = (double) *((int64_t *)&DT1); +} +#endif #endif void OPPROTO op_fdtos(void) @@ -986,6 +1484,102 @@ void OPPROTO op_fdtoi(void) *((int32_t *)&FT0) = (int32_t) DT1; } +#ifdef TARGET_SPARC64 +void OPPROTO op_fstox(void) +{ + *((int64_t *)&DT0) = (int64_t) FT1; +} + +void OPPROTO op_fdtox(void) +{ + *((int64_t *)&DT0) = (int64_t) DT1; +} + +void OPPROTO op_fmovs_cc(void) +{ + if (T2) + FT0 = FT1; +} + +void OPPROTO op_fmovd_cc(void) +{ + if (T2) + DT0 = DT1; +} + +void OPPROTO op_mov_cc(void) +{ + if (T2) + T0 = T1; +} + +void OPPROTO op_flushw(void) +{ + if (env->cansave != NWINDOWS - 2) { + raise_exception(TT_SPILL | (env->otherwin != 0 ? + (TT_WOTHER | ((env->wstate & 0x38) >> 1)): + ((env->wstate & 0x7) << 2))); + } +} + +void OPPROTO op_saved(void) +{ + env->cansave++; + if (env->otherwin == 0) + env->canrestore--; +} + +void OPPROTO op_restored(void) +{ + env->canrestore++; + if (env->cleanwin < NWINDOWS - 1) + env->cleanwin++; + if (env->otherwin == 0) + env->cansave--; + else + env->otherwin--; +} + +void OPPROTO op_popc(void) +{ + do_popc(); +} + +void OPPROTO op_done(void) +{ + env->pc = env->tnpc[env->tl]; + env->npc = env->tnpc[env->tl] + 4; + env->pstate = env->tstate[env->tl]; + env->tl--; +} + +void OPPROTO op_retry(void) +{ + env->pc = env->tpc[env->tl]; + env->npc = env->tnpc[env->tl]; + env->pstate = env->tstate[env->tl]; + env->tl--; +} + +void OPPROTO op_sir(void) +{ + // XXX + +} + +void OPPROTO op_ld_asi_reg() +{ + T0 += PARAM1; + helper_ld_asi(env->asi, PARAM2, PARAM3); +} + +void OPPROTO op_st_asi_reg() +{ + T0 += PARAM1; + helper_st_asi(env->asi, PARAM2, PARAM3); +} +#endif + void OPPROTO op_ld_asi() { helper_ld_asi(PARAM1, PARAM2, PARAM3); diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 143cc16449..ac307a79b0 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -25,6 +25,13 @@ void do_fabss(void) FT0 = float32_abs(FT1); } +#ifdef TARGET_SPARC64 +void do_fabsd(void) +{ + DT0 = float64_abs(DT1); +} +#endif + void do_fsqrts(void) { FT0 = float32_sqrt(FT1, &env->fp_status); @@ -35,48 +42,185 @@ void do_fsqrtd(void) DT0 = float64_sqrt(DT1, &env->fp_status); } +#define FS 0 void do_fcmps (void) { + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); if (isnan(FT0) || isnan(FT1)) { - T0 = FSR_FCC1 | FSR_FCC0; - env->fsr &= ~(FSR_FCC1 | FSR_FCC0); - env->fsr |= T0; + T0 = (FSR_FCC1 | FSR_FCC0) << FS; if (env->fsr & FSR_NVM) { + env->fsr |= T0; raise_exception(TT_FP_EXCP); } else { env->fsr |= FSR_NVA; } } else if (FT0 < FT1) { - T0 = FSR_FCC0; + T0 = FSR_FCC0 << FS; } else if (FT0 > FT1) { - T0 = FSR_FCC1; + T0 = FSR_FCC1 << FS; } else { T0 = 0; } - env->fsr = T0; + env->fsr |= T0; } void do_fcmpd (void) { + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); + if (isnan(DT0) || isnan(DT1)) { + T0 = (FSR_FCC1 | FSR_FCC0) << FS; + if (env->fsr & FSR_NVM) { + env->fsr |= T0; + raise_exception(TT_FP_EXCP); + } else { + env->fsr |= FSR_NVA; + } + } else if (DT0 < DT1) { + T0 = FSR_FCC0 << FS; + } else if (DT0 > DT1) { + T0 = FSR_FCC1 << FS; + } else { + T0 = 0; + } + env->fsr |= T0; +} + +#ifdef TARGET_SPARC64 +#undef FS +#define FS 22 +void do_fcmps_fcc1 (void) +{ + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); + if (isnan(FT0) || isnan(FT1)) { + T0 = (FSR_FCC1 | FSR_FCC0) << FS; + if (env->fsr & FSR_NVM) { + env->fsr |= T0; + raise_exception(TT_FP_EXCP); + } else { + env->fsr |= FSR_NVA; + } + } else if (FT0 < FT1) { + T0 = FSR_FCC0 << FS; + } else if (FT0 > FT1) { + T0 = FSR_FCC1 << FS; + } else { + T0 = 0; + } + env->fsr |= T0; +} + +void do_fcmpd_fcc1 (void) +{ + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); + if (isnan(DT0) || isnan(DT1)) { + T0 = (FSR_FCC1 | FSR_FCC0) << FS; + if (env->fsr & FSR_NVM) { + env->fsr |= T0; + raise_exception(TT_FP_EXCP); + } else { + env->fsr |= FSR_NVA; + } + } else if (DT0 < DT1) { + T0 = FSR_FCC0 << FS; + } else if (DT0 > DT1) { + T0 = FSR_FCC1 << FS; + } else { + T0 = 0; + } + env->fsr |= T0; +} + +#undef FS +#define FS 24 +void do_fcmps_fcc2 (void) +{ + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); + if (isnan(FT0) || isnan(FT1)) { + T0 = (FSR_FCC1 | FSR_FCC0) << FS; + if (env->fsr & FSR_NVM) { + env->fsr |= T0; + raise_exception(TT_FP_EXCP); + } else { + env->fsr |= FSR_NVA; + } + } else if (FT0 < FT1) { + T0 = FSR_FCC0 << FS; + } else if (FT0 > FT1) { + T0 = FSR_FCC1 << FS; + } else { + T0 = 0; + } + env->fsr |= T0; +} + +void do_fcmpd_fcc2 (void) +{ + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); if (isnan(DT0) || isnan(DT1)) { - T0 = FSR_FCC1 | FSR_FCC0; - env->fsr &= ~(FSR_FCC1 | FSR_FCC0); - env->fsr |= T0; + T0 = (FSR_FCC1 | FSR_FCC0) << FS; if (env->fsr & FSR_NVM) { + env->fsr |= T0; raise_exception(TT_FP_EXCP); } else { env->fsr |= FSR_NVA; } } else if (DT0 < DT1) { - T0 = FSR_FCC0; + T0 = FSR_FCC0 << FS; } else if (DT0 > DT1) { - T0 = FSR_FCC1; + T0 = FSR_FCC1 << FS; + } else { + T0 = 0; + } + env->fsr |= T0; +} + +#undef FS +#define FS 26 +void do_fcmps_fcc3 (void) +{ + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); + if (isnan(FT0) || isnan(FT1)) { + T0 = (FSR_FCC1 | FSR_FCC0) << FS; + if (env->fsr & FSR_NVM) { + env->fsr |= T0; + raise_exception(TT_FP_EXCP); + } else { + env->fsr |= FSR_NVA; + } + } else if (FT0 < FT1) { + T0 = FSR_FCC0 << FS; + } else if (FT0 > FT1) { + T0 = FSR_FCC1 << FS; } else { T0 = 0; } - env->fsr = T0; + env->fsr |= T0; } +void do_fcmpd_fcc3 (void) +{ + env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); + if (isnan(DT0) || isnan(DT1)) { + T0 = (FSR_FCC1 | FSR_FCC0) << FS; + if (env->fsr & FSR_NVM) { + env->fsr |= T0; + raise_exception(TT_FP_EXCP); + } else { + env->fsr |= FSR_NVA; + } + } else if (DT0 < DT1) { + T0 = FSR_FCC0 << FS; + } else if (DT0 > DT1) { + T0 = FSR_FCC1 << FS; + } else { + T0 = 0; + } + env->fsr |= T0; +} +#undef FS +#endif + +#ifndef TARGET_SPARC64 void helper_ld_asi(int asi, int size, int sign) { uint32_t ret; @@ -235,6 +379,255 @@ void helper_st_asi(int asi, int size, int sign) } } +#else + +void helper_ld_asi(int asi, int size, int sign) +{ + uint64_t ret; + + if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) + raise_exception(TT_PRIV_INSN); + + switch (asi) { + case 0x14: // Bypass + case 0x15: // Bypass, non-cacheable + { + cpu_physical_memory_read(T0, (void *) &ret, size); + if (size == 8) + tswap64s(&ret); + if (size == 4) + tswap32s((uint32_t *)&ret); + else if (size == 2) + tswap16s((uint16_t *)&ret); + break; + } + case 0x1c: // Bypass LE + case 0x1d: // Bypass, non-cacheable LE + // XXX + break; + case 0x45: // LSU + ret = env->lsu; + break; + case 0x50: // I-MMU regs + { + int reg = (T0 >> 3) & 0xf; + + ret = env->immuregs[reg]; + break; + } + case 0x51: // I-MMU 8k TSB pointer + case 0x52: // I-MMU 64k TSB pointer + case 0x55: // I-MMU data access + case 0x56: // I-MMU tag read + break; + case 0x58: // D-MMU regs + { + int reg = (T0 >> 3) & 0xf; + + ret = env->dmmuregs[reg]; + break; + } + case 0x59: // D-MMU 8k TSB pointer + case 0x5a: // D-MMU 64k TSB pointer + case 0x5b: // D-MMU data pointer + case 0x5d: // D-MMU data access + case 0x5e: // D-MMU tag read + break; + case 0x54: // I-MMU data in, WO + case 0x57: // I-MMU demap, WO + case 0x5c: // D-MMU data in, WO + case 0x5f: // D-MMU demap, WO + default: + ret = 0; + break; + } + T1 = ret; +} + +void helper_st_asi(int asi, int size, int sign) +{ + if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) + raise_exception(TT_PRIV_INSN); + + switch(asi) { + case 0x14: // Bypass + case 0x15: // Bypass, non-cacheable + { + target_ulong temp = T1; + if (size == 8) + tswap64s(&temp); + else if (size == 4) + tswap32s((uint32_t *)&temp); + else if (size == 2) + tswap16s((uint16_t *)&temp); + cpu_physical_memory_write(T0, (void *) &temp, size); + } + return; + case 0x1c: // Bypass LE + case 0x1d: // Bypass, non-cacheable LE + // XXX + return; + case 0x45: // LSU + { + uint64_t oldreg; + + oldreg = env->lsu; + env->lsu = T1 & (DMMU_E | IMMU_E); + // Mappings generated during D/I MMU disabled mode are + // invalid in normal mode + if (oldreg != env->lsu) + tlb_flush(env, 1); + return; + } + case 0x50: // I-MMU regs + { + int reg = (T0 >> 3) & 0xf; + uint64_t oldreg; + + oldreg = env->immuregs[reg]; + switch(reg) { + case 0: // RO + case 4: + return; + case 1: // Not in I-MMU + case 2: + case 7: + case 8: + return; + case 3: // SFSR + if ((T1 & 1) == 0) + T1 = 0; // Clear SFSR + break; + case 5: // TSB access + case 6: // Tag access + default: + break; + } + env->immuregs[reg] = T1; +#ifdef DEBUG_MMU + if (oldreg != env->immuregs[reg]) { + printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->immuregs[reg]); + } + dump_mmu(); +#endif + return; + } + case 0x54: // I-MMU data in + { + unsigned int i; + + // Try finding an invalid entry + for (i = 0; i < 64; i++) { + if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { + env->itlb_tag[i] = env->immuregs[6]; + env->itlb_tte[i] = T1; + return; + } + } + // Try finding an unlocked entry + for (i = 0; i < 64; i++) { + if ((env->itlb_tte[i] & 0x40) == 0) { + env->itlb_tag[i] = env->immuregs[6]; + env->itlb_tte[i] = T1; + return; + } + } + // error state? + return; + } + case 0x55: // I-MMU data access + { + unsigned int i = (T0 >> 3) & 0x3f; + + env->itlb_tag[i] = env->immuregs[6]; + env->itlb_tte[i] = T1; + return; + } + case 0x57: // I-MMU demap + return; + case 0x58: // D-MMU regs + { + int reg = (T0 >> 3) & 0xf; + uint64_t oldreg; + + oldreg = env->dmmuregs[reg]; + switch(reg) { + case 0: // RO + case 4: + return; + case 3: // SFSR + if ((T1 & 1) == 0) { + T1 = 0; // Clear SFSR, Fault address + env->dmmuregs[4] = 0; + } + env->dmmuregs[reg] = T1; + break; + case 1: // Primary context + case 2: // Secondary context + case 5: // TSB access + case 6: // Tag access + case 7: // Virtual Watchpoint + case 8: // Physical Watchpoint + default: + break; + } + env->dmmuregs[reg] = T1; +#ifdef DEBUG_MMU + if (oldreg != env->dmmuregs[reg]) { + printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->dmmuregs[reg]); + } + dump_mmu(); +#endif + return; + } + case 0x5c: // D-MMU data in + { + unsigned int i; + + // Try finding an invalid entry + for (i = 0; i < 64; i++) { + if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { + env->dtlb_tag[i] = env->dmmuregs[6]; + env->dtlb_tte[i] = T1; + return; + } + } + // Try finding an unlocked entry + for (i = 0; i < 64; i++) { + if ((env->dtlb_tte[i] & 0x40) == 0) { + env->dtlb_tag[i] = env->dmmuregs[6]; + env->dtlb_tte[i] = T1; + return; + } + } + // error state? + return; + } + case 0x5d: // D-MMU data access + { + unsigned int i = (T0 >> 3) & 0x3f; + + env->dtlb_tag[i] = env->dmmuregs[6]; + env->dtlb_tte[i] = T1; + return; + } + case 0x5f: // D-MMU demap + return; + case 0x51: // I-MMU 8k TSB pointer, RO + case 0x52: // I-MMU 64k TSB pointer, RO + case 0x56: // I-MMU tag read, RO + case 0x59: // D-MMU 8k TSB pointer, RO + case 0x5a: // D-MMU 64k TSB pointer, RO + case 0x5b: // D-MMU data pointer, RO + case 0x5e: // D-MMU tag read, RO + default: + return; + } +} + +#endif + +#ifndef TARGET_SPARC64 void helper_rett() { unsigned int cwp; @@ -247,6 +640,7 @@ void helper_rett() set_cwp(cwp); env->psrs = env->psrps; } +#endif void helper_ldfsr(void) { @@ -288,6 +682,7 @@ void helper_debug() cpu_loop_exit(); } +#ifndef TARGET_SPARC64 void do_wrpsr() { PUT_PSR(env, T0); @@ -297,3 +692,16 @@ void do_rdpsr() { T0 = GET_PSR(env); } + +#else + +void do_popc() +{ + T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); + T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); + T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); + T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); + T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); + T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); +} +#endif diff --git a/target-sparc/op_mem.h b/target-sparc/op_mem.h index 9f6ecefd8f..2407c15d8b 100644 --- a/target-sparc/op_mem.h +++ b/target-sparc/op_mem.h @@ -2,9 +2,15 @@ #define SPARC_LD_OP(name, qp) \ void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \ { \ - T1 = glue(qp, MEMSUFFIX)(T0); \ + T1 = (target_ulong)glue(qp, MEMSUFFIX)(T0); \ } +#define SPARC_LD_OP_S(name, qp) \ + void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \ + { \ + T1 = (target_long)glue(qp, MEMSUFFIX)(T0); \ + } + #define SPARC_ST_OP(name, op) \ void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \ { \ @@ -14,8 +20,8 @@ void OPPROTO glue(glue(op_, name), MEMSUFFIX)(void) \ SPARC_LD_OP(ld, ldl); SPARC_LD_OP(ldub, ldub); SPARC_LD_OP(lduh, lduw); -SPARC_LD_OP(ldsb, ldsb); -SPARC_LD_OP(ldsh, ldsw); +SPARC_LD_OP_S(ldsb, ldsb); +SPARC_LD_OP_S(ldsh, ldsw); /*** Integer store ***/ SPARC_ST_OP(st, stl); @@ -68,4 +74,51 @@ void OPPROTO glue(op_lddf, MEMSUFFIX) (void) { DT0 = glue(ldfq, MEMSUFFIX)(T0); } + +#ifdef TARGET_SPARC64 +/* XXX: Should be Atomically */ +/* XXX: There are no cas[x] instructions, only cas[x]a */ +void OPPROTO glue(op_cas, MEMSUFFIX)(void) +{ + uint32_t tmp; + + tmp = glue(ldl, MEMSUFFIX)(T0); + T2 &= 0xffffffffULL; + if (tmp == (T1 & 0xffffffffULL)) { + glue(stl, MEMSUFFIX)(T0, T2); + } + T2 = tmp; +} + +void OPPROTO glue(op_casx, MEMSUFFIX)(void) +{ + uint64_t tmp; + + // XXX + tmp = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32; + tmp |= glue(ldl, MEMSUFFIX)(T0); + if (tmp == T1) { + glue(stq, MEMSUFFIX)(T0, T2); + } + T2 = tmp; +} + +void OPPROTO glue(op_ldsw, MEMSUFFIX)(void) +{ + T1 = (int64_t)glue(ldl, MEMSUFFIX)(T0); +} + +void OPPROTO glue(op_ldx, MEMSUFFIX)(void) +{ + // XXX + T1 = (uint64_t)glue(ldl, MEMSUFFIX)(T0) << 32; + T1 |= glue(ldl, MEMSUFFIX)(T0); +} + +void OPPROTO glue(op_stx, MEMSUFFIX)(void) +{ + glue(stl, MEMSUFFIX)(T0, T1 >> 32); + glue(stl, MEMSUFFIX)(T0, T1 & 0xffffffff); +} +#endif #undef MEMSUFFIX diff --git a/target-sparc/translate.c b/target-sparc/translate.c index f93c3b1ca4..e1c02725fe 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2,7 +2,7 @@ SPARC translation Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at> - Copyright (C) 2003 Fabrice Bellard + Copyright (C) 2003-2005 Fabrice Bellard This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public @@ -22,12 +22,12 @@ /* TODO-list: + Rest of V9 instructions, VIS instructions NPC/PC static optimisations (use JUMP_TB when possible) - FPU-Instructions - Privileged instructions - Coprocessor-Instructions Optimize synthetic instructions - Optional alignment and privileged instruction check + Optional alignment check + 128-bit float + Tagged add/sub */ #include <stdarg.h> @@ -69,9 +69,29 @@ enum { #include "gen-op.h" +// This function uses non-native bit order #define GET_FIELD(X, FROM, TO) \ ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) +// This function uses the order in the manuals, i.e. bit 0 is 2^0 +#define GET_FIELD_SP(X, FROM, TO) \ + GET_FIELD(X, 31 - (TO), 31 - (FROM)) + +#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) +#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1)) + +#ifdef TARGET_SPARC64 +#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e)) +#else +#define DFPREG(r) (r) +#endif + +static int sign_extend(int x, int len) +{ + len = 32 - len; + return (x << len) >> len; +} + #define IS_IMM (insn & (1<<13)) static void disas_sparc_insn(DisasContext * dc); @@ -258,6 +278,34 @@ static GenOpFunc1 *gen_op_movl_TN_im[3] = { gen_op_movl_T2_im }; +// Sign extending version +static GenOpFunc1 * const gen_op_movl_TN_sim[3] = { + gen_op_movl_T0_sim, + gen_op_movl_T1_sim, + gen_op_movl_T2_sim +}; + +#ifdef TARGET_SPARC64 +#define GEN32(func, NAME) \ +static GenOpFunc *NAME ## _table [64] = { \ +NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ +NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ +NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ +NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ +NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ +NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ +NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ +NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ +NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \ +NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \ +NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \ +NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \ +}; \ +static inline void func(int n) \ +{ \ + NAME ## _table[n](); \ +} +#else #define GEN32(func, NAME) \ static GenOpFunc *NAME ## _table [32] = { \ NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ @@ -273,22 +321,77 @@ static inline void func(int n) \ { \ NAME ## _table[n](); \ } +#endif /* floating point registers moves */ GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf); GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf); -GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf); GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf); GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf); -GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf); GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf); GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf); -GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf); GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf); GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf); -GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf); +#ifdef TARGET_SPARC64 +// 'a' versions allowed to user depending on asi +#if defined(CONFIG_USER_ONLY) +#define supervisor(dc) 0 +#define gen_op_ldst(name) gen_op_##name##_raw() +#define OP_LD_TABLE(width) \ + static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ + { \ + int asi, offset; \ + \ + if (IS_IMM) { \ + offset = GET_FIELD(insn, 25, 31); \ + if (is_ld) \ + gen_op_ld_asi_reg(offset, size, sign); \ + else \ + gen_op_st_asi_reg(offset, size, sign); \ + return; \ + } \ + asi = GET_FIELD(insn, 19, 26); \ + switch (asi) { \ + case 0x80: /* Primary address space */ \ + gen_op_##width##_raw(); \ + break; \ + default: \ + break; \ + } \ + } + +#else +#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() +#define OP_LD_TABLE(width) \ + static GenOpFunc *gen_op_##width[] = { \ + &gen_op_##width##_user, \ + &gen_op_##width##_kernel, \ + }; \ + \ + static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ + { \ + int asi, offset; \ + \ + if (IS_IMM) { \ + offset = GET_FIELD(insn, 25, 31); \ + if (is_ld) \ + gen_op_ld_asi_reg(offset, size, sign); \ + else \ + gen_op_st_asi_reg(offset, size, sign); \ + return; \ + } \ + asi = GET_FIELD(insn, 19, 26); \ + if (is_ld) \ + gen_op_ld_asi(asi, size, sign); \ + else \ + gen_op_st_asi(asi, size, sign); \ + } + +#define supervisor(dc) (dc->mem_idx == 1) +#endif +#else #if defined(CONFIG_USER_ONLY) #define gen_op_ldst(name) gen_op_##name##_raw() #define OP_LD_TABLE(width) @@ -330,6 +433,7 @@ static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \ #define supervisor(dc) (dc->mem_idx == 1) #endif +#endif OP_LD_TABLE(ld); OP_LD_TABLE(st); @@ -348,21 +452,44 @@ OP_LD_TABLE(stdf); OP_LD_TABLE(ldf); OP_LD_TABLE(lddf); -static inline void gen_movl_imm_TN(int reg, int imm) +#ifdef TARGET_SPARC64 +OP_LD_TABLE(ldsw); +OP_LD_TABLE(ldx); +OP_LD_TABLE(stx); +OP_LD_TABLE(cas); +OP_LD_TABLE(casx); +#endif + +static inline void gen_movl_imm_TN(int reg, uint32_t imm) { gen_op_movl_TN_im[reg] (imm); } -static inline void gen_movl_imm_T1(int val) +static inline void gen_movl_imm_T1(uint32_t val) { gen_movl_imm_TN(1, val); } -static inline void gen_movl_imm_T0(int val) +static inline void gen_movl_imm_T0(uint32_t val) { gen_movl_imm_TN(0, val); } +static inline void gen_movl_simm_TN(int reg, int32_t imm) +{ + gen_op_movl_TN_sim[reg](imm); +} + +static inline void gen_movl_simm_T1(int32_t val) +{ + gen_movl_simm_TN(1, val); +} + +static inline void gen_movl_simm_T0(int32_t val) +{ + gen_movl_simm_TN(0, val); +} + static inline void gen_movl_reg_TN(int reg, int t) { if (reg) @@ -411,19 +538,45 @@ static inline void flush_T2(DisasContext * dc) } } +static inline void gen_jmp_im(target_ulong pc) +{ +#ifdef TARGET_SPARC64 + if (pc == (uint32_t)pc) { + gen_op_jmp_im(pc); + } else { + gen_op_jmp_im64(pc >> 32, pc); + } +#else + gen_op_jmp_im(pc); +#endif +} + +static inline void gen_movl_npc_im(target_ulong npc) +{ +#ifdef TARGET_SPARC64 + if (npc == (uint32_t)npc) { + gen_op_movl_npc_im(npc); + } else { + gen_op_movq_npc_im64(npc >> 32, npc); + } +#else + gen_op_movl_npc_im(npc); +#endif +} + static inline void save_npc(DisasContext * dc) { if (dc->npc == JUMP_PC) { gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); dc->npc = DYNAMIC_PC; } else if (dc->npc != DYNAMIC_PC) { - gen_op_movl_npc_im(dc->npc); + gen_movl_npc_im(dc->npc); } } static inline void save_state(DisasContext * dc) { - gen_op_jmp_im(dc->pc); + gen_jmp_im(dc->pc); save_npc(dc); } @@ -441,110 +594,159 @@ static inline void gen_mov_pc_npc(DisasContext * dc) } } -static void gen_cond(int cond) -{ - switch (cond) { - case 0x1: - gen_op_eval_be(); - break; - case 0x2: - gen_op_eval_ble(); - break; - case 0x3: - gen_op_eval_bl(); - break; - case 0x4: - gen_op_eval_bleu(); - break; - case 0x5: - gen_op_eval_bcs(); - break; - case 0x6: - gen_op_eval_bneg(); - break; - case 0x7: - gen_op_eval_bvs(); - break; - case 0x9: - gen_op_eval_bne(); - break; - case 0xa: - gen_op_eval_bg(); - break; - case 0xb: - gen_op_eval_bge(); - break; - case 0xc: - gen_op_eval_bgu(); - break; - case 0xd: - gen_op_eval_bcc(); - break; - case 0xe: - gen_op_eval_bpos(); - break; - default: - case 0xf: - gen_op_eval_bvc(); - break; - } -} +static GenOpFunc * const gen_cond[2][16] = { + { + gen_op_eval_ba, + gen_op_eval_be, + gen_op_eval_ble, + gen_op_eval_bl, + gen_op_eval_bleu, + gen_op_eval_bcs, + gen_op_eval_bneg, + gen_op_eval_bvs, + gen_op_eval_bn, + gen_op_eval_bne, + gen_op_eval_bg, + gen_op_eval_bge, + gen_op_eval_bgu, + gen_op_eval_bcc, + gen_op_eval_bpos, + gen_op_eval_bvc, + }, + { +#ifdef TARGET_SPARC64 + gen_op_eval_ba, + gen_op_eval_xbe, + gen_op_eval_xble, + gen_op_eval_xbl, + gen_op_eval_xbleu, + gen_op_eval_xbcs, + gen_op_eval_xbneg, + gen_op_eval_xbvs, + gen_op_eval_bn, + gen_op_eval_xbne, + gen_op_eval_xbg, + gen_op_eval_xbge, + gen_op_eval_xbgu, + gen_op_eval_xbcc, + gen_op_eval_xbpos, + gen_op_eval_xbvc, +#endif + }, +}; + +static GenOpFunc * const gen_fcond[4][16] = { + { + gen_op_eval_ba, + gen_op_eval_fbne, + gen_op_eval_fblg, + gen_op_eval_fbul, + gen_op_eval_fbl, + gen_op_eval_fbug, + gen_op_eval_fbg, + gen_op_eval_fbu, + gen_op_eval_bn, + gen_op_eval_fbe, + gen_op_eval_fbue, + gen_op_eval_fbge, + gen_op_eval_fbuge, + gen_op_eval_fble, + gen_op_eval_fbule, + gen_op_eval_fbo, + }, +#ifdef TARGET_SPARC64 + { + gen_op_eval_ba, + gen_op_eval_fbne_fcc1, + gen_op_eval_fblg_fcc1, + gen_op_eval_fbul_fcc1, + gen_op_eval_fbl_fcc1, + gen_op_eval_fbug_fcc1, + gen_op_eval_fbg_fcc1, + gen_op_eval_fbu_fcc1, + gen_op_eval_bn, + gen_op_eval_fbe_fcc1, + gen_op_eval_fbue_fcc1, + gen_op_eval_fbge_fcc1, + gen_op_eval_fbuge_fcc1, + gen_op_eval_fble_fcc1, + gen_op_eval_fbule_fcc1, + gen_op_eval_fbo_fcc1, + }, + { + gen_op_eval_ba, + gen_op_eval_fbne_fcc2, + gen_op_eval_fblg_fcc2, + gen_op_eval_fbul_fcc2, + gen_op_eval_fbl_fcc2, + gen_op_eval_fbug_fcc2, + gen_op_eval_fbg_fcc2, + gen_op_eval_fbu_fcc2, + gen_op_eval_bn, + gen_op_eval_fbe_fcc2, + gen_op_eval_fbue_fcc2, + gen_op_eval_fbge_fcc2, + gen_op_eval_fbuge_fcc2, + gen_op_eval_fble_fcc2, + gen_op_eval_fbule_fcc2, + gen_op_eval_fbo_fcc2, + }, + { + gen_op_eval_ba, + gen_op_eval_fbne_fcc3, + gen_op_eval_fblg_fcc3, + gen_op_eval_fbul_fcc3, + gen_op_eval_fbl_fcc3, + gen_op_eval_fbug_fcc3, + gen_op_eval_fbg_fcc3, + gen_op_eval_fbu_fcc3, + gen_op_eval_bn, + gen_op_eval_fbe_fcc3, + gen_op_eval_fbue_fcc3, + gen_op_eval_fbge_fcc3, + gen_op_eval_fbuge_fcc3, + gen_op_eval_fble_fcc3, + gen_op_eval_fbule_fcc3, + gen_op_eval_fbo_fcc3, + }, +#else + {}, {}, {}, +#endif +}; -static void gen_fcond(int cond) +#ifdef TARGET_SPARC64 +static void gen_cond_reg(int cond) { switch (cond) { case 0x1: - gen_op_eval_fbne(); + gen_op_eval_brz(); break; case 0x2: - gen_op_eval_fblg(); + gen_op_eval_brlez(); break; case 0x3: - gen_op_eval_fbul(); - break; - case 0x4: - gen_op_eval_fbl(); + gen_op_eval_brlz(); break; case 0x5: - gen_op_eval_fbug(); + gen_op_eval_brnz(); break; case 0x6: - gen_op_eval_fbg(); - break; - case 0x7: - gen_op_eval_fbu(); - break; - case 0x9: - gen_op_eval_fbe(); - break; - case 0xa: - gen_op_eval_fbue(); - break; - case 0xb: - gen_op_eval_fbge(); - break; - case 0xc: - gen_op_eval_fbuge(); - break; - case 0xd: - gen_op_eval_fble(); - break; - case 0xe: - gen_op_eval_fbule(); + gen_op_eval_brgz(); break; default: - case 0xf: - gen_op_eval_fbo(); + case 0x7: + gen_op_eval_brgez(); break; } } +#endif /* XXX: potentially incorrect if dynamic npc */ -static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn) +static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) { unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); target_ulong target = dc->pc + offset; - + if (cond == 0x0) { /* unconditional not taken */ if (a) { @@ -565,7 +767,7 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn) } } else { flush_T2(dc); - gen_cond(cond); + gen_cond[cc][cond](); if (a) { gen_op_branch_a((long)dc->tb, target, dc->npc); dc->is_br = 1; @@ -579,7 +781,7 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn) } /* XXX: potentially incorrect if dynamic npc */ -static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn) +static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) { unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); target_ulong target = dc->pc + offset; @@ -604,7 +806,7 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn) } } else { flush_T2(dc); - gen_fcond(cond); + gen_fcond[cc][cond](); if (a) { gen_op_branch_a((long)dc->tb, target, dc->npc); dc->is_br = 1; @@ -617,14 +819,41 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn) } } -#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) - -static int sign_extend(int x, int len) +#ifdef TARGET_SPARC64 +/* XXX: potentially incorrect if dynamic npc */ +static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) { - len = 32 - len; - return (x << len) >> len; + unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); + target_ulong target = dc->pc + offset; + + flush_T2(dc); + gen_cond_reg(cond); + if (a) { + gen_op_branch_a((long)dc->tb, target, dc->npc); + dc->is_br = 1; + } else { + dc->pc = dc->npc; + dc->jump_pc[0] = target; + dc->jump_pc[1] = dc->npc + 4; + dc->npc = JUMP_PC; + } } +static GenOpFunc * const gen_fcmps[4] = { + gen_op_fcmps, + gen_op_fcmps_fcc1, + gen_op_fcmps_fcc2, + gen_op_fcmps_fcc3, +}; + +static GenOpFunc * const gen_fcmpd[4] = { + gen_op_fcmpd, + gen_op_fcmpd_fcc1, + gen_op_fcmpd_fcc2, + gen_op_fcmpd_fcc3, +}; +#endif + /* before an instruction, dc->pc must be static */ static void disas_sparc_insn(DisasContext * dc) { @@ -639,19 +868,54 @@ static void disas_sparc_insn(DisasContext * dc) { unsigned int xop = GET_FIELD(insn, 7, 9); int32_t target; - target = GET_FIELD(insn, 10, 31); switch (xop) { - case 0x0: /* UNIMPL */ +#ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ + { + int cc; + + target = GET_FIELD_SP(insn, 0, 18); + target <<= 2; + target = sign_extend(target, 18); + cc = GET_FIELD_SP(insn, 20, 21); + if (cc == 0) + do_branch(dc, target, insn, 0); + else if (cc == 2) + do_branch(dc, target, insn, 1); + else + goto illegal_insn; + goto jmp_insn; + } case 0x3: /* V9 BPr */ + { + target = GET_FIELD_SP(insn, 0, 13) | + (GET_FIELD_SP(insn, 20, 21) >> 7); + target <<= 2; + target = sign_extend(target, 16); + rs1 = GET_FIELD(insn, 13, 17); + gen_movl_T0_reg(rs1); + do_branch_reg(dc, target, insn); + goto jmp_insn; + } case 0x5: /* V9 FBPcc */ - default: - goto illegal_insn; + { + int cc = GET_FIELD_SP(insn, 20, 21); +#if !defined(CONFIG_USER_ONLY) + gen_op_trap_ifnofpu(); +#endif + target = GET_FIELD_SP(insn, 0, 18); + target <<= 2; + target = sign_extend(target, 19); + do_fbranch(dc, target, insn, cc); + goto jmp_insn; + } +#endif case 0x2: /* BN+x */ { + target = GET_FIELD(insn, 10, 31); target <<= 2; target = sign_extend(target, 22); - do_branch(dc, target, insn); + do_branch(dc, target, insn, 0); goto jmp_insn; } case 0x6: /* FBN+x */ @@ -659,9 +923,10 @@ static void disas_sparc_insn(DisasContext * dc) #if !defined(CONFIG_USER_ONLY) gen_op_trap_ifnofpu(); #endif + target = GET_FIELD(insn, 10, 31); target <<= 2; target = sign_extend(target, 22); - do_fbranch(dc, target, insn); + do_fbranch(dc, target, insn, 0); goto jmp_insn; } case 0x4: /* SETHI */ @@ -669,12 +934,16 @@ static void disas_sparc_insn(DisasContext * dc) #if defined(OPTIM) if (rd) { // nop #endif - gen_movl_imm_T0(target << 10); + uint32_t value = GET_FIELD(insn, 10, 31); + gen_movl_imm_T0(value << 10); gen_movl_T0_reg(rd); #if defined(OPTIM) } #endif break; + case 0x0: /* UNIMPL */ + default: + goto illegal_insn; } break; } @@ -695,6 +964,7 @@ static void disas_sparc_insn(DisasContext * dc) unsigned int xop = GET_FIELD(insn, 7, 12); if (xop == 0x3a) { /* generate trap */ int cond; + rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); if (IS_IMM) { @@ -702,7 +972,7 @@ static void disas_sparc_insn(DisasContext * dc) #if defined(OPTIM) if (rs2 != 0) { #endif - gen_movl_imm_T1(rs2); + gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } @@ -719,51 +989,141 @@ static void disas_sparc_insn(DisasContext * dc) #endif } save_state(dc); - /* V9 icc/xcc */ cond = GET_FIELD(insn, 3, 6); if (cond == 0x8) { gen_op_trap_T0(); dc->is_br = 1; goto jmp_insn; } else if (cond != 0) { - gen_cond(cond); +#ifdef TARGET_SPARC64 + /* V9 icc/xcc */ + int cc = GET_FIELD_SP(insn, 11, 12); + if (cc == 0) + gen_cond[0][cond](); + else if (cc == 2) + gen_cond[1][cond](); + else + goto illegal_insn; +#else + gen_cond[0][cond](); +#endif gen_op_trapcc_T0(); } } else if (xop == 0x28) { rs1 = GET_FIELD(insn, 13, 17); switch(rs1) { case 0: /* rdy */ - gen_op_rdy(); + gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); gen_movl_T0_reg(rd); break; case 15: /* stbar / V9 membar */ break; /* no effect? */ - default: +#ifdef TARGET_SPARC64 case 0x2: /* V9 rdccr */ + gen_op_rdccr(); + gen_movl_T0_reg(rd); + break; case 0x3: /* V9 rdasi */ + gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); + gen_movl_T0_reg(rd); + break; case 0x4: /* V9 rdtick */ + gen_op_rdtick(); + gen_movl_T0_reg(rd); + break; case 0x5: /* V9 rdpc */ + gen_op_movl_T0_im(dc->pc); + gen_movl_T0_reg(rd); + break; case 0x6: /* V9 rdfprs */ + gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); + gen_movl_T0_reg(rd); + break; +#endif + default: goto illegal_insn; } #if !defined(CONFIG_USER_ONLY) - } else if (xop == 0x29) { +#ifndef TARGET_SPARC64 + } else if (xop == 0x29) { /* rdpsr / V9 unimp */ if (!supervisor(dc)) goto priv_insn; gen_op_rdpsr(); gen_movl_T0_reg(rd); break; - } else if (xop == 0x2a) { +#endif + } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) goto priv_insn; - gen_op_rdwim(); +#ifdef TARGET_SPARC64 + rs1 = GET_FIELD(insn, 13, 17); + switch (rs1) { + case 0: // tpc + gen_op_rdtpc(); + break; + case 1: // tnpc + gen_op_rdtnpc(); + break; + case 2: // tstate + gen_op_rdtstate(); + break; + case 3: // tt + gen_op_rdtt(); + break; + case 4: // tick + gen_op_rdtick(); + break; + case 5: // tba + gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); + break; + case 6: // pstate + gen_op_rdpstate(); + break; + case 7: // tl + gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); + break; + case 8: // pil + gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); + break; + case 9: // cwp + gen_op_rdcwp(); + break; + case 10: // cansave + gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); + break; + case 11: // canrestore + gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); + break; + case 12: // cleanwin + gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); + break; + case 13: // otherwin + gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); + break; + case 14: // wstate + gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); + break; + case 31: // ver + gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); + break; + case 15: // fq + default: + goto illegal_insn; + } +#else + gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); +#endif gen_movl_T0_reg(rd); break; - } else if (xop == 0x2b) { + } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ +#ifdef TARGET_SPARC64 + gen_op_flushw(); +#else if (!supervisor(dc)) goto priv_insn; - gen_op_rdtbr(); + gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); gen_movl_T0_reg(rd); +#endif break; #endif } else if (xop == 0x34) { /* FPU Operations */ @@ -794,9 +1154,9 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_store_FT0_fpr(rd); break; case 0x2a: /* fsqrtd */ - gen_op_load_fpr_DT1(rs2); + gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsqrtd(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x2b: /* fsqrtq */ goto nfpu_insn; @@ -807,10 +1167,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_store_FT0_fpr(rd); break; case 0x42: - gen_op_load_fpr_DT0(rs1); - gen_op_load_fpr_DT1(rs2); + gen_op_load_fpr_DT0(DFPREG(rs1)); + gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_faddd(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x43: /* faddq */ goto nfpu_insn; @@ -821,10 +1181,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_store_FT0_fpr(rd); break; case 0x46: - gen_op_load_fpr_DT0(rs1); - gen_op_load_fpr_DT1(rs2); + gen_op_load_fpr_DT0(DFPREG(rs1)); + gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fsubd(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x47: /* fsubq */ goto nfpu_insn; @@ -835,8 +1195,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_store_FT0_fpr(rd); break; case 0x4a: - gen_op_load_fpr_DT0(rs1); - gen_op_load_fpr_DT1(rs2); + gen_op_load_fpr_DT0(DFPREG(rs1)); + gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fmuld(); gen_op_store_DT0_fpr(rd); break; @@ -849,10 +1209,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_store_FT0_fpr(rd); break; case 0x4e: - gen_op_load_fpr_DT0(rs1); - gen_op_load_fpr_DT1(rs2); + gen_op_load_fpr_DT0(DFPREG(rs1)); + gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdivd(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x4f: /* fdivq */ goto nfpu_insn; @@ -860,7 +1220,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); gen_op_fsmuld(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6e: /* fdmulq */ goto nfpu_insn; @@ -870,7 +1230,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_store_FT0_fpr(rd); break; case 0xc6: - gen_op_load_fpr_DT1(rs2); + gen_op_load_fpr_DT1(DFPREG(rs2)); gen_op_fdtos(); gen_op_store_FT0_fpr(rd); break; @@ -879,12 +1239,12 @@ static void disas_sparc_insn(DisasContext * dc) case 0xc8: gen_op_load_fpr_FT1(rs2); gen_op_fitod(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xc9: gen_op_load_fpr_FT1(rs2); gen_op_fstod(); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xcb: /* fqtod */ goto nfpu_insn; @@ -906,55 +1266,248 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0xd3: /* fqtoi */ goto nfpu_insn; - default: +#ifdef TARGET_SPARC64 case 0x2: /* V9 fmovd */ + gen_op_load_fpr_DT0(DFPREG(rs2)); + gen_op_store_DT0_fpr(DFPREG(rd)); + break; case 0x6: /* V9 fnegd */ + gen_op_load_fpr_DT1(DFPREG(rs2)); + gen_op_fnegd(); + gen_op_store_DT0_fpr(DFPREG(rd)); + break; case 0xa: /* V9 fabsd */ + gen_op_load_fpr_DT1(DFPREG(rs2)); + gen_op_fabsd(); + gen_op_store_DT0_fpr(DFPREG(rd)); + break; case 0x81: /* V9 fstox */ + gen_op_load_fpr_FT1(rs2); + gen_op_fstox(); + gen_op_store_DT0_fpr(DFPREG(rd)); + break; case 0x82: /* V9 fdtox */ + gen_op_load_fpr_DT1(DFPREG(rs2)); + gen_op_fdtox(); + gen_op_store_DT0_fpr(DFPREG(rd)); + break; case 0x84: /* V9 fxtos */ + gen_op_load_fpr_DT1(DFPREG(rs2)); + gen_op_fxtos(); + gen_op_store_FT0_fpr(rd); + break; case 0x88: /* V9 fxtod */ - + gen_op_load_fpr_DT1(DFPREG(rs2)); + gen_op_fxtod(); + gen_op_store_DT0_fpr(DFPREG(rd)); + break; case 0x3: /* V9 fmovq */ case 0x7: /* V9 fnegq */ case 0xb: /* V9 fabsq */ case 0x83: /* V9 fqtox */ case 0x8c: /* V9 fxtoq */ + goto nfpu_insn; +#endif + default: goto illegal_insn; } } else if (xop == 0x35) { /* FPU Operations */ +#ifdef TARGET_SPARC64 + int cond; +#endif #if !defined(CONFIG_USER_ONLY) gen_op_trap_ifnofpu(); #endif rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); - /* V9 fmovscc: x5, cond = x >> 1 */ - /* V9 fmovdcc: x6, cond = x >> 1 */ - - /* V9 fmovqcc: x7, cond = x >> 1 */ +#ifdef TARGET_SPARC64 + if ((xop & 0x11f) == 0x005) { // V9 fmovsr + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + rs1 = GET_FIELD(insn, 13, 17); + gen_movl_reg_T0(rs1); + flush_T2(dc); + gen_cond_reg(cond); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + rs1 = GET_FIELD(insn, 13, 17); + gen_movl_reg_T0(rs1); + gen_cond_reg(cond); + gen_op_fmovs_cc(); + gen_op_store_DT0_fpr(rd); + break; + } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr + goto nfpu_insn; + } +#endif switch (xop) { - case 0x51: +#ifdef TARGET_SPARC64 + case 0x001: /* V9 fmovscc %fcc0 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + flush_T2(dc); + gen_fcond[0][cond](); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + case 0x002: /* V9 fmovdcc %fcc0 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + gen_fcond[0][cond](); + gen_op_fmovd_cc(); + gen_op_store_DT0_fpr(rd); + break; + case 0x003: /* V9 fmovqcc %fcc0 */ + goto nfpu_insn; + case 0x041: /* V9 fmovscc %fcc1 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + flush_T2(dc); + gen_fcond[1][cond](); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + case 0x042: /* V9 fmovdcc %fcc1 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + gen_fcond[1][cond](); + gen_op_fmovd_cc(); + gen_op_store_DT0_fpr(rd); + break; + case 0x043: /* V9 fmovqcc %fcc1 */ + goto nfpu_insn; + case 0x081: /* V9 fmovscc %fcc2 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + flush_T2(dc); + gen_fcond[2][cond](); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + case 0x082: /* V9 fmovdcc %fcc2 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + gen_fcond[2][cond](); + gen_op_fmovd_cc(); + gen_op_store_DT0_fpr(rd); + break; + case 0x083: /* V9 fmovqcc %fcc2 */ + goto nfpu_insn; + case 0x0c1: /* V9 fmovscc %fcc3 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + flush_T2(dc); + gen_fcond[3][cond](); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + case 0x0c2: /* V9 fmovdcc %fcc3 */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + gen_fcond[3][cond](); + gen_op_fmovd_cc(); + gen_op_store_DT0_fpr(rd); + break; + case 0x0c3: /* V9 fmovqcc %fcc3 */ + goto nfpu_insn; + case 0x101: /* V9 fmovscc %icc */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + flush_T2(dc); + gen_cond[0][cond](); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + case 0x102: /* V9 fmovdcc %icc */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + gen_cond[0][cond](); + gen_op_fmovd_cc(); + gen_op_store_DT0_fpr(rd); + break; + case 0x103: /* V9 fmovqcc %icc */ + goto nfpu_insn; + case 0x181: /* V9 fmovscc %xcc */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_FT0(rd); + gen_op_load_fpr_FT1(rs2); + flush_T2(dc); + gen_cond[1][cond](); + gen_op_fmovs_cc(); + gen_op_store_FT0_fpr(rd); + break; + case 0x182: /* V9 fmovdcc %xcc */ + cond = GET_FIELD_SP(insn, 14, 17); + gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT1(rs2); + flush_T2(dc); + gen_cond[1][cond](); + gen_op_fmovd_cc(); + gen_op_store_DT0_fpr(rd); + break; + case 0x183: /* V9 fmovqcc %xcc */ + goto nfpu_insn; +#endif + case 0x51: /* V9 %fcc */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); +#ifdef TARGET_SPARC64 + gen_fcmps[rd & 3](); +#else gen_op_fcmps(); +#endif break; - case 0x52: - gen_op_load_fpr_DT0(rs1); - gen_op_load_fpr_DT1(rs2); + case 0x52: /* V9 %fcc */ + gen_op_load_fpr_DT0(DFPREG(rs1)); + gen_op_load_fpr_DT1(DFPREG(rs2)); +#ifdef TARGET_SPARC64 + gen_fcmpd[rd & 3](); +#else gen_op_fcmpd(); +#endif break; case 0x53: /* fcmpq */ goto nfpu_insn; - case 0x55: /* fcmpes */ + case 0x55: /* fcmpes, V9 %fcc */ gen_op_load_fpr_FT0(rs1); gen_op_load_fpr_FT1(rs2); +#ifdef TARGET_SPARC64 + gen_fcmps[rd & 3](); +#else gen_op_fcmps(); /* XXX should trap if qNaN or sNaN */ +#endif break; - case 0x56: /* fcmped */ - gen_op_load_fpr_DT0(rs1); - gen_op_load_fpr_DT1(rs2); + case 0x56: /* fcmped, V9 %fcc */ + gen_op_load_fpr_DT0(DFPREG(rs1)); + gen_op_load_fpr_DT1(DFPREG(rs2)); +#ifdef TARGET_SPARC64 + gen_fcmpd[rd & 3](); +#else gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN */ +#endif break; case 0x57: /* fcmpeq */ goto nfpu_insn; @@ -970,7 +1523,7 @@ static void disas_sparc_insn(DisasContext * dc) // or %g0, x, y -> mov T1, x; mov y, T1 if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); - gen_movl_imm_T1(rs2); + gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); @@ -982,7 +1535,7 @@ static void disas_sparc_insn(DisasContext * dc) // or x, #0, y -> mov T1, x; mov y, T1 rs2 = GET_FIELDs(insn, 19, 31); if (rs2 != 0) { - gen_movl_imm_T1(rs2); + gen_movl_simm_T1(rs2); gen_op_or_T1_T0(); } } else { /* register */ @@ -1001,7 +1554,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_reg_T0(rs1); if (IS_IMM) { /* immediate */ rs2 = GET_FIELDs(insn, 19, 31); - gen_movl_imm_T1(rs2); + gen_movl_simm_T1(rs2); } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); gen_movl_reg_T1(rs2); @@ -1083,13 +1636,21 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_div_cc(); break; default: - case 0x9: /* V9 mulx */ - case 0xd: /* V9 udivx */ goto illegal_insn; } gen_movl_T0_reg(rd); } else { switch (xop) { +#ifdef TARGET_SPARC64 + case 0x9: /* V9 mulx */ + gen_op_mulx_T1_T0(); + gen_movl_T0_reg(rd); + break; + case 0xd: /* V9 udivx */ + gen_op_udivx_T1_T0(); + gen_movl_T0_reg(rd); + break; +#endif case 0x20: /* taddcc */ case 0x21: /* tsubcc */ case 0x22: /* taddcctv */ @@ -1099,30 +1660,67 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_mulscc_T1_T0(); gen_movl_T0_reg(rd); break; - case 0x25: /* sll, V9 sllx */ - gen_op_sll(); + case 0x25: /* sll, V9 sllx ( == sll) */ + gen_op_sll(); gen_movl_T0_reg(rd); break; case 0x26: /* srl, V9 srlx */ - gen_op_srl(); +#ifdef TARGET_SPARC64 + if (insn & (1 << 12)) + gen_op_srlx(); + else + gen_op_srl(); +#else + gen_op_srl(); +#endif gen_movl_T0_reg(rd); break; case 0x27: /* sra, V9 srax */ - gen_op_sra(); +#ifdef TARGET_SPARC64 + if (insn & (1 << 12)) + gen_op_srax(); + else + gen_op_sra(); +#else + gen_op_sra(); +#endif gen_movl_T0_reg(rd); break; case 0x30: { - gen_op_xor_T1_T0(); switch(rd) { - case 0: - gen_op_wry(); + case 0: /* wry */ + gen_op_xor_T1_T0(); + gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); break; - default: +#ifdef TARGET_SPARC64 case 0x2: /* V9 wrccr */ + gen_op_wrccr(); + break; case 0x3: /* V9 wrasi */ + gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); + break; case 0x6: /* V9 wrfprs */ - case 0xf: /* V9 sir */ + gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); + break; + case 0xf: /* V9 sir, nop if user */ +#if !defined(CONFIG_USER_ONLY) + if (supervisor(dc)) + gen_op_sir(); +#endif + break; +#endif + case 0x10: /* Performance Control */ + case 0x11: /* Performance Instrumentation Counter */ + case 0x12: /* Dispatch Control */ + case 0x13: /* Graphics Status */ + case 0x14: /* Softint set */ + case 0x15: /* Softint clear */ + case 0x16: /* Softint write */ + case 0x17: /* Tick compare */ + case 0x18: /* System tick */ + case 0x19: /* System tick compare */ + default: goto illegal_insn; } } @@ -1132,8 +1730,21 @@ static void disas_sparc_insn(DisasContext * dc) { if (!supervisor(dc)) goto priv_insn; +#ifdef TARGET_SPARC64 + switch (rd) { + case 0: + gen_op_saved(); + break; + case 1: + gen_op_restored(); + break; + default: + goto illegal_insn; + } +#else gen_op_xor_T1_T0(); gen_op_wrpsr(); +#endif } break; case 0x32: /* wrwim, V9 wrpr */ @@ -1141,28 +1752,179 @@ static void disas_sparc_insn(DisasContext * dc) if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); - gen_op_wrwim(); +#ifdef TARGET_SPARC64 + switch (rd) { + case 0: // tpc + gen_op_wrtpc(); + break; + case 1: // tnpc + gen_op_wrtnpc(); + break; + case 2: // tstate + gen_op_wrtstate(); + break; + case 3: // tt + gen_op_wrtt(); + break; + case 4: // tick + gen_op_wrtick(); + break; + case 5: // tba + gen_op_movl_env_T0(offsetof(CPUSPARCState, tbr)); + break; + case 6: // pstate + gen_op_wrpstate(); + break; + case 7: // tl + gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); + break; + case 8: // pil + gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); + break; + case 9: // cwp + gen_op_wrcwp(); + break; + case 10: // cansave + gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); + break; + case 11: // canrestore + gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); + break; + case 12: // cleanwin + gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); + break; + case 13: // otherwin + gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); + break; + case 14: // wstate + gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); + break; + default: + goto illegal_insn; + } +#else + gen_op_movl_env_T0(offsetof(CPUSPARCState, wim)); +#endif } break; - case 0x33: +#ifndef TARGET_SPARC64 + case 0x33: /* wrtbr, V9 unimp */ { if (!supervisor(dc)) goto priv_insn; gen_op_xor_T1_T0(); - gen_op_wrtbr(); + gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); } break; #endif - default: - case 0x2a: /* V9 rdpr */ - case 0x2b: /* V9 flushw */ +#endif +#ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ + { + int cc = GET_FIELD_SP(insn, 11, 12); + int cond = GET_FIELD_SP(insn, 14, 17); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELD_SPs(insn, 0, 10); + gen_movl_simm_T1(rs2); + } + else { + rs2 = GET_FIELD_SP(insn, 0, 4); + gen_movl_reg_T1(rs2); + } + gen_movl_reg_T0(rd); + flush_T2(dc); + if (insn & (1 << 18)) { + if (cc == 0) + gen_cond[0][cond](); + else if (cc == 2) + gen_cond[1][cond](); + else + goto illegal_insn; + } else { + gen_fcond[cc][cond](); + } + gen_op_mov_cc(); + gen_movl_T0_reg(rd); + break; + } case 0x2d: /* V9 sdivx */ + gen_op_sdivx_T1_T0(); + gen_movl_T0_reg(rd); + break; case 0x2e: /* V9 popc */ + { + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELD_SPs(insn, 0, 12); + gen_movl_simm_T1(rs2); + // XXX optimize: popc(constant) + } + else { + rs2 = GET_FIELD_SP(insn, 0, 4); + gen_movl_reg_T1(rs2); + } + gen_op_popc(); + gen_movl_T0_reg(rd); + } case 0x2f: /* V9 movr */ + { + int cond = GET_FIELD_SP(insn, 10, 12); + rs1 = GET_FIELD(insn, 13, 17); + flush_T2(dc); + gen_movl_reg_T0(rs1); + gen_cond_reg(cond); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELD_SPs(insn, 0, 10); + gen_movl_simm_T1(rs2); + } + else { + rs2 = GET_FIELD_SP(insn, 0, 4); + gen_movl_reg_T1(rs2); + } + gen_movl_reg_T0(rd); + gen_op_mov_cc(); + gen_movl_T0_reg(rd); + break; + } + case 0x36: /* UltraSparc shutdown, VIS */ + { + // XXX + } +#endif + default: goto illegal_insn; } } +#ifdef TARGET_SPARC64 + } else if (xop == 0x39) { /* V9 return */ + gen_op_restore(); + rs1 = GET_FIELD(insn, 13, 17); + gen_movl_reg_T0(rs1); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 19, 31); +#if defined(OPTIM) + if (rs2) { +#endif + gen_movl_simm_T1(rs2); + gen_op_add_T1_T0(); +#if defined(OPTIM) + } +#endif + } else { /* register */ + rs2 = GET_FIELD(insn, 27, 31); +#if defined(OPTIM) + if (rs2) { +#endif + gen_movl_reg_T1(rs2); + gen_op_add_T1_T0(); +#if defined(OPTIM) + } +#endif + } + gen_mov_pc_npc(dc); + gen_op_movl_npc_T0(); + dc->npc = DYNAMIC_PC; + goto jmp_insn; +#endif } else { rs1 = GET_FIELD(insn, 13, 17); gen_movl_reg_T0(rs1); @@ -1171,7 +1933,7 @@ static void disas_sparc_insn(DisasContext * dc) #if defined(OPTIM) if (rs2) { #endif - gen_movl_imm_T1(rs2); + gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } @@ -1199,7 +1961,7 @@ static void disas_sparc_insn(DisasContext * dc) dc->npc = DYNAMIC_PC; } goto jmp_insn; -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: /* rett, V9 return */ { if (!supervisor(dc)) @@ -1224,8 +1986,27 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_restore(); gen_movl_T0_reg(rd); break; - default: +#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) case 0x3e: /* V9 done/retry */ + { + switch (rd) { + case 0: + if (!supervisor(dc)) + goto priv_insn; + gen_op_done(); + break; + case 1: + if (!supervisor(dc)) + goto priv_insn; + gen_op_retry(); + break; + default: + goto illegal_insn; + } + } + break; +#endif + default: goto illegal_insn; } } @@ -1242,7 +2023,7 @@ static void disas_sparc_insn(DisasContext * dc) #if defined(OPTIM) if (rs2 != 0) { #endif - gen_movl_imm_T1(rs2); + gen_movl_simm_T1(rs2); gen_op_add_T1_T0(); #if defined(OPTIM) } @@ -1258,8 +2039,9 @@ static void disas_sparc_insn(DisasContext * dc) } #endif } - if (xop < 4 || (xop > 7 && xop < 0x14) || \ - (xop > 0x17 && xop < 0x20)) { + if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \ + (xop > 0x17 && xop < 0x1d ) || \ + (xop > 0x2c && xop < 0x33) || xop == 0x1f) { switch (xop) { case 0x0: /* load word */ gen_op_ldst(ld); @@ -1287,72 +2069,115 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_reg_T1(rd); gen_op_ldst(swap); break; -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x10: /* load word alternate */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_lda(insn, 1, 4, 0); break; case 0x11: /* load unsigned byte alternate */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_lduba(insn, 1, 1, 0); break; case 0x12: /* load unsigned halfword alternate */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_lduha(insn, 1, 2, 0); break; case 0x13: /* load double word alternate */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_ldda(insn, 1, 8, 0); gen_movl_T0_reg(rd + 1); break; case 0x19: /* load signed byte alternate */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_ldsba(insn, 1, 1, 1); break; case 0x1a: /* load signed halfword alternate */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_ldsha(insn, 1, 2 ,1); break; case 0x1d: /* ldstuba -- XXX: should be atomically */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_ldstuba(insn, 1, 1, 0); break; case 0x1f: /* swap reg with alt. memory. Also atomically */ +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_movl_reg_T1(rd); gen_op_swapa(insn, 1, 4, 0); break; - + +#ifndef TARGET_SPARC64 /* avoid warnings */ (void) &gen_op_stfa; (void) &gen_op_stdfa; (void) &gen_op_ldfa; (void) &gen_op_lddfa; +#else +#if !defined(CONFIG_USER_ONLY) + (void) &gen_op_cas; + (void) &gen_op_casx; #endif - default: +#endif +#endif +#ifdef TARGET_SPARC64 case 0x08: /* V9 ldsw */ + gen_op_ldst(ldsw); + break; case 0x0b: /* V9 ldx */ + gen_op_ldst(ldx); + break; case 0x18: /* V9 ldswa */ + gen_op_ldswa(insn, 1, 4, 1); + break; case 0x1b: /* V9 ldxa */ - case 0x2d: /* V9 prefetch */ + gen_op_ldxa(insn, 1, 8, 0); + break; + case 0x2d: /* V9 prefetch, no effect */ + goto skip_move; case 0x30: /* V9 ldfa */ + gen_op_ldfa(insn, 1, 8, 0); // XXX + break; case 0x33: /* V9 lddfa */ - case 0x3d: /* V9 prefetcha */ + gen_op_lddfa(insn, 1, 8, 0); // XXX + break; + case 0x3d: /* V9 prefetcha, no effect */ + goto skip_move; case 0x32: /* V9 ldqfa */ + goto nfpu_insn; +#endif + default: goto illegal_insn; } gen_movl_T1_reg(rd); +#ifdef TARGET_SPARC64 + skip_move: ; +#endif } else if (xop >= 0x20 && xop < 0x24) { -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) gen_op_trap_ifnofpu(); #endif switch (xop) { @@ -1368,12 +2193,13 @@ static void disas_sparc_insn(DisasContext * dc) goto nfpu_insn; case 0x23: /* load double fpreg */ gen_op_ldst(lddf); - gen_op_store_DT0_fpr(rd); + gen_op_store_DT0_fpr(DFPREG(rd)); break; default: goto illegal_insn; } - } else if (xop < 8 || (xop >= 0x14 && xop < 0x18)) { + } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ + xop == 0xe || xop == 0x1e) { gen_movl_reg_T1(rd); switch (xop) { case 0x4: @@ -1390,33 +2216,47 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_reg_T2(rd + 1); gen_op_ldst(std); break; -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_sta(insn, 0, 4, 0); break; case 0x15: +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_stba(insn, 0, 1, 0); break; case 0x16: +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif gen_op_stha(insn, 0, 2, 0); break; case 0x17: +#ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; +#endif flush_T2(dc); gen_movl_reg_T2(rd + 1); gen_op_stda(insn, 0, 8, 0); break; #endif - default: +#ifdef TARGET_SPARC64 case 0x0e: /* V9 stx */ + gen_op_ldst(stx); + break; case 0x1e: /* V9 stxa */ + gen_op_stxa(insn, 0, 8, 0); // XXX + break; +#endif + default: goto illegal_insn; } } else if (xop > 0x23 && xop < 0x28) { @@ -1430,26 +2270,41 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x25: /* stfsr, V9 stxfsr */ gen_op_load_fpr_FT0(rd); + // XXX gen_op_stfsr(); break; case 0x26: /* stdfq */ goto nfpu_insn; case 0x27: - gen_op_load_fpr_DT0(rd); + gen_op_load_fpr_DT0(DFPREG(rd)); gen_op_ldst(stdf); break; default: + goto illegal_insn; + } + } else if (xop > 0x33 && xop < 0x3f) { +#ifdef TARGET_SPARC64 + switch (xop) { case 0x34: /* V9 stfa */ + gen_op_stfa(insn, 0, 0, 0); // XXX + break; case 0x37: /* V9 stdfa */ + gen_op_stdfa(insn, 0, 0, 0); // XXX + break; case 0x3c: /* V9 casa */ + gen_op_casa(insn, 0, 4, 0); // XXX + break; case 0x3e: /* V9 casxa */ - + gen_op_casxa(insn, 0, 8, 0); // XXX + break; case 0x36: /* V9 stqfa */ + goto nfpu_insn; + default: goto illegal_insn; } - } else if (xop > 0x33 && xop < 0x38) { - /* Co-processor */ +#else goto illegal_insn; +#endif } else goto illegal_insn; @@ -1540,6 +2395,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, } last_pc = dc->pc; disas_sparc_insn(dc); + if (dc->is_br) break; /* if the next PC is different, we abort now */ @@ -1552,7 +2408,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, /* if single step mode, we generate only one instruction and generate an exception */ if (env->singlestep_enabled) { - gen_op_jmp_im(dc->pc); + gen_jmp_im(dc->pc); gen_op_movl_T0_0(); gen_op_exit_tb(); break; @@ -1568,7 +2424,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, gen_op_branch((long)tb, dc->pc, dc->npc); } else { if (dc->pc != DYNAMIC_PC) - gen_op_jmp_im(dc->pc); + gen_jmp_im(dc->pc); save_npc(dc); gen_op_movl_T0_0(); gen_op_exit_tb(); @@ -1633,8 +2489,13 @@ void cpu_reset(CPUSPARCState *env) env->psrps = 1; env->pc = 0xffd00000; env->gregs[1] = ram_size; - env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */ env->npc = env->pc + 4; +#ifdef TARGET_SPARC64 + env->pstate = PS_AM | PS_PRIV; // XXX: Force AM + env->version = GET_VER(env); +#else + env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */ +#endif #endif } @@ -1692,7 +2553,7 @@ void cpu_dump_state(CPUState *env, FILE *f, GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), env->psrs?'S':'-', env->psrps?'P':'-', env->psret?'E':'-', env->wim); - cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr); + cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); } #if defined(CONFIG_USER_ONLY) |