diff options
Diffstat (limited to 'target-unicore32/cpu.h')
| -rw-r--r-- | target-unicore32/cpu.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index f725634801..a3f8589205 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -18,7 +18,7 @@ #define ELF_MACHINE EM_UNICORE32 -#define CPUState struct CPUState_UniCore32 +#define CPUArchState struct CPUUniCore32State #include "config.h" #include "qemu-common.h" @@ -27,7 +27,7 @@ #define NB_MMU_MODES 2 -typedef struct CPUState_UniCore32 { +typedef struct CPUUniCore32State { /* Regs for current mode. */ uint32_t regs[32]; /* Frequently accessed ASR bits are stored separately for efficiently. @@ -71,7 +71,7 @@ typedef struct CPUState_UniCore32 { /* Internal CPU feature flags. */ uint32_t features; -} CPUState_UniCore32; +} CPUUniCore32State; #define ASR_M (0x1f) #define ASR_MODE_USER (0x10) @@ -92,9 +92,9 @@ typedef struct CPUState_UniCore32 { #define UC32_EXCP_TRAP (ASR_MODE_TRAP) /* Return the current ASR value. */ -target_ulong cpu_asr_read(CPUState *env1); +target_ulong cpu_asr_read(CPUUniCore32State *env1); /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */ -void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask); +void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask); /* UniCore-F64 system registers. */ #define UC32_UCF64_FPSCR (31) @@ -128,10 +128,10 @@ void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask); #define cpu_signal_handler uc32_cpu_signal_handler #define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault -CPUState *uc32_cpu_init(const char *cpu_model); -int uc32_cpu_exec(CPUState *s); +CPUUniCore32State *uc32_cpu_init(const char *cpu_model); +int uc32_cpu_exec(CPUUniCore32State *s); int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc); -int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, +int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw, int mmu_idx); #define CPU_SAVE_VERSION 2 @@ -140,12 +140,12 @@ int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_USER_IDX 1 -static inline int cpu_mmu_index(CPUState *env) +static inline int cpu_mmu_index(CPUUniCore32State *env) { return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0; } -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUUniCore32State *env, target_ulong newsp) { if (newsp) { env->regs[29] = newsp; @@ -153,7 +153,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) env->regs[0] = 0; } -static inline void cpu_set_tls(CPUState *env, target_ulong newtls) +static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls) { env->regs[16] = newtls; } @@ -161,12 +161,12 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls) #include "cpu-all.h" #include "exec-all.h" -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb) { env->regs[31] = tb->pc; } -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc, target_ulong *cs_base, int *flags) { *pc = env->regs[31]; @@ -178,10 +178,10 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, } void uc32_translate_init(void); -void do_interrupt(CPUState *); -void switch_mode(CPUState_UniCore32 *, int); +void do_interrupt(CPUUniCore32State *); +void switch_mode(CPUUniCore32State *, int); -static inline bool cpu_has_work(CPUState *env) +static inline bool cpu_has_work(CPUUniCore32State *env) { return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); |