diff options
Diffstat (limited to 'target/hppa/mem_helper.c')
| -rw-r--r-- | target/hppa/mem_helper.c | 179 |
1 files changed, 152 insertions, 27 deletions
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 46c3dcaf15..520fd311f8 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -41,16 +41,24 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) return NULL; } -static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) +static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent, + bool force_flush_btlb) { CPUState *cs = env_cpu(env); - unsigned i, n = 1 << (2 * ent->page_size); - uint64_t addr = ent->va_b; + + if (!ent->entry_valid) { + return; + } trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa); - for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) { - tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK); + tlb_flush_range_by_mmuidx(cs, ent->va_b, + ent->va_e - ent->va_b + 1, + HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS); + + /* never clear BTLBs, unless forced to do so. */ + if (ent < &env->tlb[HPPA_BTLB_ENTRIES] && !force_flush_btlb) { + return; } memset(ent, 0, sizeof(*ent)); @@ -60,23 +68,35 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env) { hppa_tlb_entry *ent; - uint32_t i = env->tlb_last; + uint32_t i; + + if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >= ARRAY_SIZE(env->tlb)) { + i = HPPA_BTLB_ENTRIES; + env->tlb_last = HPPA_BTLB_ENTRIES + 1; + } else { + i = env->tlb_last; + env->tlb_last++; + } - env->tlb_last = (i == ARRAY_SIZE(env->tlb) - 1 ? 0 : i + 1); ent = &env->tlb[i]; - hppa_flush_tlb_ent(env, ent); + hppa_flush_tlb_ent(env, ent, false); return ent; } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot) + int type, hwaddr *pphys, int *pprot, + hppa_tlb_entry **tlb_entry) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; hppa_tlb_entry *ent; int ret = -1; + if (tlb_entry) { + *tlb_entry = NULL; + } + /* Virtual translation disabled. Direct map virtual to physical. */ if (mmu_idx == MMU_PHYS_IDX) { phys = addr; @@ -93,8 +113,12 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } + if (tlb_entry) { + *tlb_entry = ent; + } + /* We now know the physical address. */ - phys = ent->pa + (addr & ~TARGET_PAGE_MASK); + phys = ent->pa + (addr - ent->va_b); /* Map TLB access_rights field to QEMU protection. */ priv = MMU_IDX_TO_PRIV(mmu_idx); @@ -193,7 +217,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } excp = hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, 0, - &phys, &prot); + &phys, &prot, NULL); /* Since we're translating for debugging, the only error that is a hard error is no translation at all. Otherwise, while a real cpu @@ -207,6 +231,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; + hppa_tlb_entry *ent; int prot, excp, a_prot; hwaddr phys; @@ -223,7 +248,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, } excp = hppa_get_physical_address(env, addr, mmu_idx, - a_prot, &phys, &prot); + a_prot, &phys, &prot, &ent); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -243,7 +268,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, phys & TARGET_PAGE_MASK, size, type, mmu_idx); /* Success! Store the translation into the QEMU TLB. */ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + prot, mmu_idx, TARGET_PAGE_SIZE << (ent ? 2 * ent->page_size : 0)); return true; } @@ -254,11 +279,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) int i; /* Zap any old entries covering ADDR; notice empty entries on the way. */ - for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) { + for (i = HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent = &env->tlb[i]; if (ent->va_b <= addr && addr <= ent->va_e) { if (ent->entry_valid) { - hppa_flush_tlb_ent(env, ent); + hppa_flush_tlb_ent(env, ent, false); } if (!empty) { empty = ent; @@ -278,16 +303,8 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa); } -/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ -void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg reg) { - hppa_tlb_entry *ent = hppa_find_tlb(env, addr); - - if (unlikely(ent == NULL)) { - qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); - return; - } - ent->access_id = extract32(reg, 1, 18); ent->u = extract32(reg, 19, 1); ent->ar_pl2 = extract32(reg, 20, 2); @@ -301,6 +318,19 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) ent->ar_pl1, ent->ar_type, ent->b, ent->d, ent->t); } +/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ +void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +{ + hppa_tlb_entry *ent = hppa_find_tlb(env, addr); + + if (unlikely(ent == NULL)) { + qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); + return; + } + + set_access_bits(env, ent, reg); +} + /* Purge (Insn/Data) TLB. This is explicitly page-based, and is synchronous across all processors. */ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) @@ -310,7 +340,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) hppa_tlb_entry *ent = hppa_find_tlb(env, addr); if (ent && ent->entry_valid) { - hppa_flush_tlb_ent(env, ent); + hppa_flush_tlb_ent(env, ent, false); } } @@ -334,7 +364,10 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) void HELPER(ptlbe)(CPUHPPAState *env) { trace_hppa_tlb_ptlbe(env); - memset(env->tlb, 0, sizeof(env->tlb)); + qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n"); + memset(&env->tlb[HPPA_BTLB_ENTRIES], 0, + sizeof(env->tlb) - HPPA_BTLB_ENTRIES * sizeof(env->tlb[0])); + env->tlb_last = HPPA_BTLB_ENTRIES; tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); } @@ -356,7 +389,7 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) int prot, excp; excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, - &phys, &prot); + &phys, &prot, NULL); if (excp >= 0) { if (env->psw & PSW_Q) { /* ??? Needs tweaking for hppa64. */ @@ -379,3 +412,95 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr); return ent ? ent->ar_type : -1; } + +/* + * diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to + * allow operating systems to modify the Block TLB (BTLB) entries. + * For implementation details see page 1-13 in + * https://parisc.wiki.kernel.org/images-parisc/e/ef/Pdc11-v0.96-Ch1-procs.pdf + */ +void HELPER(diag_btlb)(CPUHPPAState *env) +{ + unsigned int phys_page, len, slot; + int mmu_idx = cpu_mmu_index(env, 0); + uintptr_t ra = GETPC(); + hppa_tlb_entry *btlb; + uint64_t virt_page; + uint32_t *vaddr; + +#ifdef TARGET_HPPA64 + /* BTLBs are not supported on 64-bit CPUs */ + env->gr[28] = -1; /* nonexistent procedure */ + return; +#endif + env->gr[28] = 0; /* PDC_OK */ + + switch (env->gr[25]) { + case 0: + /* return BTLB parameters */ + qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INFO\n"); + vaddr = probe_access(env, env->gr[24], 4 * sizeof(target_ulong), + MMU_DATA_STORE, mmu_idx, ra); + if (vaddr == NULL) { + env->gr[28] = -10; /* invalid argument */ + } else { + vaddr[0] = cpu_to_be32(1); + vaddr[1] = cpu_to_be32(16 * 1024); + vaddr[2] = cpu_to_be32(HPPA_BTLB_FIXED); + vaddr[3] = cpu_to_be32(HPPA_BTLB_VARIABLE); + } + break; + case 1: + /* insert BTLB entry */ + virt_page = env->gr[24]; /* upper 32 bits */ + virt_page <<= 32; + virt_page |= env->gr[23]; /* lower 32 bits */ + phys_page = env->gr[22]; + len = env->gr[21]; + slot = env->gr[19]; + qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INSERT " + "0x%08llx-0x%08llx: vpage 0x%llx for phys page 0x%04x len %d " + "into slot %d\n", + (long long) virt_page << TARGET_PAGE_BITS, + (long long) (virt_page + len) << TARGET_PAGE_BITS, + (long long) virt_page, phys_page, len, slot); + if (slot < HPPA_BTLB_ENTRIES) { + btlb = &env->tlb[slot]; + /* force flush of possibly existing BTLB entry */ + hppa_flush_tlb_ent(env, btlb, true); + /* create new BTLB entry */ + btlb->va_b = virt_page << TARGET_PAGE_BITS; + btlb->va_e = btlb->va_b + len * TARGET_PAGE_SIZE - 1; + btlb->pa = phys_page << TARGET_PAGE_BITS; + set_access_bits(env, btlb, env->gr[20]); + btlb->t = 0; + btlb->d = 1; + } else { + env->gr[28] = -10; /* invalid argument */ + } + break; + case 2: + /* Purge BTLB entry */ + slot = env->gr[22]; + qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\n", + slot); + if (slot < HPPA_BTLB_ENTRIES) { + btlb = &env->tlb[slot]; + hppa_flush_tlb_ent(env, btlb, true); + } else { + env->gr[28] = -10; /* invalid argument */ + } + break; + case 3: + /* Purge all BTLB entries */ + qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n"); + for (slot = 0; slot < HPPA_BTLB_ENTRIES; slot++) { + btlb = &env->tlb[slot]; + hppa_flush_tlb_ent(env, btlb, true); + } + break; + default: + env->gr[28] = -2; /* nonexistent option */ + break; + } +} |