diff options
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/cpu.h | 2 | ||||
| -rw-r--r-- | target/mips/internal.h | 3 | ||||
| -rw-r--r-- | target/mips/trace-events | 2 | ||||
| -rw-r--r-- | target/mips/translate.c | 85 | ||||
| -rw-r--r-- | target/mips/translate_init.inc.c | 5 |
5 files changed, 48 insertions, 49 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0de3..1f41cf66d5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1065,7 +1065,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) #define ENV_OFFSET offsetof(MIPSCPU, env) -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); +void mips_cpu_list(void); #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list diff --git a/target/mips/internal.h b/target/mips/internal.h index 8f6fc919d5..286e3888ab 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -76,8 +76,7 @@ enum CPUMIPSMSADataFormat { void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, - int flags); +void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/mips/trace-events b/target/mips/trace-events index 05eafd7870..ba87fe6062 100644 --- a/target/mips/trace-events +++ b/target/mips/trace-events @@ -1,5 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. -# target/mips/translate.c +# translate.c mips_translate_c0(const char *instr, const char *rn, int reg, int sel) "%s %s (reg %d sel %d)" mips_translate_tr(const char *instr, int rt, int u, int sel, int h) "%s (reg %d u %d sel %d h %d)" diff --git a/target/mips/translate.c b/target/mips/translate.c index 364bd6dc4f..f96c0d01ef 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -38,6 +38,7 @@ #include "trace-tcg.h" #include "exec/translator.h" #include "exec/log.h" +#include "qemu/qemu-print.h" #define MIPS_DEBUG_DISAS 0 @@ -29720,15 +29721,14 @@ static const TranslatorOps mips_tr_ops = { .disas_log = mips_tr_disas_log, }; -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) { DisasContext ctx; - translator_loop(&mips_tr_ops, &ctx.base, cs, tb); + translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } -static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf, - int flags) +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { int i; int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); @@ -29736,68 +29736,69 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fpri #define printfpr(fp) \ do { \ if (is_fpu64) \ - fpu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu: %13g\n", \ + (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ + (double)(fp)->fd, \ + (double)(fp)->fs[FP_ENDIAN_IDX], \ + (double)(fp)->fs[!FP_ENDIAN_IDX]); \ else { \ fpr_t tmp; \ tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - fpu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ + qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ + " fd:%13g fs:%13g psu:%13g\n", \ + tmp.w[FP_ENDIAN_IDX], tmp.d, \ + (double)tmp.fd, \ + (double)tmp.fs[FP_ENDIAN_IDX], \ + (double)tmp.fs[!FP_ENDIAN_IDX]); \ } \ } while(0) - fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { - fpu_fprintf(f, "%3s: ", fregnames[i]); + qemu_fprintf(f, "%3s: ", fregnames[i]); printfpr(&env->active_fpu.fpr[i]); } #undef printfpr } -void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, - int flags) +void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; int i; - cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx - " LO=0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], - env->hflags, env->btarget, env->bcond); + qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx + " LO=0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], + env->hflags, env->btarget, env->bcond); for (i = 0; i < 32; i++) { if ((i & 3) == 0) - cpu_fprintf(f, "GPR%02d:", i); - cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]); + qemu_fprintf(f, "GPR%02d:", i); + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); if ((i & 3) == 3) - cpu_fprintf(f, "\n"); - } - - cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); + qemu_fprintf(f, "\n"); + } + + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, cpu_fprintf, flags); + fpu_dump_state(env, f, flags); } } diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index bf559aff08..1c2d017d36 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -835,13 +835,12 @@ const mips_def_t mips_defs[] = }; const int mips_defs_number = ARRAY_SIZE(mips_defs); -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf) +void mips_cpu_list(void) { int i; for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { - (*cpu_fprintf)(f, "MIPS '%s'\n", - mips_defs[i].name); + qemu_printf("MIPS '%s'\n", mips_defs[i].name); } } |