diff options
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 50 |
1 files changed, 34 insertions, 16 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 508ef568b4..418a0e6960 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -32,7 +32,7 @@ struct OpenRISCCPU; #include "fpu/softfloat.h" #include "qom/cpu.h" -#define TYPE_OPENRISC_CPU "or32-cpu" +#define TYPE_OPENRISC_CPU "or1k-cpu" #define OPENRISC_CPU_CLASS(klass) \ OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU) @@ -58,6 +58,7 @@ typedef struct OpenRISCCPUClass { } OpenRISCCPUClass; #define NB_MMU_MODES 3 +#define TARGET_INSN_START_EXTRA_WORDS 1 enum { MMU_NOMMU_IDX = 0, @@ -82,9 +83,6 @@ enum { /* Version Register */ #define SPR_VR 0xFFFF003F -/* Internal flags, delay slot flag */ -#define D_FLAG 1 - /* Interrupt */ #define NR_IRQS 32 @@ -273,20 +271,18 @@ typedef struct CPUOpenRISCTLBContext { typedef struct CPUOpenRISCState { target_ulong gpr[32]; /* General registers */ target_ulong pc; /* Program counter */ - target_ulong npc; /* Next PC */ target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ - target_ulong machi; /* Multiply register MACHI */ - target_ulong maclo; /* Multiply register MACLO */ - - target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */ - target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */ + uint64_t mac; /* Multiply registers MACHI:MACLO */ target_ulong epcr; /* Exception PC register */ target_ulong eear; /* Exception EA register */ - uint32_t sr; /* Supervisor register */ + target_ulong sr_f; /* the SR_F bit, values 0, 1. */ + target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ + target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ + uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ @@ -296,9 +292,10 @@ typedef struct CPUOpenRISCState { uint32_t fpcsr; /* Float register */ float_status fp_status; - uint32_t flags; /* cpu_flags, we only use it for exception - in solt so far. */ - uint32_t btaken; /* the SR_F bit */ + target_ulong lock_addr; + target_ulong lock_value; + + uint32_t dflag; /* In delay slot (boolean) */ /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -391,14 +388,19 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, #include "exec/cpu-all.h" +#define TB_FLAGS_DFLAG 1 +#define TB_FLAGS_R0_0 2 +#define TB_FLAGS_OVE SR_OVE + static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; *cs_base = 0; - /* D_FLAG -- branch instruction exception */ - *flags = (env->flags & D_FLAG); + *flags = (env->dflag + | (env->gpr[0] == 0 ? TB_FLAGS_R0_0 : 0) + | (env->sr & SR_OVE)); } static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) @@ -409,6 +411,22 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } +static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) +{ + return (env->sr + + env->sr_f * SR_F + + env->sr_cy * SR_CY + + (env->sr_ov < 0) * SR_OV); +} + +static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) +{ + env->sr_f = (val & SR_F) != 0; + env->sr_cy = (val & SR_CY) != 0; + env->sr_ov = (val & SR_OV ? -1 : 0); + env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; +} + #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 #endif /* OPENRISC_CPU_H */ |