diff options
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/cpu-qom.h | 5 | ||||
| -rw-r--r-- | target/ppc/excp_helper.c | 4 | ||||
| -rw-r--r-- | target/ppc/fpu_helper.c | 220 | ||||
| -rw-r--r-- | target/ppc/machine.c | 4 | ||||
| -rw-r--r-- | target/ppc/mmu-hash64.c | 2 | ||||
| -rw-r--r-- | target/ppc/mmu_helper.c | 15 | ||||
| -rw-r--r-- | target/ppc/translate.c | 4 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-impl.c.inc | 46 | ||||
| -rw-r--r-- | target/ppc/translate_init.c.inc | 61 |
9 files changed, 171 insertions, 190 deletions
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 5fdb96f04d..63b9e8632c 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -74,6 +74,11 @@ enum powerpc_mmu_t { POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, }; +static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) +{ + return mmu_model & POWERPC_MMU_64; +} + /*****************************************************************************/ /* Exception model */ typedef enum powerpc_excp_t powerpc_excp_t; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 74f987080f..85de7e6c90 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -266,7 +266,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) */ if (excp == POWERPC_EXCP_HV_EMU #if defined(TARGET_PPC64) - && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB)) + && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) #endif /* defined(TARGET_PPC64) */ ) { @@ -824,7 +824,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) vector = (uint32_t)vector; } } else { - if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { + if (!msr_isf && !mmu_is_64bit(env->mmu_model)) { vector = (uint32_t)vector; } else { new_msr |= (target_ulong)1 << MSR_SF; diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 32a9a8a0f8..44315fca0b 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2467,101 +2467,135 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode, do_float_check_status(env, GETPC()); } -#define VSX_SCALAR_CMP(op, ordered) \ -void helper_##op(CPUPPCState *env, uint32_t opcode, \ - ppc_vsr_t *xa, ppc_vsr_t *xb) \ -{ \ - uint32_t cc = 0; \ - bool vxsnan_flag = false, vxvc_flag = false; \ - \ - helper_reset_fpstatus(env); \ - \ - if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \ - float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \ - vxsnan_flag = true; \ - cc = CRF_SO; \ - if (fpscr_ve == 0 && ordered) { \ - vxvc_flag = true; \ - } \ - } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \ - float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \ - cc = CRF_SO; \ - if (ordered) { \ - vxvc_flag = true; \ - } \ - } \ - if (vxsnan_flag) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ - if (vxvc_flag) { \ - float_invalid_op_vxvc(env, 0, GETPC()); \ - } \ - \ - if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ - cc |= CRF_LT; \ - } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ - cc |= CRF_GT; \ - } else { \ - cc |= CRF_EQ; \ - } \ - \ - env->fpscr &= ~FP_FPCC; \ - env->fpscr |= cc << FPSCR_FPCC; \ - env->crf[BF(opcode)] = cc; \ - \ - do_float_check_status(env, GETPC()); \ -} - -VSX_SCALAR_CMP(xscmpodp, 1) -VSX_SCALAR_CMP(xscmpudp, 0) - -#define VSX_SCALAR_CMPQ(op, ordered) \ -void helper_##op(CPUPPCState *env, uint32_t opcode, \ - ppc_vsr_t *xa, ppc_vsr_t *xb) \ -{ \ - uint32_t cc = 0; \ - bool vxsnan_flag = false, vxvc_flag = false; \ - \ - helper_reset_fpstatus(env); \ - \ - if (float128_is_signaling_nan(xa->f128, &env->fp_status) || \ - float128_is_signaling_nan(xb->f128, &env->fp_status)) { \ - vxsnan_flag = true; \ - cc = CRF_SO; \ - if (fpscr_ve == 0 && ordered) { \ - vxvc_flag = true; \ - } \ - } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) || \ - float128_is_quiet_nan(xb->f128, &env->fp_status)) { \ - cc = CRF_SO; \ - if (ordered) { \ - vxvc_flag = true; \ - } \ - } \ - if (vxsnan_flag) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ - if (vxvc_flag) { \ - float_invalid_op_vxvc(env, 0, GETPC()); \ - } \ - \ - if (float128_lt(xa->f128, xb->f128, &env->fp_status)) { \ - cc |= CRF_LT; \ - } else if (!float128_le(xa->f128, xb->f128, &env->fp_status)) { \ - cc |= CRF_GT; \ - } else { \ - cc |= CRF_EQ; \ - } \ - \ - env->fpscr &= ~FP_FPCC; \ - env->fpscr |= cc << FPSCR_FPCC; \ - env->crf[BF(opcode)] = cc; \ - \ - do_float_check_status(env, GETPC()); \ +static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb, + int crf_idx, bool ordered) +{ + uint32_t cc; + bool vxsnan_flag = false, vxvc_flag = false; + + helper_reset_fpstatus(env); + + switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { + case float_relation_less: + cc = CRF_LT; + break; + case float_relation_equal: + cc = CRF_EQ; + break; + case float_relation_greater: + cc = CRF_GT; + break; + case float_relation_unordered: + cc = CRF_SO; + + if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || + float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { + vxsnan_flag = true; + if (fpscr_ve == 0 && ordered) { + vxvc_flag = true; + } + } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || + float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { + if (ordered) { + vxvc_flag = true; + } + } + + break; + default: + g_assert_not_reached(); + } + + env->fpscr &= ~FP_FPCC; + env->fpscr |= cc << FPSCR_FPCC; + env->crf[crf_idx] = cc; + + if (vxsnan_flag) { + float_invalid_op_vxsnan(env, GETPC()); + } + if (vxvc_flag) { + float_invalid_op_vxvc(env, 0, GETPC()); + } + + do_float_check_status(env, GETPC()); +} + +void helper_xscmpodp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa, + ppc_vsr_t *xb) +{ + do_scalar_cmp(env, xa, xb, BF(opcode), true); +} + +void helper_xscmpudp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa, + ppc_vsr_t *xb) +{ + do_scalar_cmp(env, xa, xb, BF(opcode), false); +} + +static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa, + ppc_vsr_t *xb, int crf_idx, bool ordered) +{ + uint32_t cc; + bool vxsnan_flag = false, vxvc_flag = false; + + helper_reset_fpstatus(env); + + switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) { + case float_relation_less: + cc = CRF_LT; + break; + case float_relation_equal: + cc = CRF_EQ; + break; + case float_relation_greater: + cc = CRF_GT; + break; + case float_relation_unordered: + cc = CRF_SO; + + if (float128_is_signaling_nan(xa->f128, &env->fp_status) || + float128_is_signaling_nan(xb->f128, &env->fp_status)) { + vxsnan_flag = true; + if (fpscr_ve == 0 && ordered) { + vxvc_flag = true; + } + } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) || + float128_is_quiet_nan(xb->f128, &env->fp_status)) { + if (ordered) { + vxvc_flag = true; + } + } + + break; + default: + g_assert_not_reached(); + } + + env->fpscr &= ~FP_FPCC; + env->fpscr |= cc << FPSCR_FPCC; + env->crf[crf_idx] = cc; + + if (vxsnan_flag) { + float_invalid_op_vxsnan(env, GETPC()); + } + if (vxvc_flag) { + float_invalid_op_vxvc(env, 0, GETPC()); + } + + do_float_check_status(env, GETPC()); } -VSX_SCALAR_CMPQ(xscmpoqp, 1) -VSX_SCALAR_CMPQ(xscmpuqp, 0) +void helper_xscmpoqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa, + ppc_vsr_t *xb) +{ + do_scalar_cmpq(env, xa, xb, BF(opcode), true); +} + +void helper_xscmpuqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa, + ppc_vsr_t *xb) +{ + do_scalar_cmpq(env, xa, xb, BF(opcode), false); +} /* * VSX_MAX_MIN - VSX floating point maximum/minimum diff --git a/target/ppc/machine.c b/target/ppc/machine.c index c38e7b1268..d9d911b9b1 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -550,7 +550,7 @@ static bool sr_needed(void *opaque) #ifdef TARGET_PPC64 PowerPCCPU *cpu = opaque; - return !(cpu->env.mmu_model & POWERPC_MMU_64); + return !mmu_is_64bit(cpu->env.mmu_model); #else return true; #endif @@ -606,7 +606,7 @@ static bool slb_needed(void *opaque) PowerPCCPU *cpu = opaque; /* We don't support any of the old segment table based 64-bit CPUs */ - return cpu->env.mmu_model & POWERPC_MMU_64; + return mmu_is_64bit(cpu->env.mmu_model); } static int slb_post_load(void *opaque, int version_id) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 1b1248fc90..0fabc10302 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1140,7 +1140,7 @@ void ppc_hash64_init(PowerPCCPU *cpu) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); if (!pcc->hash64_opts) { - assert(!(env->mmu_model & POWERPC_MMU_64)); + assert(!mmu_is_64bit(env->mmu_model)); return; } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 064d2e8d13..ca88658cba 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1349,11 +1349,12 @@ void dump_mmu(CPUPPCState *env) break; case POWERPC_MMU_3_00: if (ppc64_v3_radix(env_archcpu(env))) { - /* TODO - Unsupported */ + qemu_log_mask(LOG_UNIMP, "%s: the PPC64 MMU is unsupported\n", + __func__); } else { dump_slb(env_archcpu(env)); - break; } + break; #endif default: qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__); @@ -2001,7 +2002,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) void ppc_tlb_invalidate_all(CPUPPCState *env) { #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { + if (mmu_is_64bit(env->mmu_model)) { env->tlb_need_flush = 0; tlb_flush(env_cpu(env)); } else @@ -2045,7 +2046,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #if !defined(FLUSH_ALL_TLBS) addr &= TARGET_PAGE_MASK; #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { + if (mmu_is_64bit(env->mmu_model)) { /* tlbie invalidate TLBs for all segments */ /* * XXX: given the fact that there are too many segments to invalidate, @@ -2090,7 +2091,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!cpu->vhyp); #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { + if (mmu_is_64bit(env->mmu_model)) { target_ulong sdr_mask = SDR_64_HTABORG | SDR_64_HTABSIZE; target_ulong htabsize = value & SDR_64_HTABSIZE; @@ -2143,7 +2144,7 @@ void ppc_store_ptcr(CPUPPCState *env, target_ulong value) target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num) { #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { + if (mmu_is_64bit(env->mmu_model)) { /* XXX */ return 0; } @@ -2157,7 +2158,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) "%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { + if (mmu_is_64bit(env->mmu_model)) { PowerPCCPU *cpu = env_archcpu(env); uint64_t esid, vsid; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 54cac0e6a7..0984ce637b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7892,7 +7892,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->insns_flags = env->insns_flags; ctx->insns_flags2 = env->insns_flags2; ctx->access_type = -1; - ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); + ctx->need_access_type = !mmu_is_64bit(env->mmu_model); ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; ctx->flags = env->flags; @@ -7902,7 +7902,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #endif ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B || env->mmu_model == POWERPC_MMU_601 - || (env->mmu_model & POWERPC_MMU_64B); + || env->mmu_model & POWERPC_MMU_64; ctx->fpu_enabled = !!msr_fp; if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 075f063e98..b817d31260 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -75,29 +75,6 @@ static void gen_lxvd2x(DisasContext *ctx) tcg_temp_free_i64(t0); } -static void gen_lxvdsx(DisasContext *ctx) -{ - TCGv EA; - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, t0, EA); - set_cpu_vsrh(xT(ctx->opcode), t0); - tcg_gen_mov_i64(t1, t0); - set_cpu_vsrl(xT(ctx->opcode), t1); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - static void gen_lxvw4x(DisasContext *ctx) { TCGv EA; @@ -169,6 +146,29 @@ static void gen_lxvwsx(DisasContext *ctx) tcg_temp_free_i32(data); } +static void gen_lxvdsx(DisasContext *ctx) +{ + TCGv EA; + TCGv_i64 data; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + + gen_addr_reg_index(ctx, EA); + + data = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ); + tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, data); + + tcg_temp_free(EA); + tcg_temp_free_i64(data); +} + static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, TCGv_i64 inh, TCGv_i64 inl) { diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 78cc8f043b..a4d0038828 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10470,63 +10470,6 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name) return oc; } -static void ppc_cpu_parse_featurestr(const char *type, char *features, - Error **errp) -{ - Object *machine = qdev_get_machine(); - const PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(object_class_by_name(type)); - - if (!features) { - return; - } - - if (object_property_find(machine, "max-cpu-compat")) { - int i; - char **inpieces; - char *s = features; - Error *local_err = NULL; - char *compat_str = NULL; - - /* - * Backwards compatibility hack: - * - * CPUs had a "compat=" property which didn't make sense for - * anything except pseries. It was replaced by "max-cpu-compat" - * machine option. This supports old command lines like - * -cpu POWER8,compat=power7 - * By stripping the compat option and applying it to the machine - * before passing it on to the cpu level parser. - */ - inpieces = g_strsplit(features, ",", 0); - *s = '\0'; - for (i = 0; inpieces[i]; i++) { - if (g_str_has_prefix(inpieces[i], "compat=")) { - warn_report_once("CPU 'compat' property is deprecated; " - "use max-cpu-compat machine property instead"); - compat_str = inpieces[i]; - continue; - } - if ((i != 0) && (s != features)) { - s = g_stpcpy(s, ","); - } - s = g_stpcpy(s, inpieces[i]); - } - - if (compat_str) { - char *v = compat_str + strlen("compat="); - object_property_set_str(machine, "max-cpu-compat", v, &local_err); - } - g_strfreev(inpieces); - if (local_err) { - error_propagate(errp, local_err); - return; - } - } - - /* do property processing with generic handler */ - pcc->parent_parse_features(type, features, errp); -} - PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) { ObjectClass *oc = OBJECT_CLASS(pcc); @@ -10728,7 +10671,7 @@ static void ppc_cpu_reset(DeviceState *dev) #endif #if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { + if (mmu_is_64bit(env->mmu_model)) { msr |= (1ULL << MSR_SF); } #endif @@ -10905,8 +10848,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); cc->class_by_name = ppc_cpu_class_by_name; - pcc->parent_parse_features = cc->parse_features; - cc->parse_features = ppc_cpu_parse_featurestr; cc->has_work = ppc_cpu_has_work; cc->do_interrupt = ppc_cpu_do_interrupt; cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt; |