diff options
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 115 |
1 files changed, 108 insertions, 7 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b316184fd..b8d5120106 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -199,6 +200,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), @@ -213,7 +215,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), - DEFINE_PROP_END_OF_LIST(), + { }, }; bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -579,6 +581,100 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } +/* Tenstorrent Ascalon */ +static void rv64_tt_ascalon_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); + env->priv_ver = PRIV_VERSION_1_13_0; + + /* Enable ISA extensions */ + cpu->cfg.mmu = true; + cpu->cfg.vlenb = 256 >> 3; + cpu->cfg.elen = 64; + cpu->env.vext_ver = VEXT_VERSION_1_00_0; + cpu->cfg.rvv_ma_all_1s = true; + cpu->cfg.rvv_ta_all_1s = true; + cpu->cfg.misa_w = true; + cpu->cfg.pmp = true; + cpu->cfg.cbom_blocksize = 64; + cpu->cfg.cbop_blocksize = 64; + cpu->cfg.cboz_blocksize = 64; + cpu->cfg.ext_zic64b = true; + cpu->cfg.ext_zicbom = true; + cpu->cfg.ext_zicbop = true; + cpu->cfg.ext_zicboz = true; + cpu->cfg.ext_zicntr = true; + cpu->cfg.ext_zicond = true; + cpu->cfg.ext_zicsr = true; + cpu->cfg.ext_zifencei = true; + cpu->cfg.ext_zihintntl = true; + cpu->cfg.ext_zihintpause = true; + cpu->cfg.ext_zihpm = true; + cpu->cfg.ext_zimop = true; + cpu->cfg.ext_zawrs = true; + cpu->cfg.ext_zfa = true; + cpu->cfg.ext_zfbfmin = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.ext_zfhmin = true; + cpu->cfg.ext_zcb = true; + cpu->cfg.ext_zcmop = true; + cpu->cfg.ext_zba = true; + cpu->cfg.ext_zbb = true; + cpu->cfg.ext_zbs = true; + cpu->cfg.ext_zkt = true; + cpu->cfg.ext_zvbb = true; + cpu->cfg.ext_zvbc = true; + cpu->cfg.ext_zvfbfmin = true; + cpu->cfg.ext_zvfbfwma = true; + cpu->cfg.ext_zvfh = true; + cpu->cfg.ext_zvfhmin = true; + cpu->cfg.ext_zvkng = true; + cpu->cfg.ext_smaia = true; + cpu->cfg.ext_smstateen = true; + cpu->cfg.ext_ssaia = true; + cpu->cfg.ext_sscofpmf = true; + cpu->cfg.ext_sstc = true; + cpu->cfg.ext_svade = true; + cpu->cfg.ext_svinval = true; + cpu->cfg.ext_svnapot = true; + cpu->cfg.ext_svpbmt = true; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif +} + +static void rv64_xiangshan_nanhu_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU); + env->priv_ver = PRIV_VERSION_1_12_0; + + /* Enable ISA extensions */ + cpu->cfg.ext_zbc = true; + cpu->cfg.ext_zbkb = true; + cpu->cfg.ext_zbkc = true; + cpu->cfg.ext_zbkx = true; + cpu->cfg.ext_zknd = true; + cpu->cfg.ext_zkne = true; + cpu->cfg.ext_zknh = true; + cpu->cfg.ext_zksed = true; + cpu->cfg.ext_zksh = true; + cpu->cfg.ext_svinval = true; + + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV39); +#endif +} + #ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { @@ -1575,7 +1671,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false), MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false), - DEFINE_PROP_END_OF_LIST(), + { }, }; const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { @@ -1592,12 +1688,14 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), - DEFINE_PROP_END_OF_LIST(), + { }, }; /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { - DEFINE_PROP_END_OF_LIST(), + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), + + { }, }; /* @@ -1609,8 +1707,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { */ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), + MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), - DEFINE_PROP_END_OF_LIST(), + { }, }; /* Deprecated entries marked for future removal */ @@ -1627,7 +1726,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), - DEFINE_PROP_END_OF_LIST(), + { }, }; static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, @@ -2699,7 +2798,6 @@ static const Property riscv_cpu_properties[] = { * it with -x and default to 'false'. */ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), - DEFINE_PROP_END_OF_LIST(), }; #if defined(TARGET_RISCV64) @@ -2984,7 +3082,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, + MXL_RV64, rv64_xiangshan_nanhu_cpu_init), #ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init), #endif /* CONFIG_TCG */ |