diff options
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 84 |
1 files changed, 57 insertions, 27 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b..254cd83f8b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -108,6 +108,15 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } +bool riscv_cpu_is_32bit(CPURISCVState *env) +{ + if (env->misa & RV64) { + return false; + } + + return true; +} + static void set_misa(CPURISCVState *env, target_ulong misa) { env->misa_mask = env->misa = misa; @@ -142,29 +151,50 @@ static void riscv_any_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); } -static void riscv_base_cpu_init(Object *obj) +#if defined(TARGET_RISCV64) +static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, 0); + set_misa(env, RV64); } -static void rvxx_sifive_u_cpu_init(Object *obj) +static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); } -static void rvxx_sifive_e_cpu_init(Object *obj) +static void rv64_sifive_e_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); + set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } +#else +static void rv32_base_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + /* We set this in the realise function */ + set_misa(env, RV32); +} -#if defined(TARGET_RISCV32) +static void rv32_sifive_u_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); +} + +static void rv32_sifive_e_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_10_0); + qdev_prop_set_bit(DEVICE(obj), "mmu", false); +} static void rv32_ibex_cpu_init(Object *obj) { @@ -182,7 +212,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } - #endif static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -218,10 +247,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); -#ifdef TARGET_RISCV32 - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); -#endif + if (riscv_cpu_is_32bit(env)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", + (target_ulong)(env->mstatus >> 32)); + } if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", @@ -334,11 +363,12 @@ static void riscv_cpu_reset(DeviceState *dev) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { -#if defined(TARGET_RISCV32) - info->print_insn = print_insn_riscv32; -#elif defined(TARGET_RISCV64) - info->print_insn = print_insn_riscv64; -#endif + RISCVCPU *cpu = RISCV_CPU(s); + if (riscv_cpu_is_32bit(&cpu->env)) { + info->print_insn = print_insn_riscv32; + } else { + info->print_insn = print_insn_riscv64; + } } static void riscv_cpu_realize(DeviceState *dev, Error **errp) @@ -349,7 +379,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); int priv_version = PRIV_VERSION_1_11_0; int vext_version = VEXT_VERSION_0_07_1; - target_ulong target_misa = 0; + target_ulong target_misa = env->misa; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -384,8 +414,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_resetvec(env, cpu->cfg.resetvec); - /* If misa isn't set (rv32 and rv64 machines) set it here */ - if (!env->misa) { + /* If only XLEN is set for misa, then set misa from properties */ + if (env->misa == RV32 || env->misa == RV64) { /* Do some ISA extension error checking */ if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, @@ -481,7 +511,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_vext_version(env, vext_version); } - set_misa(env, RVXLEN | target_misa); + set_misa(env, target_misa); } riscv_cpu_register_gdb_regs_for_features(cs); @@ -632,15 +662,15 @@ static const TypeInfo riscv_cpu_type_infos[] = { }, DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), #endif }; 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