diff options
Diffstat (limited to 'target/riscv/insn_trans/trans_rvv.c.inc')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 58 |
1 files changed, 30 insertions, 28 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f2e3d38515..6c07eebc52 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -29,12 +29,12 @@ static inline bool is_overlapped(const int8_t astart, int8_t asize, static bool require_rvv(DisasContext *s) { - return s->mstatus_vs != 0; + return s->mstatus_vs != EXT_STATUS_DISABLED; } static bool require_rvf(DisasContext *s) { - if (s->mstatus_fs == 0) { + if (s->mstatus_fs == EXT_STATUS_DISABLED) { return false; } @@ -52,7 +52,7 @@ static bool require_rvf(DisasContext *s) static bool require_scale_rvf(DisasContext *s) { - if (s->mstatus_fs == 0) { + if (s->mstatus_fs == EXT_STATUS_DISABLED) { return false; } @@ -70,7 +70,7 @@ static bool require_scale_rvf(DisasContext *s) static bool require_scale_rvfmin(DisasContext *s) { - if (s->mstatus_fs == 0) { + if (s->mstatus_fs == EXT_STATUS_DISABLED) { return false; } @@ -238,8 +238,8 @@ static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew) { int8_t emul = eew - s->sew + s->lmul; return (emul >= -3 && emul <= 3) && - require_align(vd, emul) && - require_nf(vd, nf, emul); + require_align(vd, emul) && + require_nf(vd, nf, emul); } /* @@ -315,7 +315,7 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2, int8_t seg_vd; int8_t emul = eew - s->sew + s->lmul; bool ret = vext_check_st_index(s, vd, vs2, nf, eew) && - require_vm(vm, vd); + require_vm(vm, vd); /* Each segment register group has to follow overlap rules. */ for (int i = 0; i < nf; ++i) { @@ -345,8 +345,8 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2, static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) { return require_vm(vm, vd) && - require_align(vd, s->lmul) && - require_align(vs, s->lmul); + require_align(vd, s->lmul) && + require_align(vs, s->lmul); } /* @@ -365,7 +365,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm) { return vext_check_ss(s, vd, vs2, vm) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); } static bool vext_check_ms(DisasContext *s, int vd, int vs) @@ -396,7 +396,7 @@ static bool vext_check_ms(DisasContext *s, int vd, int vs) static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) { bool ret = vext_check_ms(s, vd, vs2) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); if (vd != vs1) { ret &= require_noover(vd, 0, vs1, s->lmul); } @@ -460,14 +460,14 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm) { return vext_wide_check_common(s, vd, vm) && - require_align(vs, s->lmul) && - require_noover(vd, s->lmul + 1, vs, s->lmul); + require_align(vs, s->lmul) && + require_noover(vd, s->lmul + 1, vs, s->lmul); } static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) { return vext_wide_check_common(s, vd, vm) && - require_align(vs, s->lmul + 1); + require_align(vs, s->lmul + 1); } /* @@ -485,8 +485,8 @@ static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm) { return vext_check_ds(s, vd, vs2, vm) && - require_align(vs1, s->lmul) && - require_noover(vd, s->lmul + 1, vs1, s->lmul); + require_align(vs1, s->lmul) && + require_noover(vd, s->lmul + 1, vs1, s->lmul); } /* @@ -507,7 +507,7 @@ static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm) static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm) { return vext_check_ds(s, vd, vs1, vm) && - require_align(vs2, s->lmul + 1); + require_align(vs2, s->lmul + 1); } static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) @@ -535,7 +535,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm) { return vext_check_sd(s, vd, vs2, vm) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); } /* @@ -547,7 +547,7 @@ static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm) */ static bool vext_check_reduction(DisasContext *s, int vs2) { - return require_align(vs2, s->lmul) && (s->vstart == 0); + return require_align(vs2, s->lmul) && s->vstart_eq_zero; } /* @@ -3083,7 +3083,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s) && - s->vstart == 0) { + s->vstart_eq_zero) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -3112,7 +3112,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s) && - s->vstart == 0) { + s->vstart_eq_zero) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -3136,9 +3136,11 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) return false; } -/* vmsbf.m set-before-first mask bit */ -/* vmsif.m set-includ-first mask bit */ -/* vmsof.m set-only-first mask bit */ +/* + * vmsbf.m set-before-first mask bit + * vmsif.m set-including-first mask bit + * vmsof.m set-only-first mask bit + */ #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ @@ -3146,7 +3148,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vext_check_isa_ill(s) && \ require_vm(a->vm, a->rd) && \ (a->rd != a->rs2) && \ - (s->vstart == 0)) { \ + s->vstart_eq_zero) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ @@ -3187,7 +3189,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && require_vm(a->vm, a->rd) && require_align(a->rd, s->lmul) && - (s->vstart == 0)) { + s->vstart_eq_zero) { uint32_t data = 0; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -3636,7 +3638,7 @@ static bool vcompress_vm_check(DisasContext *s, arg_r *a) require_align(a->rs2, s->lmul) && (a->rd != a->rs2) && !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) && - (s->vstart == 0); + s->vstart_eq_zero; } static bool trans_vcompress_vm(DisasContext *s, arg_r *a) @@ -3675,7 +3677,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ QEMU_IS_ALIGNED(a->rd, LEN) && \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \ - if (s->vstart == 0) { \ + if (s->vstart_eq_zero) { \ /* EEW = 8 */ \ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ vreg_ofs(s, a->rs2), maxsz, maxsz); \ |