diff options
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/meson.build | 2 | ||||
| -rw-r--r-- | target/riscv/vector_helper.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 660078bda1..ff60b21d04 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -39,4 +39,4 @@ riscv_system_ss.add(files( )) target_arch += {'riscv': riscv_ss} -target_softmmu_arch += {'riscv': riscv_system_ss} +target_system_arch += {'riscv': riscv_system_ss} diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cba02c1320..c9b39fb67f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -100,7 +100,7 @@ static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) /* * This function checks watchpoint before real load operation. * - * In softmmu mode, the TLB API probe_access is enough for watchpoint check. + * In system mode, the TLB API probe_access is enough for watchpoint check. * In user mode, there is no watchpoint support now. * * It will trigger an exception if there is no mapping in TLB |