diff options
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 7 | ||||
| -rw-r--r-- | target/riscv/translate.c | 2 |
2 files changed, 6 insertions, 3 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cac9f1dc7e..5bc0005cc7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,7 @@ #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" #include "kvm_riscv.h" +#include "tcg/tcg.h" /* RISC-V CPU definitions */ @@ -538,10 +539,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, CPURISCVState *env = &cpu->env; RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + if (xl == MXL_RV32) { - env->pc = (int32_t)tb_pc(tb); + env->pc = (int32_t) tb->pc; } else { - env->pc = tb_pc(tb); + env->pc = tb->pc; } } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4a957a50b5..a8d516ca3e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1310,7 +1310,7 @@ static const TranslatorOps riscv_tr_ops = { .disas_log = riscv_tr_disas_log, }; -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, target_ulong pc, void *host_pc) { DisasContext ctx; |