diff options
Diffstat (limited to 'target/sparc')
| -rw-r--r-- | target/sparc/cpu.c | 3 | ||||
| -rw-r--r-- | target/sparc/cpu.h | 3 | ||||
| -rw-r--r-- | target/sparc/ldst_helper.c | 12 |
3 files changed, 10 insertions, 8 deletions
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 4e07b92fbd..d6583f1c2a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -36,8 +36,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSPARCState, version)); - tlb_flush(s, 1); + memset(env, 0, offsetof(CPUSPARCState, end_reset_fields)); env->cwp = 0; #ifndef TARGET_SPARC64 env->wim = 1; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5fb0ed1aad..601c018a05 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -419,6 +419,9 @@ struct CPUSPARCState { /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[MAX_NWINDOWS * 16 + 8]; + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + CPU_COMMON /* Fields from here on are preserved across CPU reset. */ diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index de7d53ae20..a0171f73f7 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -816,7 +816,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); break; default: break; @@ -841,7 +841,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, are invalid in normal mode. */ if ((oldreg ^ env->mmuregs[reg]) & (MMU_NF | env->def->mmu_bm)) { - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); } break; case 1: /* Context Table Pointer Register */ @@ -852,7 +852,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1509,13 +1509,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context = val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -1654,7 +1654,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, /* flush neverland mappings created during no-fault mode, so the sequential MMU faults report proper fault types */ if (env->mmuregs[0] & MMU_NF) { - tlb_flush(cs, 1); + tlb_flush(cs); } } #else |