diff options
Diffstat (limited to 'target/xtensa/translate.c')
| -rw-r--r-- | target/xtensa/translate.c | 5860 |
1 files changed, 3698 insertions, 2162 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 20f7ddf042..4bdfcd24d0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -59,7 +59,6 @@ typedef struct DisasContext { int ring; uint32_t lbeg; uint32_t lend; - TCGv_i32 litbase; int is_jmp; int singlestep_enabled; @@ -75,6 +74,10 @@ typedef struct DisasContext { TCGv_i32 next_icount; unsigned cpenable; + + uint32_t *raw_arg; + xtensa_insnbuf insnbuf; + xtensa_insnbuf slotbuf; } DisasContext; static TCGv_i32 cpu_pc; @@ -132,6 +135,7 @@ static const XtensaReg sregnames[256] = { [WINDOW_START] = XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), + [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), @@ -139,6 +143,7 @@ static const XtensaReg sregnames[256] = { [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), + [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), @@ -199,6 +204,7 @@ static const XtensaReg sregnames[256] = { }; static const XtensaReg uregnames[256] = { + [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), @@ -252,31 +258,11 @@ void xtensa_translate_init(void) } } -static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt) -{ - return xtensa_option_bits_enabled(dc->config, opt); -} - static inline bool option_enabled(DisasContext *dc, int opt) { return xtensa_option_enabled(dc->config, opt); } -static void init_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - dc->litbase = tcg_temp_local_new_i32(); - tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); - } -} - -static void reset_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_temp_free(dc->litbase); - } -} - static void init_sar_tracker(DisasContext *dc) { dc->sar_5bit = false; @@ -469,21 +455,21 @@ static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) } static void gen_brcond(DisasContext *dc, TCGCond cond, - TCGv_i32 t0, TCGv_i32 t1, uint32_t offset) + TCGv_i32 t0, TCGv_i32 t1, uint32_t addr) { TCGLabel *label = gen_new_label(); tcg_gen_brcond_i32(cond, t0, t1, label); gen_jumpi_check_loop_end(dc, 0); gen_set_label(label); - gen_jumpi(dc, dc->pc + offset, 1); + gen_jumpi(dc, addr, 1); } static void gen_brcondi(DisasContext *dc, TCGCond cond, - TCGv_i32 t0, uint32_t t1, uint32_t offset) + TCGv_i32 t0, uint32_t t1, uint32_t addr) { TCGv_i32 tmp = tcg_const_i32(t1); - gen_brcond(dc, cond, t0, tmp, offset); + gen_brcond(dc, cond, t0, tmp, addr); tcg_temp_free(tmp); } @@ -945,2164 +931,98 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) return m; } -static inline unsigned xtensa_op0_insn_len(unsigned op0) +static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) { - return op0 >= 8 ? 2 : 3; + return xtensa_isa_length_from_chars(dc->config->isa, &op0); } static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { -#define HAS_OPTION_BITS(opt) do { \ - if (!option_bits_enabled(dc, opt)) { \ - qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \ - __FILE__, __LINE__); \ - goto invalid_opcode; \ - } \ - } while (0) - -#define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt)) - -#define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__) -#define RESERVED() do { \ - qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \ - dc->pc, b0, b1, b2, __FILE__, __LINE__); \ - goto invalid_opcode; \ - } while (0) - - -#ifdef TARGET_WORDS_BIGENDIAN -#define OP0 (((b0) & 0xf0) >> 4) -#define OP1 (((b2) & 0xf0) >> 4) -#define OP2 ((b2) & 0xf) -#define RRR_R ((b1) & 0xf) -#define RRR_S (((b1) & 0xf0) >> 4) -#define RRR_T ((b0) & 0xf) -#else -#define OP0 (((b0) & 0xf)) -#define OP1 (((b2) & 0xf)) -#define OP2 (((b2) & 0xf0) >> 4) -#define RRR_R (((b1) & 0xf0) >> 4) -#define RRR_S (((b1) & 0xf)) -#define RRR_T (((b0) & 0xf0) >> 4) -#endif -#define RRR_X ((RRR_R & 0x4) >> 2) -#define RRR_Y ((RRR_T & 0x4) >> 2) -#define RRR_W (RRR_R & 0x3) - -#define RRRN_R RRR_R -#define RRRN_S RRR_S -#define RRRN_T RRR_T - -#define RRI4_R RRR_R -#define RRI4_S RRR_S -#define RRI4_T RRR_T -#ifdef TARGET_WORDS_BIGENDIAN -#define RRI4_IMM4 ((b2) & 0xf) -#else -#define RRI4_IMM4 (((b2) & 0xf0) >> 4) -#endif - -#define RRI8_R RRR_R -#define RRI8_S RRR_S -#define RRI8_T RRR_T -#define RRI8_IMM8 (b2) -#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8) - -#ifdef TARGET_WORDS_BIGENDIAN -#define RI16_IMM16 (((b1) << 8) | (b2)) -#else -#define RI16_IMM16 (((b2) << 8) | (b1)) -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define CALL_N (((b0) & 0xc) >> 2) -#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2)) -#else -#define CALL_N (((b0) & 0x30) >> 4) -#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10)) -#endif -#define CALL_OFFSET_SE \ - (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET) - -#define CALLX_N CALL_N -#ifdef TARGET_WORDS_BIGENDIAN -#define CALLX_M ((b0) & 0x3) -#else -#define CALLX_M (((b0) & 0xc0) >> 6) -#endif -#define CALLX_S RRR_S - -#define BRI12_M CALLX_M -#define BRI12_S RRR_S -#ifdef TARGET_WORDS_BIGENDIAN -#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2)) -#else -#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4)) -#endif -#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12) - -#define BRI8_M BRI12_M -#define BRI8_R RRI8_R -#define BRI8_S RRI8_S -#define BRI8_IMM8 RRI8_IMM8 -#define BRI8_IMM8_SE RRI8_IMM8_SE - -#define RSR_SR (b1) - - uint8_t b0 = cpu_ldub_code(env, dc->pc); - uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); - uint8_t b2 = 0; - unsigned len = xtensa_op0_insn_len(OP0); - - static const uint32_t B4CONST[] = { - 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 - }; - - static const uint32_t B4CONSTU[] = { - 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 - }; - - switch (len) { - case 2: - HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); - break; - - case 3: - b2 = cpu_ldub_code(env, dc->pc + 2); - break; + xtensa_isa isa = dc->config->isa; + unsigned char b[MAX_INSN_LENGTH] = {cpu_ldub_code(env, dc->pc)}; + unsigned len = xtensa_op0_insn_len(dc, b[0]); + xtensa_format fmt; + unsigned slot, slots; + unsigned i; - default: - RESERVED(); + if (len == XTENSA_UNDEFINED) { + qemu_log_mask(LOG_GUEST_ERROR, + "unknown instruction length (pc = %08x)\n", + dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; } - dc->next_pc = dc->pc + len; - - switch (OP0) { - case 0: /*QRST*/ - switch (OP1) { - case 0: /*RST0*/ - switch (OP2) { - case 0: /*ST0*/ - if ((RRR_R & 0xc) == 0x8) { - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - } - - switch (RRR_R) { - case 0: /*SNM0*/ - switch (CALLX_M) { - case 0: /*ILL*/ - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - break; - - case 1: /*reserved*/ - RESERVED(); - break; - - case 2: /*JR*/ - switch (CALLX_N) { - case 0: /*RET*/ - case 2: /*JX*/ - if (gen_window_check1(dc, CALLX_S)) { - gen_jump(dc, cpu_R[CALLX_S]); - } - break; - - case 1: /*RETWw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 tmp = tcg_const_i32(dc->pc); - gen_helper_retw(tmp, cpu_env, tmp); - gen_jump(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 3: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*CALLX*/ - if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) { - break; - } - switch (CALLX_N) { - case 0: /*CALLX0*/ - { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); - gen_jump(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 1: /*CALLX4w*/ - case 2: /*CALLX8w*/ - case 3: /*CALLX12w*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]); - gen_callw(dc, CALLX_N, tmp); - tcg_temp_free(tmp); - } - break; - } - break; - } - break; - - case 1: /*MOVSPw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_window_check2(dc, RRR_T, RRR_S)) { - TCGv_i32 pc = tcg_const_i32(dc->pc); - gen_helper_movsp(cpu_env, pc); - tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]); - tcg_temp_free(pc); - } - break; - - case 2: /*SYNC*/ - switch (RRR_T) { - case 0: /*ISYNC*/ - break; - - case 1: /*RSYNC*/ - break; - - case 2: /*ESYNC*/ - break; - - case 3: /*DSYNC*/ - break; - - case 8: /*EXCW*/ - HAS_OPTION(XTENSA_OPTION_EXCEPTION); - break; - - case 12: /*MEMW*/ - break; - - case 13: /*EXTW*/ - break; - - case 15: /*NOP*/ - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*RFEIx*/ - switch (RRR_T) { - case 0: /*RFETx*/ - HAS_OPTION(XTENSA_OPTION_EXCEPTION); - switch (RRR_S) { - case 0: /*RFEx*/ - if (gen_check_privilege(dc)) { - tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1]); - } - break; - - case 1: /*RFUEx*/ - RESERVED(); - break; - - case 2: /*RFDEx*/ - if (gen_check_privilege(dc)) { - gen_jump(dc, cpu_SR[ - dc->config->ndepc ? DEPC : EPC1]); - } - break; - - case 4: /*RFWOw*/ - case 5: /*RFWUw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { - TCGv_i32 tmp = tcg_const_i32(1); - - tcg_gen_andi_i32( - cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); - tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); - - if (RRR_S == 4) { - tcg_gen_andc_i32(cpu_SR[WINDOW_START], - cpu_SR[WINDOW_START], tmp); - } else { - tcg_gen_or_i32(cpu_SR[WINDOW_START], - cpu_SR[WINDOW_START], tmp); - } - - gen_helper_restore_owb(cpu_env); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1]); - - tcg_temp_free(tmp); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 1: /*RFIx*/ - HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT); - if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) { - if (gen_check_privilege(dc)) { - tcg_gen_mov_i32(cpu_SR[PS], - cpu_SR[EPS2 + RRR_S - 2]); - gen_check_interrupts(dc); - gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]); - } - } else { - qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S); - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - } - break; - - case 2: /*RFME*/ - TBD(); - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - - case 4: /*BREAKx*/ - HAS_OPTION(XTENSA_OPTION_DEBUG); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_BI); - } - break; - - case 5: /*SYSCALLx*/ - HAS_OPTION(XTENSA_OPTION_EXCEPTION); - switch (RRR_S) { - case 0: /*SYSCALLx*/ - gen_exception_cause(dc, SYSCALL_CAUSE); - break; - - case 1: /*SIMCALL*/ - if (semihosting_enabled()) { - if (gen_check_privilege(dc)) { - gen_helper_simcall(cpu_env); - } - } else { - qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - } - break; - - default: - RESERVED(); - break; - } - break; - - case 6: /*RSILx*/ - HAS_OPTION(XTENSA_OPTION_INTERRUPT); - if (gen_check_privilege(dc) && - gen_window_check1(dc, RRR_T)) { - tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]); - tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); - tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S); - gen_check_interrupts(dc); - gen_jumpi_check_loop_end(dc, 0); - } - break; - - case 7: /*WAITIx*/ - HAS_OPTION(XTENSA_OPTION_INTERRUPT); - if (gen_check_privilege(dc)) { - gen_waiti(dc, RRR_S); - } - break; - - case 8: /*ANY4p*/ - case 9: /*ALL4p*/ - case 10: /*ANY8p*/ - case 11: /*ALL8p*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - { - const unsigned shift = (RRR_R & 2) ? 8 : 4; - TCGv_i32 mask = tcg_const_i32( - ((1 << shift) - 1) << RRR_S); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_and_i32(tmp, cpu_SR[BR], mask); - if (RRR_R & 1) { /*ALL*/ - tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S); - } else { /*ANY*/ - tcg_gen_add_i32(tmp, tmp, mask); - } - tcg_gen_shri_i32(tmp, tmp, RRR_S + shift); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], - tmp, RRR_T, 1); - tcg_temp_free(mask); - tcg_temp_free(tmp); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - - case 1: /*AND*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 2: /*OR*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 3: /*XOR*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 4: /*ST1*/ - switch (RRR_R) { - case 0: /*SSR*/ - if (gen_window_check1(dc, RRR_S)) { - gen_right_shift_sar(dc, cpu_R[RRR_S]); - } - break; - - case 1: /*SSL*/ - if (gen_window_check1(dc, RRR_S)) { - gen_left_shift_sar(dc, cpu_R[RRR_S]); - } - break; - - case 2: /*SSA8L*/ - if (gen_window_check1(dc, RRR_S)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); - gen_right_shift_sar(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 3: /*SSA8B*/ - if (gen_window_check1(dc, RRR_S)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3); - gen_left_shift_sar(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 4: /*SSAI*/ - { - TCGv_i32 tmp = tcg_const_i32( - RRR_S | ((RRR_T & 1) << 4)); - gen_right_shift_sar(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 6: /*RER*/ - HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - gen_helper_rer(cpu_R[RRR_T], cpu_env, cpu_R[RRR_S]); - } - break; - - case 7: /*WER*/ - HAS_OPTION(XTENSA_OPTION_EXTERN_REGS); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - gen_helper_wer(cpu_env, cpu_R[RRR_T], cpu_R[RRR_S]); - } - break; - - case 8: /*ROTWw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc)) { - TCGv_i32 tmp = tcg_const_i32( - RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0)); - gen_helper_rotw(cpu_env, tmp); - tcg_temp_free(tmp); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - } - break; - - case 14: /*NSAu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); - if (gen_window_check2(dc, RRR_S, RRR_T)) { - tcg_gen_clrsb_i32(cpu_R[RRR_T], cpu_R[RRR_S]); - } - break; - - case 15: /*NSAUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); - if (gen_window_check2(dc, RRR_S, RRR_T)) { - tcg_gen_clzi_i32(cpu_R[RRR_T], cpu_R[RRR_S], 32); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 5: /*TLB*/ - HAS_OPTION_BITS( - XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION)); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0); - - switch (RRR_R & 7) { - case 3: /*RITLB0*/ /*RDTLB0*/ - gen_helper_rtlb0(cpu_R[RRR_T], - cpu_env, cpu_R[RRR_S], dtlb); - break; - - case 4: /*IITLB*/ /*IDTLB*/ - gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb); - /* This could change memory mapping, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - break; - - case 5: /*PITLB*/ /*PDTLB*/ - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_ptlb(cpu_R[RRR_T], - cpu_env, cpu_R[RRR_S], dtlb); - break; - - case 6: /*WITLB*/ /*WDTLB*/ - gen_helper_wtlb( - cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb); - /* This could change memory mapping, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - break; - - case 7: /*RITLB1*/ /*RDTLB1*/ - gen_helper_rtlb1(cpu_R[RRR_T], - cpu_env, cpu_R[RRR_S], dtlb); - break; - - default: - tcg_temp_free(dtlb); - RESERVED(); - break; - } - tcg_temp_free(dtlb); - } - break; - - case 6: /*RT0*/ - if (!gen_window_check2(dc, RRR_R, RRR_T)) { - break; - } - switch (RRR_S) { - case 0: /*NEG*/ - tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]); - break; - - case 1: /*ABS*/ - { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 neg = tcg_temp_new_i32(); - - tcg_gen_neg_i32(neg, cpu_R[RRR_T]); - tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R], - cpu_R[RRR_T], zero, cpu_R[RRR_T], neg); - tcg_temp_free(neg); - tcg_temp_free(zero); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 7: /*reserved*/ - RESERVED(); - break; - - case 8: /*ADD*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 9: /*ADD**/ - case 10: - case 11: - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8); - tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); - tcg_temp_free(tmp); - } - break; - - case 12: /*SUB*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 13: /*SUB**/ - case 14: - case 15: - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12); - tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]); - tcg_temp_free(tmp); - } - break; - } - break; - - case 1: /*RST1*/ - switch (OP2) { - case 0: /*SLLI*/ - case 1: - if (gen_window_check2(dc, RRR_R, RRR_S)) { - tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S], - 32 - (RRR_T | ((OP2 & 1) << 4))); - } - break; - - case 2: /*SRAI*/ - case 3: - if (gen_window_check2(dc, RRR_R, RRR_T)) { - tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T], - RRR_S | ((OP2 & 1) << 4)); - } - break; - - case 4: /*SRLI*/ - if (gen_window_check2(dc, RRR_R, RRR_T)) { - tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S); - } - break; - - case 6: /*XSR*/ - if (gen_check_sr(dc, RSR_SR, SR_X) && - (RSR_SR < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, RRR_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - bool rsr_end, wsr_end; - - tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); - rsr_end = gen_rsr(dc, cpu_R[RRR_T], RSR_SR); - wsr_end = gen_wsr(dc, RSR_SR, tmp); - tcg_temp_free(tmp); - if (rsr_end && !wsr_end) { - gen_jumpi_check_loop_end(dc, 0); - } - } - break; - - /* - * Note: 64 bit ops are used here solely because SAR values - * have range 0..63 - */ -#define gen_shift_reg(cmd, reg) do { \ - TCGv_i64 tmp = tcg_temp_new_i64(); \ - tcg_gen_extu_i32_i64(tmp, reg); \ - tcg_gen_##cmd##_i64(v, v, tmp); \ - tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \ - tcg_temp_free_i64(v); \ - tcg_temp_free_i64(tmp); \ - } while (0) - -#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) - - case 8: /*SRC*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]); - gen_shift(shr); - } - break; - - case 9: /*SRL*/ - if (!gen_window_check2(dc, RRR_R, RRR_T)) { - break; - } - if (dc->sar_5bit) { - tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); - } else { - TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]); - gen_shift(shr); - } - break; - - case 10: /*SLL*/ - if (!gen_window_check2(dc, RRR_R, RRR_S)) { - break; - } - if (dc->sar_m32_5bit) { - tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32); - } else { - TCGv_i64 v = tcg_temp_new_i64(); - TCGv_i32 s = tcg_const_i32(32); - tcg_gen_sub_i32(s, s, cpu_SR[SAR]); - tcg_gen_andi_i32(s, s, 0x3f); - tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]); - gen_shift_reg(shl, s); - tcg_temp_free(s); - } - break; - - case 11: /*SRA*/ - if (!gen_window_check2(dc, RRR_R, RRR_T)) { - break; - } - if (dc->sar_5bit) { - tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]); - } else { - TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]); - gen_shift(sar); - } - break; -#undef gen_shift -#undef gen_shift_reg - - case 12: /*MUL16U*/ - HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 v1 = tcg_temp_new_i32(); - TCGv_i32 v2 = tcg_temp_new_i32(); - tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]); - tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]); - tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); - tcg_temp_free(v2); - tcg_temp_free(v1); - } - break; - - case 13: /*MUL16S*/ - HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL); - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - TCGv_i32 v1 = tcg_temp_new_i32(); - TCGv_i32 v2 = tcg_temp_new_i32(); - tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]); - tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]); - tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2); - tcg_temp_free(v2); - tcg_temp_free(v1); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 2: /*RST2*/ - if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - break; - } - - if (OP2 >= 12) { - HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV); - TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label); - gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); - gen_set_label(label); - } - - switch (OP2) { -#define BOOLEAN_LOGIC(fn, r, s, t) \ - do { \ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); \ - TCGv_i32 tmp1 = tcg_temp_new_i32(); \ - TCGv_i32 tmp2 = tcg_temp_new_i32(); \ - \ - tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \ - tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \ - tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \ - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \ - tcg_temp_free(tmp1); \ - tcg_temp_free(tmp2); \ - } while (0) - - case 0: /*ANDBp*/ - BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T); - break; - - case 1: /*ANDBCp*/ - BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T); - break; - - case 2: /*ORBp*/ - BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T); - break; - - case 3: /*ORBCp*/ - BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T); - break; - - case 4: /*XORBp*/ - BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T); - break; - -#undef BOOLEAN_LOGIC - - case 8: /*MULLi*/ - HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL); - tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - break; - - case 10: /*MULUHi*/ - case 11: /*MULSHi*/ - HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH); - { - TCGv lo = tcg_temp_new(); - - if (OP2 == 10) { - tcg_gen_mulu2_i32(lo, cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } else { - tcg_gen_muls2_i32(lo, cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } - tcg_temp_free(lo); - } - break; - - case 12: /*QUOUi*/ - tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - break; - - case 13: /*QUOSi*/ - case 15: /*REMSi*/ - { - TCGLabel *label1 = gen_new_label(); - TCGLabel *label2 = gen_new_label(); - - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000, - label1); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff, - label1); - tcg_gen_movi_i32(cpu_R[RRR_R], - OP2 == 13 ? 0x80000000 : 0); - tcg_gen_br(label2); - gen_set_label(label1); - if (OP2 == 13) { - tcg_gen_div_i32(cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } else { - tcg_gen_rem_i32(cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T]); - } - gen_set_label(label2); - } - break; - - case 14: /*REMUi*/ - tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]); - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*RST3*/ - switch (OP2) { - case 0: /*RSR*/ - if (gen_check_sr(dc, RSR_SR, SR_R) && - (RSR_SR < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, RRR_T)) { - if (gen_rsr(dc, cpu_R[RRR_T], RSR_SR)) { - gen_jumpi_check_loop_end(dc, 0); - } - } - break; - - case 1: /*WSR*/ - if (gen_check_sr(dc, RSR_SR, SR_W) && - (RSR_SR < 64 || gen_check_privilege(dc)) && - gen_window_check1(dc, RRR_T)) { - gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); - } - break; - - case 2: /*SEXTu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT); - if (gen_window_check2(dc, RRR_R, RRR_S)) { - int shift = 24 - RRR_T; - - if (shift == 24) { - tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); - } else if (shift == 16) { - tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); - } else { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); - tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); - tcg_temp_free(tmp); - } - } - break; - - case 3: /*CLAMPSu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS); - if (gen_window_check2(dc, RRR_R, RRR_S)) { - TCGv_i32 tmp1 = tcg_temp_new_i32(); - TCGv_i32 tmp2 = tcg_temp_new_i32(); - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); - tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); - tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); - - tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); - tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T)); - - tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero, - cpu_R[RRR_S], tmp1); - tcg_temp_free(tmp1); - tcg_temp_free(tmp2); - tcg_temp_free(zero); - } - break; - - case 4: /*MINu*/ - case 5: /*MAXu*/ - case 6: /*MINUu*/ - case 7: /*MAXUu*/ - HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX); - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - static const TCGCond cond[] = { - TCG_COND_LE, - TCG_COND_GE, - TCG_COND_LEU, - TCG_COND_GEU - }; - tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R], - cpu_R[RRR_S], cpu_R[RRR_T], - cpu_R[RRR_S], cpu_R[RRR_T]); - } - break; - - case 8: /*MOVEQZ*/ - case 9: /*MOVNEZ*/ - case 10: /*MOVLTZ*/ - case 11: /*MOVGEZ*/ - if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) { - static const TCGCond cond[] = { - TCG_COND_EQ, - TCG_COND_NE, - TCG_COND_LT, - TCG_COND_GE, - }; - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R], - cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]); - tcg_temp_free(zero); - } - break; - - case 12: /*MOVFp*/ - case 13: /*MOVTp*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - if (gen_window_check2(dc, RRR_R, RRR_S)) { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); - tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, - cpu_R[RRR_R], tmp, zero, - cpu_R[RRR_S], cpu_R[RRR_R]); - - tcg_temp_free(tmp); - tcg_temp_free(zero); - } - break; - - case 14: /*RUR*/ - if (gen_window_check1(dc, RRR_R)) { - int st = (RRR_S << 4) + RRR_T; - if (uregnames[st].name) { - tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); - } else { - qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st); - TBD(); - } - } - break; - - case 15: /*WUR*/ - if (gen_window_check1(dc, RRR_T)) { - if (uregnames[RSR_SR].name) { - gen_wur(RSR_SR, cpu_R[RRR_T]); - } else { - qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR); - TBD(); - } - } - break; - - } - break; - - case 4: /*EXTUI*/ - case 5: - if (gen_window_check2(dc, RRR_R, RRR_T)) { - int shiftimm = RRR_S | ((OP1 & 1) << 4); - int maskimm = (1 << (OP2 + 1)) - 1; - - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); - tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); - tcg_temp_free(tmp); - } - break; - - case 6: /*CUST0*/ - RESERVED(); - break; - - case 7: /*CUST1*/ - RESERVED(); - break; - - case 8: /*LSCXp*/ - switch (OP2) { - case 0: /*LSXf*/ - case 1: /*LSXUf*/ - case 4: /*SSXf*/ - case 5: /*SSXUf*/ - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - if (gen_window_check2(dc, RRR_S, RRR_T) && - gen_check_cpenable(dc, 0)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]); - gen_load_store_alignment(dc, 2, addr, false); - if (OP2 & 0x4) { - tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring); - } else { - tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring); - } - if (OP2 & 0x1) { - tcg_gen_mov_i32(cpu_R[RRR_S], addr); - } - tcg_temp_free(addr); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 9: /*LSC4*/ - if (!gen_window_check2(dc, RRR_S, RRR_T)) { - break; - } - switch (OP2) { - case 0: /*L32E*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[RRR_S], - (0xffffffc0 | (RRR_R << 2))); - tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring); - tcg_temp_free(addr); - } - break; - - case 4: /*S32E*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_check_privilege(dc) && - gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[RRR_S], - (0xffffffc0 | (RRR_R << 2))); - tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring); - tcg_temp_free(addr); - } - break; - - case 5: /*S32N*/ - if (gen_window_check2(dc, RRI4_S, RRI4_T)) { - TCGv_i32 addr = tcg_temp_new_i32(); - - tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2); - gen_load_store_alignment(dc, 2, addr, false); - tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring); - tcg_temp_free(addr); - } - break; - - default: - RESERVED(); - break; - } - break; - - case 10: /*FP0*/ - /*DEPBITS*/ - if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { - if (!gen_window_check2(dc, RRR_S, RRR_T)) { - break; - } - tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], - OP2, RRR_R + 1); - break; - } - - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - switch (OP2) { - case 0: /*ADD.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_add_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_S], cpu_FR[RRR_T]); - } - break; - - case 1: /*SUB.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_S], cpu_FR[RRR_T]); - } - break; - - case 2: /*MUL.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_S], cpu_FR[RRR_T]); - } - break; - - case 4: /*MADD.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_R], cpu_FR[RRR_S], - cpu_FR[RRR_T]); - } - break; - - case 5: /*MSUB.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, - cpu_FR[RRR_R], cpu_FR[RRR_S], - cpu_FR[RRR_T]); - } - break; - - case 8: /*ROUND.Sf*/ - case 9: /*TRUNC.Sf*/ - case 10: /*FLOOR.Sf*/ - case 11: /*CEIL.Sf*/ - case 14: /*UTRUNC.Sf*/ - if (gen_window_check1(dc, RRR_R) && - gen_check_cpenable(dc, 0)) { - static const unsigned rounding_mode_const[] = { - float_round_nearest_even, - float_round_to_zero, - float_round_down, - float_round_up, - [6] = float_round_to_zero, - }; - TCGv_i32 rounding_mode = tcg_const_i32( - rounding_mode_const[OP2 & 7]); - TCGv_i32 scale = tcg_const_i32(RRR_T); - - if (OP2 == 14) { - gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S], - rounding_mode, scale); - } else { - gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S], - rounding_mode, scale); - } - - tcg_temp_free(rounding_mode); - tcg_temp_free(scale); - } - break; - - case 12: /*FLOAT.Sf*/ - case 13: /*UFLOAT.Sf*/ - if (gen_window_check1(dc, RRR_S) && - gen_check_cpenable(dc, 0)) { - TCGv_i32 scale = tcg_const_i32(-RRR_T); - - if (OP2 == 13) { - gen_helper_uitof(cpu_FR[RRR_R], cpu_env, - cpu_R[RRR_S], scale); - } else { - gen_helper_itof(cpu_FR[RRR_R], cpu_env, - cpu_R[RRR_S], scale); - } - tcg_temp_free(scale); - } - break; - - case 15: /*FP1OP*/ - switch (RRR_T) { - case 0: /*MOV.Sf*/ - if (gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); - } - break; - - case 1: /*ABS.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); - } - break; - - case 4: /*RFRf*/ - if (gen_window_check1(dc, RRR_R) && - gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); - } - break; - - case 5: /*WFRf*/ - if (gen_window_check1(dc, RRR_S) && - gen_check_cpenable(dc, 0)) { - tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); - } - break; - - case 6: /*NEG.Sf*/ - if (gen_check_cpenable(dc, 0)) { - gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 11: /*FP1*/ - /*DEPBITS*/ - if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) { - if (!gen_window_check2(dc, RRR_S, RRR_T)) { - break; - } - tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S], - OP2 + 16, RRR_R + 1); - break; - } - - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - -#define gen_compare(rel, br, a, b) \ - do { \ - if (gen_check_cpenable(dc, 0)) { \ - TCGv_i32 bit = tcg_const_i32(1 << br); \ - \ - gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \ - tcg_temp_free(bit); \ - } \ - } while (0) - - switch (OP2) { - case 1: /*UN.Sf*/ - gen_compare(un_s, RRR_R, RRR_S, RRR_T); - break; - - case 2: /*OEQ.Sf*/ - gen_compare(oeq_s, RRR_R, RRR_S, RRR_T); - break; - - case 3: /*UEQ.Sf*/ - gen_compare(ueq_s, RRR_R, RRR_S, RRR_T); - break; - - case 4: /*OLT.Sf*/ - gen_compare(olt_s, RRR_R, RRR_S, RRR_T); - break; - - case 5: /*ULT.Sf*/ - gen_compare(ult_s, RRR_R, RRR_S, RRR_T); - break; - - case 6: /*OLE.Sf*/ - gen_compare(ole_s, RRR_R, RRR_S, RRR_T); - break; - - case 7: /*ULE.Sf*/ - gen_compare(ule_s, RRR_R, RRR_S, RRR_T); - break; - -#undef gen_compare - - case 8: /*MOVEQZ.Sf*/ - case 9: /*MOVNEZ.Sf*/ - case 10: /*MOVLTZ.Sf*/ - case 11: /*MOVGEZ.Sf*/ - if (gen_window_check1(dc, RRR_T) && - gen_check_cpenable(dc, 0)) { - static const TCGCond cond[] = { - TCG_COND_EQ, - TCG_COND_NE, - TCG_COND_LT, - TCG_COND_GE, - }; - TCGv_i32 zero = tcg_const_i32(0); - - tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R], - cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]); - tcg_temp_free(zero); - } - break; - - case 12: /*MOVF.Sf*/ - case 13: /*MOVT.Sf*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - if (gen_check_cpenable(dc, 0)) { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T); - tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ, - cpu_FR[RRR_R], tmp, zero, - cpu_FR[RRR_S], cpu_FR[RRR_R]); - - tcg_temp_free(tmp); - tcg_temp_free(zero); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 1: /*L32R*/ - if (gen_window_check1(dc, RRR_T)) { - TCGv_i32 tmp = tcg_const_i32( - ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? - 0 : ((dc->pc + 3) & ~3)) + - (0xfffc0000 | (RI16_IMM16 << 2))); - - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_gen_add_i32(tmp, tmp, dc->litbase); - } - tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring); - tcg_temp_free(tmp); - } - break; - - case 2: /*LSAI*/ -#define gen_load_store(type, shift) do { \ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - \ - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \ - if (shift) { \ - gen_load_store_alignment(dc, shift, addr, false); \ - } \ - tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ - tcg_temp_free(addr); \ - } \ - } while (0) - - switch (RRI8_R) { - case 0: /*L8UI*/ - gen_load_store(ld8u, 0); - break; - - case 1: /*L16UI*/ - gen_load_store(ld16u, 1); - break; - - case 2: /*L32I*/ - gen_load_store(ld32u, 2); - break; - - case 4: /*S8I*/ - gen_load_store(st8, 0); - break; - - case 5: /*S16I*/ - gen_load_store(st16, 1); - break; - - case 6: /*S32I*/ - gen_load_store(st32, 2); - break; - -#define gen_dcache_hit_test(w, shift) do { \ - if (gen_window_check1(dc, RRI##w##_S)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - TCGv_i32 res = tcg_temp_new_i32(); \ - tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ - RRI##w##_IMM##w << shift); \ - tcg_gen_qemu_ld8u(res, addr, dc->cring); \ - tcg_temp_free(addr); \ - tcg_temp_free(res); \ - } \ - } while (0) - -#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4) -#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2) - - case 7: /*CACHEc*/ - if (RRI8_T < 8) { - HAS_OPTION(XTENSA_OPTION_DCACHE); - } - - switch (RRI8_T) { - case 0: /*DPFRc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 1: /*DPFWc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 2: /*DPFROc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 3: /*DPFWOc*/ - gen_window_check1(dc, RRI8_S); - break; - - case 4: /*DHWBc*/ - gen_dcache_hit_test8(); - break; - - case 5: /*DHWBIc*/ - gen_dcache_hit_test8(); - break; - - case 6: /*DHIc*/ - if (gen_check_privilege(dc)) { - gen_dcache_hit_test8(); - } - break; - - case 7: /*DIIc*/ - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI8_S); - } - break; - - case 8: /*DCEc*/ - switch (OP1) { - case 0: /*DPFLl*/ - HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_dcache_hit_test4(); - } - break; - - case 2: /*DHUl*/ - HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_dcache_hit_test4(); - } - break; - - case 3: /*DIUl*/ - HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - case 4: /*DIWBc*/ - HAS_OPTION(XTENSA_OPTION_DCACHE); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - case 5: /*DIWBIc*/ - HAS_OPTION(XTENSA_OPTION_DCACHE); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - -#undef gen_dcache_hit_test -#undef gen_dcache_hit_test4 -#undef gen_dcache_hit_test8 - -#define gen_icache_hit_test(w, shift) do { \ - if (gen_window_check1(dc, RRI##w##_S)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - tcg_gen_movi_i32(cpu_pc, dc->pc); \ - tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ - RRI##w##_IMM##w << shift); \ - gen_helper_itlb_hit_test(cpu_env, addr); \ - tcg_temp_free(addr); \ - }\ - } while (0) - -#define gen_icache_hit_test4() gen_icache_hit_test(4, 4) -#define gen_icache_hit_test8() gen_icache_hit_test(8, 2) - - case 12: /*IPFc*/ - HAS_OPTION(XTENSA_OPTION_ICACHE); - gen_window_check1(dc, RRI8_S); - break; - - case 13: /*ICEc*/ - switch (OP1) { - case 0: /*IPFLl*/ - HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_icache_hit_test4(); - } - break; - - case 2: /*IHUl*/ - HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_icache_hit_test4(); - } - break; - - case 3: /*IIUl*/ - HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI4_S); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 14: /*IHIc*/ - HAS_OPTION(XTENSA_OPTION_ICACHE); - gen_icache_hit_test8(); - break; - - case 15: /*IIIc*/ - HAS_OPTION(XTENSA_OPTION_ICACHE); - if (gen_check_privilege(dc)) { - gen_window_check1(dc, RRI8_S); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - -#undef gen_icache_hit_test -#undef gen_icache_hit_test4 -#undef gen_icache_hit_test8 - - case 9: /*L16SI*/ - gen_load_store(ld16s, 1); - break; -#undef gen_load_store - - case 10: /*MOVI*/ - if (gen_window_check1(dc, RRI8_T)) { - tcg_gen_movi_i32(cpu_R[RRI8_T], - RRI8_IMM8 | (RRI8_S << 8) | - ((RRI8_S & 0x8) ? 0xfffff000 : 0)); - } - break; - -#define gen_load_store_no_hw_align(type) do { \ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \ - TCGv_i32 addr = tcg_temp_local_new_i32(); \ - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \ - gen_load_store_alignment(dc, 2, addr, true); \ - tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \ - tcg_temp_free(addr); \ - } \ - } while (0) - - case 11: /*L32AIy*/ - HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); - gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/ - break; - - case 12: /*ADDI*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE); - } - break; - - case 13: /*ADDMI*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], - RRI8_IMM8_SE << 8); - } - break; - - case 14: /*S32C1Iy*/ - HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE); - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - TCGLabel *label = gen_new_label(); - TCGv_i32 tmp = tcg_temp_local_new_i32(); - TCGv_i32 addr = tcg_temp_local_new_i32(); - TCGv_i32 tpc; - - tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]); - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); - gen_load_store_alignment(dc, 2, addr, true); - - tpc = tcg_const_i32(dc->pc); - gen_helper_check_atomctl(cpu_env, tpc, addr); - tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring); - tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T], - cpu_SR[SCOMPARE1], label); - - tcg_gen_qemu_st32(tmp, addr, dc->cring); - - gen_set_label(label); - tcg_temp_free(tpc); - tcg_temp_free(addr); - tcg_temp_free(tmp); - } - break; - - case 15: /*S32RIy*/ - HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO); - gen_load_store_no_hw_align(st32); /*TODO release?*/ - break; -#undef gen_load_store_no_hw_align - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 3: /*LSCIp*/ - switch (RRI8_R) { - case 0: /*LSIf*/ - case 4: /*SSIf*/ - case 8: /*LSIUf*/ - case 12: /*SSIUf*/ - HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - if (gen_window_check1(dc, RRI8_S) && - gen_check_cpenable(dc, 0)) { - TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); - gen_load_store_alignment(dc, 2, addr, false); - if (RRI8_R & 0x4) { - tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring); - } else { - tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring); - } - if (RRI8_R & 0x8) { - tcg_gen_mov_i32(cpu_R[RRI8_S], addr); - } - tcg_temp_free(addr); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - case 4: /*MAC16d*/ - HAS_OPTION(XTENSA_OPTION_MAC16); - { - enum { - MAC16_UMUL = 0x0, - MAC16_MUL = 0x4, - MAC16_MULA = 0x8, - MAC16_MULS = 0xc, - MAC16_NONE = 0xf, - } op = OP1 & 0xc; - bool is_m1_sr = (OP2 & 0x3) == 2; - bool is_m2_sr = (OP2 & 0xc) == 0; - uint32_t ld_offset = 0; - - if (OP2 > 9) { - RESERVED(); - } - - switch (OP2 & 2) { - case 0: /*MACI?/MACC?*/ - is_m1_sr = true; - ld_offset = (OP2 & 1) ? -4 : 4; - - if (OP2 >= 8) { /*MACI/MACC*/ - if (OP1 == 0) { /*LDINC/LDDEC*/ - op = MAC16_NONE; - } else { - RESERVED(); - } - } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/ - RESERVED(); - } - break; - - case 2: /*MACD?/MACA?*/ - if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/ - RESERVED(); - } - break; - } - - if (op != MAC16_NONE) { - if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) { - break; - } - if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) { - break; - } - } - - if (ld_offset && !gen_window_check1(dc, RRR_S)) { - break; - } - - { - TCGv_i32 vaddr = tcg_temp_new_i32(); - TCGv_i32 mem32 = tcg_temp_new_i32(); - - if (ld_offset) { - tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset); - gen_load_store_alignment(dc, 2, vaddr, false); - tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); - } - if (op != MAC16_NONE) { - TCGv_i32 m1 = gen_mac16_m( - is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S], - OP1 & 1, op == MAC16_UMUL); - TCGv_i32 m2 = gen_mac16_m( - is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T], - OP1 & 2, op == MAC16_UMUL); - - if (op == MAC16_MUL || op == MAC16_UMUL) { - tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); - if (op == MAC16_UMUL) { - tcg_gen_movi_i32(cpu_SR[ACCHI], 0); - } else { - tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); - } - } else { - TCGv_i32 lo = tcg_temp_new_i32(); - TCGv_i32 hi = tcg_temp_new_i32(); - - tcg_gen_mul_i32(lo, m1, m2); - tcg_gen_sari_i32(hi, lo, 31); - if (op == MAC16_MULA) { - tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], - cpu_SR[ACCLO], cpu_SR[ACCHI], - lo, hi); - } else { - tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], - cpu_SR[ACCLO], cpu_SR[ACCHI], - lo, hi); - } - tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); - } - tcg_temp_free(m1); - tcg_temp_free(m2); - } - if (ld_offset) { - tcg_gen_mov_i32(cpu_R[RRR_S], vaddr); - tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32); - } - tcg_temp_free(vaddr); - tcg_temp_free(mem32); - } - } - break; - - case 5: /*CALLN*/ - switch (CALL_N) { - case 0: /*CALL0*/ - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); - gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); - break; - - case 1: /*CALL4w*/ - case 2: /*CALL8w*/ - case 3: /*CALL12w*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - if (gen_window_check1(dc, CALL_N << 2)) { - gen_callwi(dc, CALL_N, - (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0); - } - break; - } - break; - - case 6: /*SI*/ - switch (CALL_N) { - case 0: /*J*/ - gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0); - break; - - case 1: /*BZ*/ - if (gen_window_check1(dc, BRI12_S)) { - static const TCGCond cond[] = { - TCG_COND_EQ, /*BEQZ*/ - TCG_COND_NE, /*BNEZ*/ - TCG_COND_LT, /*BLTZ*/ - TCG_COND_GE, /*BGEZ*/ - }; - - gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0, - 4 + BRI12_IMM12_SE); - } - break; - - case 2: /*BI0*/ - if (gen_window_check1(dc, BRI8_S)) { - static const TCGCond cond[] = { - TCG_COND_EQ, /*BEQI*/ - TCG_COND_NE, /*BNEI*/ - TCG_COND_LT, /*BLTI*/ - TCG_COND_GE, /*BGEI*/ - }; - - gen_brcondi(dc, cond[BRI8_M & 3], - cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE); - } - break; - - case 3: /*BI1*/ - switch (BRI8_M) { - case 0: /*ENTRYw*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 pc = tcg_const_i32(dc->pc); - TCGv_i32 s = tcg_const_i32(BRI12_S); - TCGv_i32 imm = tcg_const_i32(BRI12_IMM12); - gen_helper_entry(cpu_env, pc, s, imm); - tcg_temp_free(imm); - tcg_temp_free(s); - tcg_temp_free(pc); - /* This can change tb->flags, so exit tb */ - gen_jumpi_check_loop_end(dc, -1); - } - break; - - case 1: /*B1*/ - switch (BRI8_R) { - case 0: /*BFp*/ - case 1: /*BTp*/ - HAS_OPTION(XTENSA_OPTION_BOOLEAN); - { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S); - gen_brcondi(dc, - BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ, - tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - - case 8: /*LOOP*/ - case 9: /*LOOPNEZ*/ - case 10: /*LOOPGTZ*/ - HAS_OPTION(XTENSA_OPTION_LOOP); - if (gen_window_check1(dc, RRI8_S)) { - uint32_t lend = dc->pc + RRI8_IMM8 + 4; - TCGv_i32 tmp = tcg_const_i32(lend); - - tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1); - tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); - gen_helper_wsr_lend(cpu_env, tmp); - tcg_temp_free(tmp); - - if (BRI8_R > 8) { - TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32( - BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT, - cpu_R[RRI8_S], 0, label); - gen_jumpi(dc, lend, 1); - gen_set_label(label); - } - - gen_jumpi(dc, dc->next_pc, 0); - } - break; - - default: /*reserved*/ - RESERVED(); - break; - - } - break; - - case 2: /*BLTUI*/ - case 3: /*BGEUI*/ - if (gen_window_check1(dc, BRI8_S)) { - gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU, - cpu_R[BRI8_S], B4CONSTU[BRI8_R], - 4 + BRI8_IMM8_SE); - } - break; - } - break; + dc->next_pc = dc->pc + len; + for (i = 1; i < len; ++i) { + b[i] = cpu_ldub_code(env, dc->pc + i); + } + xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len); + fmt = xtensa_format_decode(isa, dc->insnbuf); + if (fmt == XTENSA_UNDEFINED) { + qemu_log_mask(LOG_GUEST_ERROR, + "unrecognized instruction format (pc = %08x)\n", + dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; + } + slots = xtensa_format_num_slots(isa, fmt); + for (slot = 0; slot < slots; ++slot) { + xtensa_opcode opc; + unsigned opnd, vopnd, opnds; + uint32_t raw_arg[MAX_OPCODE_ARGS]; + uint32_t arg[MAX_OPCODE_ARGS]; + XtensaOpcodeOps *ops; + + dc->raw_arg = raw_arg; + + xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); + opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); + if (opc == XTENSA_UNDEFINED) { + qemu_log_mask(LOG_GUEST_ERROR, + "unrecognized opcode in slot %d (pc = %08x)\n", + slot, dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; } - break; - - case 7: /*B*/ - { - TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ; - - switch (RRI8_R & 7) { - case 0: /*BNONE*/ /*BANY*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); - gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - - case 1: /*BEQ*/ /*BNE*/ - case 2: /*BLT*/ /*BGE*/ - case 3: /*BLTU*/ /*BGEU*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - static const TCGCond cond[] = { - [1] = TCG_COND_EQ, - [2] = TCG_COND_LT, - [3] = TCG_COND_LTU, - [9] = TCG_COND_NE, - [10] = TCG_COND_GE, - [11] = TCG_COND_GEU, - }; - gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T], - 4 + RRI8_IMM8_SE); + opnds = xtensa_opcode_num_operands(isa, opc); + + for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + if (xtensa_operand_is_visible(isa, opc, opnd)) { + uint32_t v; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + raw_arg[vopnd] = v; + if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { + xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); } - break; - - case 4: /*BALL*/ /*BNALL*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]); - gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T], - 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - - case 5: /*BBC*/ /*BBS*/ - if (gen_window_check2(dc, RRI8_S, RRI8_T)) { -#ifdef TARGET_WORDS_BIGENDIAN - TCGv_i32 bit = tcg_const_i32(0x80000000); -#else - TCGv_i32 bit = tcg_const_i32(0x00000001); -#endif - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_shr_i32(bit, bit, tmp); -#else - tcg_gen_shl_i32(bit, bit, tmp); -#endif - tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit); - gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - tcg_temp_free(bit); - } - break; - - case 6: /*BBCI*/ /*BBSI*/ - case 7: - if (gen_window_check1(dc, RRI8_S)) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_R[RRI8_S], -#ifdef TARGET_WORDS_BIGENDIAN - 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T)); -#else - 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T)); -#endif - gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE); - tcg_temp_free(tmp); - } - break; - + arg[vopnd] = v; + ++vopnd; } } - break; - -#define gen_narrow_load_store(type) do { \ - if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \ - TCGv_i32 addr = tcg_temp_new_i32(); \ - tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ - gen_load_store_alignment(dc, 2, addr, false); \ - tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \ - tcg_temp_free(addr); \ - } \ - } while (0) - - case 8: /*L32I.Nn*/ - gen_narrow_load_store(ld32u); - break; - - case 9: /*S32I.Nn*/ - gen_narrow_load_store(st32); - break; -#undef gen_narrow_load_store - - case 10: /*ADD.Nn*/ - if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) { - tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); - } - break; - - case 11: /*ADDI.Nn*/ - if (gen_window_check2(dc, RRRN_R, RRRN_S)) { - tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], - RRRN_T ? RRRN_T : -1); - } - break; - - case 12: /*ST2n*/ - if (!gen_window_check1(dc, RRRN_S)) { - break; - } - if (RRRN_T < 8) { /*MOVI.Nn*/ - tcg_gen_movi_i32(cpu_R[RRRN_S], - RRRN_R | (RRRN_T << 4) | - ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); - } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ - TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ; - - gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0, - 4 + (RRRN_R | ((RRRN_T & 3) << 4))); - } - break; - - case 13: /*ST3n*/ - switch (RRRN_R) { - case 0: /*MOV.Nn*/ - if (gen_window_check2(dc, RRRN_S, RRRN_T)) { - tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); - } - break; - - case 15: /*S3*/ - switch (RRRN_T) { - case 0: /*RET.Nn*/ - gen_jump(dc, cpu_R[0]); - break; - - case 1: /*RETW.Nn*/ - HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); - { - TCGv_i32 tmp = tcg_const_i32(dc->pc); - gen_helper_retw(tmp, cpu_env, tmp); - gen_jump(dc, tmp); - tcg_temp_free(tmp); - } - break; - - case 2: /*BREAK.Nn*/ - HAS_OPTION(XTENSA_OPTION_DEBUG); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_BN); - } - break; - - case 3: /*NOP.Nn*/ - break; - - case 6: /*ILL.Nn*/ - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); - break; - - default: /*reserved*/ - RESERVED(); - break; - } - break; - - default: /*reserved*/ - RESERVED(); - break; + ops = dc->config->opcode_ops[opc]; + if (ops) { + ops->translate(dc, arg, ops->par); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "unimplemented opcode '%s' in slot %d (pc = %08x)\n", + xtensa_opcode_name(isa, opc), slot, dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; } - break; - - default: /*reserved*/ - RESERVED(); - break; } - if (dc->is_jmp == DISAS_NEXT) { gen_check_loop_end(dc, 0); } dc->pc = dc->next_pc; - - return; - -invalid_opcode: - qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc); - gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); -#undef HAS_OPTION } static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) { uint8_t b0 = cpu_ldub_code(env, dc->pc); - return xtensa_op0_insn_len(OP0); + return xtensa_op0_insn_len(dc, b0); } static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) @@ -3151,7 +1071,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); - init_litbase(&dc); + if (dc.config->isa) { + dc.insnbuf = xtensa_insnbuf_alloc(dc.config->isa); + dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); + } + init_sar_tracker(&dc); if (dc.icount) { dc.next_icount = tcg_temp_local_new_i32(); @@ -3226,11 +1150,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && !tcg_op_buf_full()); done: - reset_litbase(&dc); reset_sar_tracker(&dc); if (dc.icount) { tcg_temp_free(dc.next_icount); } + if (dc.config->isa) { + xtensa_insnbuf_free(dc.config->isa, dc.insnbuf); + xtensa_insnbuf_free(dc.config->isa, dc.slotbuf); + } if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); @@ -3312,3 +1239,3612 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, { env->pc = data[0]; } + +static int compare_opcode_ops(const void *a, const void *b) +{ + return strcmp((const char *)a, + ((const XtensaOpcodeOps *)b)->name); +} + +XtensaOpcodeOps * +xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, + const char *name) +{ + XtensaOpcodeOps *ops; + + ops = bsearch(name, t->opcode, t->num_opcodes, + sizeof(XtensaOpcodeOps), compare_opcode_ops); + return ops; +} + +static void translate_abs(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 neg = tcg_temp_new_i32(); + + tcg_gen_neg_i32(neg, cpu_R[arg[1]]); + tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]], + cpu_R[arg[1]], zero, cpu_R[arg[1]], neg); + tcg_temp_free(neg); + tcg_temp_free(zero); + } +} + +static void translate_add(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_addi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_addx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); + tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_temp_free(tmp); + } +} + +static void translate_all(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + uint32_t shift = par[1]; + TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_and_i32(tmp, cpu_SR[BR], mask); + if (par[0]) { + tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]); + } else { + tcg_gen_add_i32(tmp, tmp, mask); + } + tcg_gen_shri_i32(tmp, tmp, arg[1] + shift); + tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], + tmp, arg[0], 1); + tcg_temp_free(mask); + tcg_temp_free(tmp); +} + +static void translate_and(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_ball(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); + gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]); + tcg_temp_free(tmp); + } +} + +static void translate_bany(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); + gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_temp_free(tmp); + } +} + +static void translate_b(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_bb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { +#ifdef TARGET_WORDS_BIGENDIAN + TCGv_i32 bit = tcg_const_i32(0x80000000u); +#else + TCGv_i32 bit = tcg_const_i32(0x00000001u); +#endif + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_shr_i32(bit, bit, tmp); +#else + tcg_gen_shl_i32(bit, bit, tmp); +#endif + tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit); + gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_temp_free(tmp); + tcg_temp_free(bit); + } +} + +static void translate_bbi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]); +#else + tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]); +#endif + gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_temp_free(tmp); + } +} + +static void translate_bi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]); + } +} + +static void translate_bz(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]); + } +} + +enum { + BOOLEAN_AND, + BOOLEAN_ANDC, + BOOLEAN_OR, + BOOLEAN_ORC, + BOOLEAN_XOR, +}; + +static void translate_boolean(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { + [BOOLEAN_AND] = tcg_gen_and_i32, + [BOOLEAN_ANDC] = tcg_gen_andc_i32, + [BOOLEAN_OR] = tcg_gen_or_i32, + [BOOLEAN_ORC] = tcg_gen_orc_i32, + [BOOLEAN_XOR] = tcg_gen_xor_i32, + }; + + TCGv_i32 tmp1 = tcg_temp_new_i32(); + TCGv_i32 tmp2 = tcg_temp_new_i32(); + + tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]); + tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]); + op[par[0]](tmp1, tmp1, tmp2); + tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); +} + +static void translate_bp(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]); + gen_brcondi(dc, par[0], tmp, 0, arg[1]); + tcg_temp_free(tmp); +} + +static void translate_break(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (dc->debug) { + gen_debug_exception(dc, par[0]); + } +} + +static void translate_call0(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + gen_jumpi(dc, arg[0], 0); +} + +static void translate_callw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, par[0] << 2)) { + gen_callwi(dc, par[0], arg[0], 0); + } +} + +static void translate_callx0(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + gen_jump(dc, tmp); + tcg_temp_free(tmp); + } +} + +static void translate_callxw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], par[0] << 2)) { + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + gen_callw(dc, par[0], tmp); + tcg_temp_free(tmp); + } +} + +static void translate_clamps(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]); + TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1); + + tcg_gen_movcond_i32(TCG_COND_GT, tmp1, + cpu_R[arg[1]], tmp1, cpu_R[arg[1]], tmp1); + tcg_gen_movcond_i32(TCG_COND_LT, cpu_R[arg[0]], + tmp1, tmp2, tmp1, tmp2); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + } +} + +static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); +} + +static void translate_const16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 c = tcg_const_i32(arg[1]); + + tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); + tcg_temp_free(c); + } +} + +/* par[0]: privileged, par[1]: check memory access */ +static void translate_dcache(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if ((!par[0] || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0]) && par[1]) { + TCGv_i32 addr = tcg_temp_new_i32(); + TCGv_i32 res = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + tcg_gen_qemu_ld8u(res, addr, dc->cring); + tcg_temp_free(addr); + tcg_temp_free(res); + } +} + +static void translate_depbits(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]], + arg[2], arg[3]); + } +} + +static void translate_entry(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 pc = tcg_const_i32(dc->pc); + TCGv_i32 s = tcg_const_i32(arg[0]); + TCGv_i32 imm = tcg_const_i32(arg[1]); + gen_helper_entry(cpu_env, pc, s, imm); + tcg_temp_free(imm); + tcg_temp_free(s); + tcg_temp_free(pc); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); +} + +static void translate_extui(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + int maskimm = (1 << arg[3]) - 1; + + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]); + tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm); + tcg_temp_free(tmp); + } +} + +/* par[0]: privileged, par[1]: check memory access */ +static void translate_icache(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if ((!par[0] || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0]) && par[1]) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_movi_i32(cpu_pc, dc->pc); + tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + gen_helper_itlb_hit_test(cpu_env, addr); + tcg_temp_free(addr); + } +} + +static void translate_itlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check1(dc, arg[0])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); + /* This could change memory mapping, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); + tcg_temp_free(dtlb); + } +} + +static void translate_ill(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); +} + +static void translate_j(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_jumpi(dc, arg[0], 0); +} + +static void translate_jx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_jump(dc, cpu_R[arg[0]]); + } +} + +static void translate_l32e(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_temp_free(addr); + } +} + +static void translate_ldst(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + if (par[0] & MO_SIZE) { + gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); + } + if (par[2]) { + tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + } else { + tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + } + tcg_temp_free(addr); + } +} + +static void translate_l32r(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp; + + if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + tmp = tcg_const_i32(dc->raw_arg[1] - 1); + tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); + } else { + tmp = tcg_const_i32(arg[1]); + } + tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); + tcg_temp_free(tmp); + } +} + +static void translate_loop(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + uint32_t lend = arg[1]; + TCGv_i32 tmp = tcg_const_i32(lend); + + tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); + tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); + gen_helper_wsr_lend(cpu_env, tmp); + tcg_temp_free(tmp); + + if (par[0] != TCG_COND_NEVER) { + TCGLabel *label = gen_new_label(); + tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label); + gen_jumpi(dc, lend, 1); + gen_set_label(label); + } + + gen_jumpi(dc, dc->next_pc, 0); + } +} + +enum { + MAC16_UMUL, + MAC16_MUL, + MAC16_MULA, + MAC16_MULS, + MAC16_NONE, +}; + +enum { + MAC16_LL, + MAC16_HL, + MAC16_LH, + MAC16_HH, + + MAC16_HX = 0x1, + MAC16_XH = 0x2, +}; + +enum { + MAC16_AA, + MAC16_AD, + MAC16_DA, + MAC16_DD, + + MAC16_XD = 0x1, + MAC16_DX = 0x2, +}; + +static void translate_mac16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + int op = par[0]; + bool is_m1_sr = par[1] & MAC16_DX; + bool is_m2_sr = par[1] & MAC16_XD; + unsigned half = par[2]; + uint32_t ld_offset = par[3]; + unsigned off = ld_offset ? 2 : 0; + uint32_t ar[3] = {0}; + unsigned n_ar = 0; + + if (op != MAC16_NONE) { + if (!is_m1_sr) { + ar[n_ar++] = arg[off]; + } + if (!is_m2_sr) { + ar[n_ar++] = arg[off + 1]; + } + } + + if (ld_offset) { + ar[n_ar++] = arg[1]; + } + + if (gen_window_check3(dc, ar[0], ar[1], ar[2])) { + TCGv_i32 vaddr = tcg_temp_new_i32(); + TCGv_i32 mem32 = tcg_temp_new_i32(); + + if (ld_offset) { + tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset); + gen_load_store_alignment(dc, 2, vaddr, false); + tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); + } + if (op != MAC16_NONE) { + TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? + cpu_SR[MR + arg[off]] : + cpu_R[arg[off]], + half & MAC16_HX, op == MAC16_UMUL); + TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? + cpu_SR[MR + arg[off + 1]] : + cpu_R[arg[off + 1]], + half & MAC16_XH, op == MAC16_UMUL); + + if (op == MAC16_MUL || op == MAC16_UMUL) { + tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2); + if (op == MAC16_UMUL) { + tcg_gen_movi_i32(cpu_SR[ACCHI], 0); + } else { + tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31); + } + } else { + TCGv_i32 lo = tcg_temp_new_i32(); + TCGv_i32 hi = tcg_temp_new_i32(); + + tcg_gen_mul_i32(lo, m1, m2); + tcg_gen_sari_i32(hi, lo, 31); + if (op == MAC16_MULA) { + tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], + cpu_SR[ACCLO], cpu_SR[ACCHI], + lo, hi); + } else { + tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], + cpu_SR[ACCLO], cpu_SR[ACCHI], + lo, hi); + } + tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); + + tcg_temp_free_i32(lo); + tcg_temp_free_i32(hi); + } + tcg_temp_free(m1); + tcg_temp_free(m2); + } + if (ld_offset) { + tcg_gen_mov_i32(cpu_R[arg[1]], vaddr); + tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32); + } + tcg_temp_free(vaddr); + tcg_temp_free(mem32); + } +} + +static void translate_minmax(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_mov(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_movcond(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], + cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]); + tcg_temp_free(zero); + } +} + +static void translate_movi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]); + } +} + +static void translate_movp(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_movcond_i32(par[0], + cpu_R[arg[0]], tmp, zero, + cpu_R[arg[1]], cpu_R[arg[0]]); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } +} + +static void translate_movsp(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 pc = tcg_const_i32(dc->pc); + gen_helper_movsp(cpu_env, pc); + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_temp_free(pc); + } +} + +static void translate_mul16(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 v1 = tcg_temp_new_i32(); + TCGv_i32 v2 = tcg_temp_new_i32(); + + if (par[0]) { + tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]); + tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]); + } else { + tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]); + tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]); + } + tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2); + tcg_temp_free(v2); + tcg_temp_free(v1); + } +} + +static void translate_mull(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_mulh(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 lo = tcg_temp_new(); + + if (par[0]) { + tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } else { + tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } + tcg_temp_free(lo); + } +} + +static void translate_neg(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_nop(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ +} + +static void translate_nsa(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_nsau(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32); + } +} + +static void translate_or(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_ptlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + tcg_temp_free(dtlb); + } +} + +static void gen_zero_check(DisasContext *dc, const uint32_t arg[]) +{ + TCGLabel *label = gen_new_label(); + + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label); + gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); + gen_set_label(label); +} + +static void translate_quos(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGLabel *label1 = gen_new_label(); + TCGLabel *label2 = gen_new_label(); + + gen_zero_check(dc, arg); + + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000, + label1); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff, + label1); + tcg_gen_movi_i32(cpu_R[arg[0]], + par[0] ? 0x80000000 : 0); + tcg_gen_br(label2); + gen_set_label(label1); + if (par[0]) { + tcg_gen_div_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } else { + tcg_gen_rem_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } + gen_set_label(label2); + } +} + +static void translate_quou(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + gen_zero_check(dc, arg); + if (par[0]) { + tcg_gen_divu_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } else { + tcg_gen_remu_i32(cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } + } +} + +static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_movi_i32(cpu_R[arg[0]], 0); + } +} + +static void translate_rer(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); + } +} + +static void translate_ret(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_jump(dc, cpu_R[0]); +} + +static void translate_retw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp = tcg_const_i32(dc->pc); + gen_helper_retw(tmp, cpu_env, tmp); + gen_jump(dc, tmp); + tcg_temp_free(tmp); +} + +static void translate_rfde(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); + } +} + +static void translate_rfe(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1]); + } +} + +static void translate_rfi(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); + } +} + +static void translate_rfw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + TCGv_i32 tmp = tcg_const_i32(1); + + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); + tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); + + if (par[0]) { + tcg_gen_andc_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + } else { + tcg_gen_or_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + } + + gen_helper_restore_owb(cpu_env); + gen_check_interrupts(dc); + gen_jump(dc, cpu_SR[EPC1]); + + tcg_temp_free(tmp); + } +} + +static void translate_rotw(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + TCGv_i32 tmp = tcg_const_i32(arg[0]); + gen_helper_rotw(cpu_env, tmp); + tcg_temp_free(tmp); + /* This can change tb->flags, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); + } +} + +static void translate_rsil(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check1(dc, arg[0])) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); + tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); + tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); + gen_check_interrupts(dc); + gen_jumpi_check_loop_end(dc, 0); + } +} + +static void translate_rsr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_sr(dc, par[0], SR_R) && + (par[0] < 64 || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0])) { + if (gen_rsr(dc, cpu_R[arg[0]], par[0])) { + gen_jumpi_check_loop_end(dc, 0); + } + } +} + +static void translate_rtlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1, + TCGv_i32 a2) = { + gen_helper_rtlb0, + gen_helper_rtlb1, + }; + + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + tcg_temp_free(dtlb); + } +} + +static void translate_rur(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + if (uregnames[par[0]].name) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]); + } else { + qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", par[0]); + } + } +} + +static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); +} + +static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + TCGLabel *label = gen_new_label(); + TCGv_i32 tmp = tcg_temp_local_new_i32(); + TCGv_i32 addr = tcg_temp_local_new_i32(); + TCGv_i32 tpc; + + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, true); + + tpc = tcg_const_i32(dc->pc); + gen_helper_check_atomctl(cpu_env, tpc, addr); + tcg_gen_qemu_ld32u(cpu_R[arg[0]], addr, dc->cring); + tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[arg[0]], + cpu_SR[SCOMPARE1], label); + + tcg_gen_qemu_st32(tmp, addr, dc->cring); + + gen_set_label(label); + tcg_temp_free(tpc); + tcg_temp_free(addr); + tcg_temp_free(tmp); + } +} + +static void translate_s32e(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_temp_free(addr); + } +} + +static void translate_salt(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_setcond_i32(par[0], + cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_sext(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + int shift = 31 - arg[2]; + + if (shift == 24) { + tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } else if (shift == 16) { + tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + } else { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift); + tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift); + tcg_temp_free(tmp); + } + } +} + +static void translate_simcall(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (semihosting_enabled()) { + if (gen_check_privilege(dc)) { + gen_helper_simcall(cpu_env); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + } +} + +/* + * Note: 64 bit ops are used here solely because SAR values + * have range 0..63 + */ +#define gen_shift_reg(cmd, reg) do { \ + TCGv_i64 tmp = tcg_temp_new_i64(); \ + tcg_gen_extu_i32_i64(tmp, reg); \ + tcg_gen_##cmd##_i64(v, v, tmp); \ + tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \ + tcg_temp_free_i64(v); \ + tcg_temp_free_i64(tmp); \ + } while (0) + +#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) + +static void translate_sll(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (dc->sar_m32_5bit) { + tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32); + } else { + TCGv_i64 v = tcg_temp_new_i64(); + TCGv_i32 s = tcg_const_i32(32); + tcg_gen_sub_i32(s, s, cpu_SR[SAR]); + tcg_gen_andi_i32(s, s, 0x3f); + tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + gen_shift_reg(shl, s); + tcg_temp_free(s); + } + } +} + +static void translate_slli(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (arg[2] == 32) { + qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined", + arg[0], arg[1]); + } + tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f); + } +} + +static void translate_sra(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (dc->sar_m32_5bit) { + tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + } else { + TCGv_i64 v = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]); + gen_shift(sar); + } + } +} + +static void translate_srai(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_src(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i64 v = tcg_temp_new_i64(); + tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]); + gen_shift(shr); + } +} + +static void translate_srl(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + if (dc->sar_m32_5bit) { + tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + } else { + TCGv_i64 v = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + gen_shift(shr); + } + } +} + +#undef gen_shift +#undef gen_shift_reg + +static void translate_srli(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + } +} + +static void translate_ssa8b(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + gen_left_shift_sar(dc, tmp); + tcg_temp_free(tmp); + } +} + +static void translate_ssa8l(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + gen_right_shift_sar(dc, tmp); + tcg_temp_free(tmp); + } +} + +static void translate_ssai(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + TCGv_i32 tmp = tcg_const_i32(arg[0]); + gen_right_shift_sar(dc, tmp); + tcg_temp_free(tmp); +} + +static void translate_ssl(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_left_shift_sar(dc, cpu_R[arg[0]]); + } +} + +static void translate_ssr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + gen_right_shift_sar(dc, cpu_R[arg[0]]); + } +} + +static void translate_sub(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_subx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); + tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_temp_free(tmp); + } +} + +static void translate_syscall(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + gen_exception_cause(dc, SYSCALL_CAUSE); +} + +static void translate_waiti(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc)) { + gen_waiti(dc, arg[0]); + } +} + +static void translate_wtlb(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + TCGv_i32 dtlb = tcg_const_i32(par[0]); + + gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); + /* This could change memory mapping, so exit tb */ + gen_jumpi_check_loop_end(dc, -1); + tcg_temp_free(dtlb); + } +} + +static void translate_wer(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_privilege(dc) && + gen_window_check2(dc, arg[0], arg[1])) { + gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + +static void translate_wsr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_sr(dc, par[0], SR_W) && + (par[0] < 64 || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0])) { + gen_wsr(dc, par[0], cpu_R[arg[0]]); + } +} + +static void translate_wur(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + if (uregnames[par[0]].name) { + gen_wur(par[0], cpu_R[arg[0]]); + } else { + qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", par[0]); + } + } +} + +static void translate_xor(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + +static void translate_xsr(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_sr(dc, par[0], SR_X) && + (par[0] < 64 || gen_check_privilege(dc)) && + gen_window_check1(dc, arg[0])) { + TCGv_i32 tmp = tcg_temp_new_i32(); + bool rsr_end, wsr_end; + + tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + rsr_end = gen_rsr(dc, cpu_R[arg[0]], par[0]); + wsr_end = gen_wsr(dc, par[0], tmp); + tcg_temp_free(tmp); + if (rsr_end && !wsr_end) { + gen_jumpi_check_loop_end(dc, 0); + } + } +} + +static const XtensaOpcodeOps core_ops[] = { + { + .name = "abs", + .translate = translate_abs, + }, { + .name = "add", + .translate = translate_add, + }, { + .name = "add.n", + .translate = translate_add, + }, { + .name = "addi", + .translate = translate_addi, + }, { + .name = "addi.n", + .translate = translate_addi, + }, { + .name = "addmi", + .translate = translate_addi, + }, { + .name = "addx2", + .translate = translate_addx, + .par = (const uint32_t[]){1}, + }, { + .name = "addx4", + .translate = translate_addx, + .par = (const uint32_t[]){2}, + }, { + .name = "addx8", + .translate = translate_addx, + .par = (const uint32_t[]){3}, + }, { + .name = "all4", + .translate = translate_all, + .par = (const uint32_t[]){true, 4}, + }, { + .name = "all8", + .translate = translate_all, + .par = (const uint32_t[]){true, 8}, + }, { + .name = "and", + .translate = translate_and, + }, { + .name = "andb", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_AND}, + }, { + .name = "andbc", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_ANDC}, + }, { + .name = "any4", + .translate = translate_all, + .par = (const uint32_t[]){false, 4}, + }, { + .name = "any8", + .translate = translate_all, + .par = (const uint32_t[]){false, 8}, + }, { + .name = "ball", + .translate = translate_ball, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bany", + .translate = translate_bany, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bbc", + .translate = translate_bb, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bbci", + .translate = translate_bbi, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bbs", + .translate = translate_bb, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bbsi", + .translate = translate_bbi, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "beq", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "beqi", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "beqz", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "beqz.n", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bf", + .translate = translate_bp, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "bge", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "bgei", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "bgeu", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_GEU}, + }, { + .name = "bgeui", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_GEU}, + }, { + .name = "bgez", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "blt", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "blti", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "bltu", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "bltui", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "bltz", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "bnall", + .translate = translate_ball, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bne", + .translate = translate_b, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnei", + .translate = translate_bi, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnez", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnez.n", + .translate = translate_bz, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "bnone", + .translate = translate_bany, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "break", + .translate = translate_break, + .par = (const uint32_t[]){DEBUGCAUSE_BI}, + }, { + .name = "break.n", + .translate = translate_break, + .par = (const uint32_t[]){DEBUGCAUSE_BN}, + }, { + .name = "bt", + .translate = translate_bp, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "call0", + .translate = translate_call0, + }, { + .name = "call12", + .translate = translate_callw, + .par = (const uint32_t[]){3}, + }, { + .name = "call4", + .translate = translate_callw, + .par = (const uint32_t[]){1}, + }, { + .name = "call8", + .translate = translate_callw, + .par = (const uint32_t[]){2}, + }, { + .name = "callx0", + .translate = translate_callx0, + }, { + .name = "callx12", + .translate = translate_callxw, + .par = (const uint32_t[]){3}, + }, { + .name = "callx4", + .translate = translate_callxw, + .par = (const uint32_t[]){1}, + }, { + .name = "callx8", + .translate = translate_callxw, + .par = (const uint32_t[]){2}, + }, { + .name = "clamps", + .translate = translate_clamps, + }, { + .name = "clrb_expstate", + .translate = translate_clrb_expstate, + }, { + .name = "const16", + .translate = translate_const16, + }, { + .name = "depbits", + .translate = translate_depbits, + }, { + .name = "dhi", + .translate = translate_dcache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "dhu", + .translate = translate_dcache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "dhwb", + .translate = translate_dcache, + .par = (const uint32_t[]){false, true}, + }, { + .name = "dhwbi", + .translate = translate_dcache, + .par = (const uint32_t[]){false, true}, + }, { + .name = "dii", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "diu", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "diwb", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "diwbi", + .translate = translate_dcache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "dpfl", + .translate = translate_dcache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "dpfr", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dpfro", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dpfw", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dpfwo", + .translate = translate_dcache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "dsync", + .translate = translate_nop, + }, { + .name = "entry", + .translate = translate_entry, + }, { + .name = "esync", + .translate = translate_nop, + }, { + .name = "excw", + .translate = translate_nop, + }, { + .name = "extui", + .translate = translate_extui, + }, { + .name = "extw", + .translate = translate_nop, + }, { + .name = "hwwdtlba", + .translate = translate_ill, + }, { + .name = "hwwitlba", + .translate = translate_ill, + }, { + .name = "idtlb", + .translate = translate_itlb, + .par = (const uint32_t[]){true}, + }, { + .name = "ihi", + .translate = translate_icache, + .par = (const uint32_t[]){false, true}, + }, { + .name = "ihu", + .translate = translate_icache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "iii", + .translate = translate_icache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "iitlb", + .translate = translate_itlb, + .par = (const uint32_t[]){false}, + }, { + .name = "iiu", + .translate = translate_icache, + .par = (const uint32_t[]){true, false}, + }, { + .name = "ill", + .translate = translate_ill, + }, { + .name = "ill.n", + .translate = translate_ill, + }, { + .name = "ipf", + .translate = translate_icache, + .par = (const uint32_t[]){false, false}, + }, { + .name = "ipfl", + .translate = translate_icache, + .par = (const uint32_t[]){true, true}, + }, { + .name = "isync", + .translate = translate_nop, + }, { + .name = "j", + .translate = translate_j, + }, { + .name = "jx", + .translate = translate_jx, + }, { + .name = "l16si", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TESW, false, false}, + }, { + .name = "l16ui", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUW, false, false}, + }, { + .name = "l32ai", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, true, false}, + }, { + .name = "l32e", + .translate = translate_l32e, + }, { + .name = "l32i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, false}, + }, { + .name = "l32i.n", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, false}, + }, { + .name = "l32r", + .translate = translate_l32r, + }, { + .name = "l8ui", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_UB, false, false}, + }, { + .name = "lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, + }, { + .name = "ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, + }, { + .name = "ldpte", + .translate = translate_ill, + }, { + .name = "loop", + .translate = translate_loop, + .par = (const uint32_t[]){TCG_COND_NEVER}, + }, { + .name = "loopgtz", + .translate = translate_loop, + .par = (const uint32_t[]){TCG_COND_GT}, + }, { + .name = "loopnez", + .translate = translate_loop, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "max", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "maxu", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_GEU}, + }, { + .name = "memw", + .translate = translate_nop, + }, { + .name = "min", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "minu", + .translate = translate_minmax, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "mov", + .translate = translate_mov, + }, { + .name = "mov.n", + .translate = translate_mov, + }, { + .name = "moveqz", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movf", + .translate = translate_movp, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movgez", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "movi", + .translate = translate_movi, + }, { + .name = "movi.n", + .translate = translate_movi, + }, { + .name = "movltz", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "movnez", + .translate = translate_movcond, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "movsp", + .translate = translate_movsp, + }, { + .name = "movt", + .translate = translate_movp, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "mul.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "mul.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "mul.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "mul.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "mul.ad.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, + }, { + .name = "mul.ad.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, + }, { + .name = "mul.ad.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, + }, { + .name = "mul.ad.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, + }, { + .name = "mul.da.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, + }, { + .name = "mul.da.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, + }, { + .name = "mul.da.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, + }, { + .name = "mul.da.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, + }, { + .name = "mul.dd.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0}, + }, { + .name = "mul.dd.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0}, + }, { + .name = "mul.dd.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0}, + }, { + .name = "mul.dd.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0}, + }, { + .name = "mul16s", + .translate = translate_mul16, + .par = (const uint32_t[]){true}, + }, { + .name = "mul16u", + .translate = translate_mul16, + .par = (const uint32_t[]){false}, + }, { + .name = "mula.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "mula.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "mula.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "mula.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "mula.ad.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, + }, { + .name = "mula.ad.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, + }, { + .name = "mula.ad.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, + }, { + .name = "mula.ad.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, + }, { + .name = "mula.da.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, + }, { + .name = "mula.da.hh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, + }, { + .name = "mula.da.hh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, + }, { + .name = "mula.da.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, + }, { + .name = "mula.da.hl.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, + }, { + .name = "mula.da.hl.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, + }, { + .name = "mula.da.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, + }, { + .name = "mula.da.lh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, + }, { + .name = "mula.da.lh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, + }, { + .name = "mula.da.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, + }, { + .name = "mula.da.ll.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, + }, { + .name = "mula.da.ll.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, + }, { + .name = "mula.dd.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0}, + }, { + .name = "mula.dd.hh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, + }, { + .name = "mula.dd.hh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, + }, { + .name = "mula.dd.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0}, + }, { + .name = "mula.dd.hl.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, + }, { + .name = "mula.dd.hl.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, + }, { + .name = "mula.dd.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0}, + }, { + .name = "mula.dd.lh.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, + }, { + .name = "mula.dd.lh.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, + }, { + .name = "mula.dd.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0}, + }, { + .name = "mula.dd.ll.lddec", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, + }, { + .name = "mula.dd.ll.ldinc", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, + }, { + .name = "mull", + .translate = translate_mull, + }, { + .name = "muls.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "muls.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "muls.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "muls.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "muls.ad.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, + }, { + .name = "muls.ad.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, + }, { + .name = "muls.ad.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, + }, { + .name = "muls.ad.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, + }, { + .name = "muls.da.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, + }, { + .name = "muls.da.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, + }, { + .name = "muls.da.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, + }, { + .name = "muls.da.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, + }, { + .name = "muls.dd.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0}, + }, { + .name = "muls.dd.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0}, + }, { + .name = "muls.dd.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0}, + }, { + .name = "muls.dd.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0}, + }, { + .name = "mulsh", + .translate = translate_mulh, + .par = (const uint32_t[]){true}, + }, { + .name = "muluh", + .translate = translate_mulh, + .par = (const uint32_t[]){false}, + }, { + .name = "neg", + .translate = translate_neg, + }, { + .name = "nop", + .translate = translate_nop, + }, { + .name = "nop.n", + .translate = translate_nop, + }, { + .name = "nsa", + .translate = translate_nsa, + }, { + .name = "nsau", + .translate = translate_nsau, + }, { + .name = "or", + .translate = translate_or, + }, { + .name = "orb", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_OR}, + }, { + .name = "orbc", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_ORC}, + }, { + .name = "pdtlb", + .translate = translate_ptlb, + .par = (const uint32_t[]){true}, + }, { + .name = "pitlb", + .translate = translate_ptlb, + .par = (const uint32_t[]){false}, + }, { + .name = "quos", + .translate = translate_quos, + .par = (const uint32_t[]){true}, + }, { + .name = "quou", + .translate = translate_quou, + .par = (const uint32_t[]){true}, + }, { + .name = "rdtlb0", + .translate = translate_rtlb, + .par = (const uint32_t[]){true, 0}, + }, { + .name = "rdtlb1", + .translate = translate_rtlb, + .par = (const uint32_t[]){true, 1}, + }, { + .name = "read_impwire", + .translate = translate_read_impwire, + }, { + .name = "rems", + .translate = translate_quos, + .par = (const uint32_t[]){false}, + }, { + .name = "remu", + .translate = translate_quou, + .par = (const uint32_t[]){false}, + }, { + .name = "rer", + .translate = translate_rer, + }, { + .name = "ret", + .translate = translate_ret, + }, { + .name = "ret.n", + .translate = translate_ret, + }, { + .name = "retw", + .translate = translate_retw, + }, { + .name = "retw.n", + .translate = translate_retw, + }, { + .name = "rfdd", + .translate = translate_ill, + }, { + .name = "rfde", + .translate = translate_rfde, + }, { + .name = "rfdo", + .translate = translate_ill, + }, { + .name = "rfe", + .translate = translate_rfe, + }, { + .name = "rfi", + .translate = translate_rfi, + }, { + .name = "rfwo", + .translate = translate_rfw, + .par = (const uint32_t[]){true}, + }, { + .name = "rfwu", + .translate = translate_rfw, + .par = (const uint32_t[]){false}, + }, { + .name = "ritlb0", + .translate = translate_rtlb, + .par = (const uint32_t[]){false, 0}, + }, { + .name = "ritlb1", + .translate = translate_rtlb, + .par = (const uint32_t[]){false, 1}, + }, { + .name = "rotw", + .translate = translate_rotw, + }, { + .name = "rsil", + .translate = translate_rsil, + }, { + .name = "rsr.176", + .translate = translate_rsr, + .par = (const uint32_t[]){176}, + }, { + .name = "rsr.208", + .translate = translate_rsr, + .par = (const uint32_t[]){208}, + }, { + .name = "rsr.acchi", + .translate = translate_rsr, + .par = (const uint32_t[]){ACCHI}, + }, { + .name = "rsr.acclo", + .translate = translate_rsr, + .par = (const uint32_t[]){ACCLO}, + }, { + .name = "rsr.atomctl", + .translate = translate_rsr, + .par = (const uint32_t[]){ATOMCTL}, + }, { + .name = "rsr.br", + .translate = translate_rsr, + .par = (const uint32_t[]){BR}, + }, { + .name = "rsr.cacheattr", + .translate = translate_rsr, + .par = (const uint32_t[]){CACHEATTR}, + }, { + .name = "rsr.ccompare0", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOMPARE}, + }, { + .name = "rsr.ccompare1", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOMPARE + 1}, + }, { + .name = "rsr.ccompare2", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOMPARE + 2}, + }, { + .name = "rsr.ccount", + .translate = translate_rsr, + .par = (const uint32_t[]){CCOUNT}, + }, { + .name = "rsr.configid0", + .translate = translate_rsr, + .par = (const uint32_t[]){CONFIGID0}, + }, { + .name = "rsr.configid1", + .translate = translate_rsr, + .par = (const uint32_t[]){CONFIGID1}, + }, { + .name = "rsr.cpenable", + .translate = translate_rsr, + .par = (const uint32_t[]){CPENABLE}, + }, { + .name = "rsr.dbreaka0", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKA}, + }, { + .name = "rsr.dbreaka1", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKA + 1}, + }, { + .name = "rsr.dbreakc0", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKC}, + }, { + .name = "rsr.dbreakc1", + .translate = translate_rsr, + .par = (const uint32_t[]){DBREAKC + 1}, + }, { + .name = "rsr.ddr", + .translate = translate_rsr, + .par = (const uint32_t[]){DDR}, + }, { + .name = "rsr.debugcause", + .translate = translate_rsr, + .par = (const uint32_t[]){DEBUGCAUSE}, + }, { + .name = "rsr.depc", + .translate = translate_rsr, + .par = (const uint32_t[]){DEPC}, + }, { + .name = "rsr.dtlbcfg", + .translate = translate_rsr, + .par = (const uint32_t[]){DTLBCFG}, + }, { + .name = "rsr.epc1", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1}, + }, { + .name = "rsr.epc2", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 1}, + }, { + .name = "rsr.epc3", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 2}, + }, { + .name = "rsr.epc4", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 3}, + }, { + .name = "rsr.epc5", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 4}, + }, { + .name = "rsr.epc6", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 5}, + }, { + .name = "rsr.epc7", + .translate = translate_rsr, + .par = (const uint32_t[]){EPC1 + 6}, + }, { + .name = "rsr.eps2", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2}, + }, { + .name = "rsr.eps3", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 1}, + }, { + .name = "rsr.eps4", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 2}, + }, { + .name = "rsr.eps5", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 3}, + }, { + .name = "rsr.eps6", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 4}, + }, { + .name = "rsr.eps7", + .translate = translate_rsr, + .par = (const uint32_t[]){EPS2 + 5}, + }, { + .name = "rsr.exccause", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCCAUSE}, + }, { + .name = "rsr.excsave1", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1}, + }, { + .name = "rsr.excsave2", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 1}, + }, { + .name = "rsr.excsave3", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 2}, + }, { + .name = "rsr.excsave4", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 3}, + }, { + .name = "rsr.excsave5", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 4}, + }, { + .name = "rsr.excsave6", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 5}, + }, { + .name = "rsr.excsave7", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCSAVE1 + 6}, + }, { + .name = "rsr.excvaddr", + .translate = translate_rsr, + .par = (const uint32_t[]){EXCVADDR}, + }, { + .name = "rsr.ibreaka0", + .translate = translate_rsr, + .par = (const uint32_t[]){IBREAKA}, + }, { + .name = "rsr.ibreaka1", + .translate = translate_rsr, + .par = (const uint32_t[]){IBREAKA + 1}, + }, { + .name = "rsr.ibreakenable", + .translate = translate_rsr, + .par = (const uint32_t[]){IBREAKENABLE}, + }, { + .name = "rsr.icount", + .translate = translate_rsr, + .par = (const uint32_t[]){ICOUNT}, + }, { + .name = "rsr.icountlevel", + .translate = translate_rsr, + .par = (const uint32_t[]){ICOUNTLEVEL}, + }, { + .name = "rsr.intclear", + .translate = translate_rsr, + .par = (const uint32_t[]){INTCLEAR}, + }, { + .name = "rsr.intenable", + .translate = translate_rsr, + .par = (const uint32_t[]){INTENABLE}, + }, { + .name = "rsr.interrupt", + .translate = translate_rsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "rsr.intset", + .translate = translate_rsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "rsr.itlbcfg", + .translate = translate_rsr, + .par = (const uint32_t[]){ITLBCFG}, + }, { + .name = "rsr.lbeg", + .translate = translate_rsr, + .par = (const uint32_t[]){LBEG}, + }, { + .name = "rsr.lcount", + .translate = translate_rsr, + .par = (const uint32_t[]){LCOUNT}, + }, { + .name = "rsr.lend", + .translate = translate_rsr, + .par = (const uint32_t[]){LEND}, + }, { + .name = "rsr.litbase", + .translate = translate_rsr, + .par = (const uint32_t[]){LITBASE}, + }, { + .name = "rsr.m0", + .translate = translate_rsr, + .par = (const uint32_t[]){MR}, + }, { + .name = "rsr.m1", + .translate = translate_rsr, + .par = (const uint32_t[]){MR + 1}, + }, { + .name = "rsr.m2", + .translate = translate_rsr, + .par = (const uint32_t[]){MR + 2}, + }, { + .name = "rsr.m3", + .translate = translate_rsr, + .par = (const uint32_t[]){MR + 3}, + }, { + .name = "rsr.memctl", + .translate = translate_rsr, + .par = (const uint32_t[]){MEMCTL}, + }, { + .name = "rsr.misc0", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC}, + }, { + .name = "rsr.misc1", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC + 1}, + }, { + .name = "rsr.misc2", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC + 2}, + }, { + .name = "rsr.misc3", + .translate = translate_rsr, + .par = (const uint32_t[]){MISC + 3}, + }, { + .name = "rsr.prid", + .translate = translate_rsr, + .par = (const uint32_t[]){PRID}, + }, { + .name = "rsr.ps", + .translate = translate_rsr, + .par = (const uint32_t[]){PS}, + }, { + .name = "rsr.ptevaddr", + .translate = translate_rsr, + .par = (const uint32_t[]){PTEVADDR}, + }, { + .name = "rsr.rasid", + .translate = translate_rsr, + .par = (const uint32_t[]){RASID}, + }, { + .name = "rsr.sar", + .translate = translate_rsr, + .par = (const uint32_t[]){SAR}, + }, { + .name = "rsr.scompare1", + .translate = translate_rsr, + .par = (const uint32_t[]){SCOMPARE1}, + }, { + .name = "rsr.vecbase", + .translate = translate_rsr, + .par = (const uint32_t[]){VECBASE}, + }, { + .name = "rsr.windowbase", + .translate = translate_rsr, + .par = (const uint32_t[]){WINDOW_BASE}, + }, { + .name = "rsr.windowstart", + .translate = translate_rsr, + .par = (const uint32_t[]){WINDOW_START}, + }, { + .name = "rsync", + .translate = translate_nop, + }, { + .name = "rur.expstate", + .translate = translate_rur, + .par = (const uint32_t[]){EXPSTATE}, + }, { + .name = "rur.fcr", + .translate = translate_rur, + .par = (const uint32_t[]){FCR}, + }, { + .name = "rur.fsr", + .translate = translate_rur, + .par = (const uint32_t[]){FSR}, + }, { + .name = "rur.threadptr", + .translate = translate_rur, + .par = (const uint32_t[]){THREADPTR}, + }, { + .name = "s16i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUW, false, true}, + }, { + .name = "s32c1i", + .translate = translate_s32c1i, + }, { + .name = "s32e", + .translate = translate_s32e, + }, { + .name = "s32i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, true}, + }, { + .name = "s32i.n", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, true}, + }, { + .name = "s32nb", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, false, true}, + }, { + .name = "s32ri", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_TEUL, true, true}, + }, { + .name = "s8i", + .translate = translate_ldst, + .par = (const uint32_t[]){MO_UB, false, true}, + }, { + .name = "salt", + .translate = translate_salt, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "saltu", + .translate = translate_salt, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { + .name = "setb_expstate", + .translate = translate_setb_expstate, + }, { + .name = "sext", + .translate = translate_sext, + }, { + .name = "simcall", + .translate = translate_simcall, + }, { + .name = "sll", + .translate = translate_sll, + }, { + .name = "slli", + .translate = translate_slli, + }, { + .name = "sra", + .translate = translate_sra, + }, { + .name = "srai", + .translate = translate_srai, + }, { + .name = "src", + .translate = translate_src, + }, { + .name = "srl", + .translate = translate_srl, + }, { + .name = "srli", + .translate = translate_srli, + }, { + .name = "ssa8b", + .translate = translate_ssa8b, + }, { + .name = "ssa8l", + .translate = translate_ssa8l, + }, { + .name = "ssai", + .translate = translate_ssai, + }, { + .name = "ssl", + .translate = translate_ssl, + }, { + .name = "ssr", + .translate = translate_ssr, + }, { + .name = "sub", + .translate = translate_sub, + }, { + .name = "subx2", + .translate = translate_subx, + .par = (const uint32_t[]){1}, + }, { + .name = "subx4", + .translate = translate_subx, + .par = (const uint32_t[]){2}, + }, { + .name = "subx8", + .translate = translate_subx, + .par = (const uint32_t[]){3}, + }, { + .name = "syscall", + .translate = translate_syscall, + }, { + .name = "umul.aa.hh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, + }, { + .name = "umul.aa.hl", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, + }, { + .name = "umul.aa.lh", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, + }, { + .name = "umul.aa.ll", + .translate = translate_mac16, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, + }, { + .name = "waiti", + .translate = translate_waiti, + }, { + .name = "wdtlb", + .translate = translate_wtlb, + .par = (const uint32_t[]){true}, + }, { + .name = "wer", + .translate = translate_wer, + }, { + .name = "witlb", + .translate = translate_wtlb, + .par = (const uint32_t[]){false}, + }, { + .name = "wrmsk_expstate", + .translate = translate_wrmsk_expstate, + }, { + .name = "wsr.176", + .translate = translate_wsr, + .par = (const uint32_t[]){176}, + }, { + .name = "wsr.208", + .translate = translate_wsr, + .par = (const uint32_t[]){208}, + }, { + .name = "wsr.acchi", + .translate = translate_wsr, + .par = (const uint32_t[]){ACCHI}, + }, { + .name = "wsr.acclo", + .translate = translate_wsr, + .par = (const uint32_t[]){ACCLO}, + }, { + .name = "wsr.atomctl", + .translate = translate_wsr, + .par = (const uint32_t[]){ATOMCTL}, + }, { + .name = "wsr.br", + .translate = translate_wsr, + .par = (const uint32_t[]){BR}, + }, { + .name = "wsr.cacheattr", + .translate = translate_wsr, + .par = (const uint32_t[]){CACHEATTR}, + }, { + .name = "wsr.ccompare0", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOMPARE}, + }, { + .name = "wsr.ccompare1", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOMPARE + 1}, + }, { + .name = "wsr.ccompare2", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOMPARE + 2}, + }, { + .name = "wsr.ccount", + .translate = translate_wsr, + .par = (const uint32_t[]){CCOUNT}, + }, { + .name = "wsr.configid0", + .translate = translate_wsr, + .par = (const uint32_t[]){CONFIGID0}, + }, { + .name = "wsr.configid1", + .translate = translate_wsr, + .par = (const uint32_t[]){CONFIGID1}, + }, { + .name = "wsr.cpenable", + .translate = translate_wsr, + .par = (const uint32_t[]){CPENABLE}, + }, { + .name = "wsr.dbreaka0", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKA}, + }, { + .name = "wsr.dbreaka1", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKA + 1}, + }, { + .name = "wsr.dbreakc0", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKC}, + }, { + .name = "wsr.dbreakc1", + .translate = translate_wsr, + .par = (const uint32_t[]){DBREAKC + 1}, + }, { + .name = "wsr.ddr", + .translate = translate_wsr, + .par = (const uint32_t[]){DDR}, + }, { + .name = "wsr.debugcause", + .translate = translate_wsr, + .par = (const uint32_t[]){DEBUGCAUSE}, + }, { + .name = "wsr.depc", + .translate = translate_wsr, + .par = (const uint32_t[]){DEPC}, + }, { + .name = "wsr.dtlbcfg", + .translate = translate_wsr, + .par = (const uint32_t[]){DTLBCFG}, + }, { + .name = "wsr.epc1", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1}, + }, { + .name = "wsr.epc2", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 1}, + }, { + .name = "wsr.epc3", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 2}, + }, { + .name = "wsr.epc4", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 3}, + }, { + .name = "wsr.epc5", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 4}, + }, { + .name = "wsr.epc6", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 5}, + }, { + .name = "wsr.epc7", + .translate = translate_wsr, + .par = (const uint32_t[]){EPC1 + 6}, + }, { + .name = "wsr.eps2", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2}, + }, { + .name = "wsr.eps3", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 1}, + }, { + .name = "wsr.eps4", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 2}, + }, { + .name = "wsr.eps5", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 3}, + }, { + .name = "wsr.eps6", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 4}, + }, { + .name = "wsr.eps7", + .translate = translate_wsr, + .par = (const uint32_t[]){EPS2 + 5}, + }, { + .name = "wsr.exccause", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCCAUSE}, + }, { + .name = "wsr.excsave1", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1}, + }, { + .name = "wsr.excsave2", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 1}, + }, { + .name = "wsr.excsave3", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 2}, + }, { + .name = "wsr.excsave4", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 3}, + }, { + .name = "wsr.excsave5", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 4}, + }, { + .name = "wsr.excsave6", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 5}, + }, { + .name = "wsr.excsave7", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCSAVE1 + 6}, + }, { + .name = "wsr.excvaddr", + .translate = translate_wsr, + .par = (const uint32_t[]){EXCVADDR}, + }, { + .name = "wsr.ibreaka0", + .translate = translate_wsr, + .par = (const uint32_t[]){IBREAKA}, + }, { + .name = "wsr.ibreaka1", + .translate = translate_wsr, + .par = (const uint32_t[]){IBREAKA + 1}, + }, { + .name = "wsr.ibreakenable", + .translate = translate_wsr, + .par = (const uint32_t[]){IBREAKENABLE}, + }, { + .name = "wsr.icount", + .translate = translate_wsr, + .par = (const uint32_t[]){ICOUNT}, + }, { + .name = "wsr.icountlevel", + .translate = translate_wsr, + .par = (const uint32_t[]){ICOUNTLEVEL}, + }, { + .name = "wsr.intclear", + .translate = translate_wsr, + .par = (const uint32_t[]){INTCLEAR}, + }, { + .name = "wsr.intenable", + .translate = translate_wsr, + .par = (const uint32_t[]){INTENABLE}, + }, { + .name = "wsr.interrupt", + .translate = translate_wsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "wsr.intset", + .translate = translate_wsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "wsr.itlbcfg", + .translate = translate_wsr, + .par = (const uint32_t[]){ITLBCFG}, + }, { + .name = "wsr.lbeg", + .translate = translate_wsr, + .par = (const uint32_t[]){LBEG}, + }, { + .name = "wsr.lcount", + .translate = translate_wsr, + .par = (const uint32_t[]){LCOUNT}, + }, { + .name = "wsr.lend", + .translate = translate_wsr, + .par = (const uint32_t[]){LEND}, + }, { + .name = "wsr.litbase", + .translate = translate_wsr, + .par = (const uint32_t[]){LITBASE}, + }, { + .name = "wsr.m0", + .translate = translate_wsr, + .par = (const uint32_t[]){MR}, + }, { + .name = "wsr.m1", + .translate = translate_wsr, + .par = (const uint32_t[]){MR + 1}, + }, { + .name = "wsr.m2", + .translate = translate_wsr, + .par = (const uint32_t[]){MR + 2}, + }, { + .name = "wsr.m3", + .translate = translate_wsr, + .par = (const uint32_t[]){MR + 3}, + }, { + .name = "wsr.memctl", + .translate = translate_wsr, + .par = (const uint32_t[]){MEMCTL}, + }, { + .name = "wsr.misc0", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC}, + }, { + .name = "wsr.misc1", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC + 1}, + }, { + .name = "wsr.misc2", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC + 2}, + }, { + .name = "wsr.misc3", + .translate = translate_wsr, + .par = (const uint32_t[]){MISC + 3}, + }, { + .name = "wsr.mmid", + .translate = translate_wsr, + .par = (const uint32_t[]){MMID}, + }, { + .name = "wsr.prid", + .translate = translate_wsr, + .par = (const uint32_t[]){PRID}, + }, { + .name = "wsr.ps", + .translate = translate_wsr, + .par = (const uint32_t[]){PS}, + }, { + .name = "wsr.ptevaddr", + .translate = translate_wsr, + .par = (const uint32_t[]){PTEVADDR}, + }, { + .name = "wsr.rasid", + .translate = translate_wsr, + .par = (const uint32_t[]){RASID}, + }, { + .name = "wsr.sar", + .translate = translate_wsr, + .par = (const uint32_t[]){SAR}, + }, { + .name = "wsr.scompare1", + .translate = translate_wsr, + .par = (const uint32_t[]){SCOMPARE1}, + }, { + .name = "wsr.vecbase", + .translate = translate_wsr, + .par = (const uint32_t[]){VECBASE}, + }, { + .name = "wsr.windowbase", + .translate = translate_wsr, + .par = (const uint32_t[]){WINDOW_BASE}, + }, { + .name = "wsr.windowstart", + .translate = translate_wsr, + .par = (const uint32_t[]){WINDOW_START}, + }, { + .name = "wur.expstate", + .translate = translate_wur, + .par = (const uint32_t[]){EXPSTATE}, + }, { + .name = "wur.fcr", + .translate = translate_wur, + .par = (const uint32_t[]){FCR}, + }, { + .name = "wur.fsr", + .translate = translate_wur, + .par = (const uint32_t[]){FSR}, + }, { + .name = "wur.threadptr", + .translate = translate_wur, + .par = (const uint32_t[]){THREADPTR}, + }, { + .name = "xor", + .translate = translate_xor, + }, { + .name = "xorb", + .translate = translate_boolean, + .par = (const uint32_t[]){BOOLEAN_XOR}, + }, { + .name = "xsr.176", + .translate = translate_xsr, + .par = (const uint32_t[]){176}, + }, { + .name = "xsr.208", + .translate = translate_xsr, + .par = (const uint32_t[]){208}, + }, { + .name = "xsr.acchi", + .translate = translate_xsr, + .par = (const uint32_t[]){ACCHI}, + }, { + .name = "xsr.acclo", + .translate = translate_xsr, + .par = (const uint32_t[]){ACCLO}, + }, { + .name = "xsr.atomctl", + .translate = translate_xsr, + .par = (const uint32_t[]){ATOMCTL}, + }, { + .name = "xsr.br", + .translate = translate_xsr, + .par = (const uint32_t[]){BR}, + }, { + .name = "xsr.cacheattr", + .translate = translate_xsr, + .par = (const uint32_t[]){CACHEATTR}, + }, { + .name = "xsr.ccompare0", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOMPARE}, + }, { + .name = "xsr.ccompare1", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOMPARE + 1}, + }, { + .name = "xsr.ccompare2", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOMPARE + 2}, + }, { + .name = "xsr.ccount", + .translate = translate_xsr, + .par = (const uint32_t[]){CCOUNT}, + }, { + .name = "xsr.configid0", + .translate = translate_xsr, + .par = (const uint32_t[]){CONFIGID0}, + }, { + .name = "xsr.configid1", + .translate = translate_xsr, + .par = (const uint32_t[]){CONFIGID1}, + }, { + .name = "xsr.cpenable", + .translate = translate_xsr, + .par = (const uint32_t[]){CPENABLE}, + }, { + .name = "xsr.dbreaka0", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKA}, + }, { + .name = "xsr.dbreaka1", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKA + 1}, + }, { + .name = "xsr.dbreakc0", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKC}, + }, { + .name = "xsr.dbreakc1", + .translate = translate_xsr, + .par = (const uint32_t[]){DBREAKC + 1}, + }, { + .name = "xsr.ddr", + .translate = translate_xsr, + .par = (const uint32_t[]){DDR}, + }, { + .name = "xsr.debugcause", + .translate = translate_xsr, + .par = (const uint32_t[]){DEBUGCAUSE}, + }, { + .name = "xsr.depc", + .translate = translate_xsr, + .par = (const uint32_t[]){DEPC}, + }, { + .name = "xsr.dtlbcfg", + .translate = translate_xsr, + .par = (const uint32_t[]){DTLBCFG}, + }, { + .name = "xsr.epc1", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1}, + }, { + .name = "xsr.epc2", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 1}, + }, { + .name = "xsr.epc3", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 2}, + }, { + .name = "xsr.epc4", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 3}, + }, { + .name = "xsr.epc5", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 4}, + }, { + .name = "xsr.epc6", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 5}, + }, { + .name = "xsr.epc7", + .translate = translate_xsr, + .par = (const uint32_t[]){EPC1 + 6}, + }, { + .name = "xsr.eps2", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2}, + }, { + .name = "xsr.eps3", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 1}, + }, { + .name = "xsr.eps4", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 2}, + }, { + .name = "xsr.eps5", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 3}, + }, { + .name = "xsr.eps6", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 4}, + }, { + .name = "xsr.eps7", + .translate = translate_xsr, + .par = (const uint32_t[]){EPS2 + 5}, + }, { + .name = "xsr.exccause", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCCAUSE}, + }, { + .name = "xsr.excsave1", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1}, + }, { + .name = "xsr.excsave2", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 1}, + }, { + .name = "xsr.excsave3", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 2}, + }, { + .name = "xsr.excsave4", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 3}, + }, { + .name = "xsr.excsave5", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 4}, + }, { + .name = "xsr.excsave6", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 5}, + }, { + .name = "xsr.excsave7", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCSAVE1 + 6}, + }, { + .name = "xsr.excvaddr", + .translate = translate_xsr, + .par = (const uint32_t[]){EXCVADDR}, + }, { + .name = "xsr.ibreaka0", + .translate = translate_xsr, + .par = (const uint32_t[]){IBREAKA}, + }, { + .name = "xsr.ibreaka1", + .translate = translate_xsr, + .par = (const uint32_t[]){IBREAKA + 1}, + }, { + .name = "xsr.ibreakenable", + .translate = translate_xsr, + .par = (const uint32_t[]){IBREAKENABLE}, + }, { + .name = "xsr.icount", + .translate = translate_xsr, + .par = (const uint32_t[]){ICOUNT}, + }, { + .name = "xsr.icountlevel", + .translate = translate_xsr, + .par = (const uint32_t[]){ICOUNTLEVEL}, + }, { + .name = "xsr.intclear", + .translate = translate_xsr, + .par = (const uint32_t[]){INTCLEAR}, + }, { + .name = "xsr.intenable", + .translate = translate_xsr, + .par = (const uint32_t[]){INTENABLE}, + }, { + .name = "xsr.interrupt", + .translate = translate_xsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "xsr.intset", + .translate = translate_xsr, + .par = (const uint32_t[]){INTSET}, + }, { + .name = "xsr.itlbcfg", + .translate = translate_xsr, + .par = (const uint32_t[]){ITLBCFG}, + }, { + .name = "xsr.lbeg", + .translate = translate_xsr, + .par = (const uint32_t[]){LBEG}, + }, { + .name = "xsr.lcount", + .translate = translate_xsr, + .par = (const uint32_t[]){LCOUNT}, + }, { + .name = "xsr.lend", + .translate = translate_xsr, + .par = (const uint32_t[]){LEND}, + }, { + .name = "xsr.litbase", + .translate = translate_xsr, + .par = (const uint32_t[]){LITBASE}, + }, { + .name = "xsr.m0", + .translate = translate_xsr, + .par = (const uint32_t[]){MR}, + }, { + .name = "xsr.m1", + .translate = translate_xsr, + .par = (const uint32_t[]){MR + 1}, + }, { + .name = "xsr.m2", + .translate = translate_xsr, + .par = (const uint32_t[]){MR + 2}, + }, { + .name = "xsr.m3", + .translate = translate_xsr, + .par = (const uint32_t[]){MR + 3}, + }, { + .name = "xsr.memctl", + .translate = translate_xsr, + .par = (const uint32_t[]){MEMCTL}, + }, { + .name = "xsr.misc0", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC}, + }, { + .name = "xsr.misc1", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC + 1}, + }, { + .name = "xsr.misc2", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC + 2}, + }, { + .name = "xsr.misc3", + .translate = translate_xsr, + .par = (const uint32_t[]){MISC + 3}, + }, { + .name = "xsr.prid", + .translate = translate_xsr, + .par = (const uint32_t[]){PRID}, + }, { + .name = "xsr.ps", + .translate = translate_xsr, + .par = (const uint32_t[]){PS}, + }, { + .name = "xsr.ptevaddr", + .translate = translate_xsr, + .par = (const uint32_t[]){PTEVADDR}, + }, { + .name = "xsr.rasid", + .translate = translate_xsr, + .par = (const uint32_t[]){RASID}, + }, { + .name = "xsr.sar", + .translate = translate_xsr, + .par = (const uint32_t[]){SAR}, + }, { + .name = "xsr.scompare1", + .translate = translate_xsr, + .par = (const uint32_t[]){SCOMPARE1}, + }, { + .name = "xsr.vecbase", + .translate = translate_xsr, + .par = (const uint32_t[]){VECBASE}, + }, { + .name = "xsr.windowbase", + .translate = translate_xsr, + .par = (const uint32_t[]){WINDOW_BASE}, + }, { + .name = "xsr.windowstart", + .translate = translate_xsr, + .par = (const uint32_t[]){WINDOW_START}, + }, +}; + +const XtensaOpcodeTranslators xtensa_core_opcodes = { + .num_opcodes = ARRAY_SIZE(core_ops), + .opcode = core_ops, +}; + + +static void translate_abs_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_add_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_add_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +enum { + COMPARE_UN, + COMPARE_OEQ, + COMPARE_UEQ, + COMPARE_OLT, + COMPARE_ULT, + COMPARE_OLE, + COMPARE_ULE, +}; + +static void translate_compare_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_env env, TCGv_i32 bit, + TCGv_i32 s, TCGv_i32 t) = { + [COMPARE_UN] = gen_helper_un_s, + [COMPARE_OEQ] = gen_helper_oeq_s, + [COMPARE_UEQ] = gen_helper_ueq_s, + [COMPARE_OLT] = gen_helper_olt_s, + [COMPARE_ULT] = gen_helper_ult_s, + [COMPARE_OLE] = gen_helper_ole_s, + [COMPARE_ULE] = gen_helper_ule_s, + }; + + if (gen_check_cpenable(dc, 0)) { + TCGv_i32 bit = tcg_const_i32(1 << arg[0]); + + helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(bit); + } +} + +static void translate_float_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 scale = tcg_const_i32(-arg[2]); + + if (par[0]) { + gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + } else { + gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + } + tcg_temp_free(scale); + } +} + +static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 rounding_mode = tcg_const_i32(par[0]); + TCGv_i32 scale = tcg_const_i32(arg[2]); + + if (par[1]) { + gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } else { + gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], + rounding_mode, scale); + } + tcg_temp_free(rounding_mode); + tcg_temp_free(scale); + } +} + +static void translate_ldsti(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); + } +} + +static void translate_ldstx(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[1], arg[2]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 addr = tcg_temp_new_i32(); + + tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + } else { + tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + } + if (par[1]) { + tcg_gen_mov_i32(cpu_R[arg[1]], addr); + } + tcg_temp_free(addr); + } +} + +static void translate_madd_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_mov_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[2]) && gen_check_cpenable(dc, 0)) { + TCGv_i32 zero = tcg_const_i32(0); + + tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], + cpu_R[arg[2]], zero, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + tcg_temp_free(zero); + } +} + +static void translate_movp_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_movcond_i32(par[0], + cpu_FR[arg[0]], tmp, zero, + cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } +} + +static void translate_mul_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_msub_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_neg_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0]) && + gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); + } +} + +static void translate_sub_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_check_cpenable(dc, 0)) { + gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, + cpu_FR[arg[1]], cpu_FR[arg[2]]); + } +} + +static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[1]) && + gen_check_cpenable(dc, 0)) { + tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); + } +} + +static const XtensaOpcodeOps fpu2000_ops[] = { + { + .name = "abs.s", + .translate = translate_abs_s, + }, { + .name = "add.s", + .translate = translate_add_s, + }, { + .name = "ceil.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_up, false}, + }, { + .name = "float.s", + .translate = translate_float_s, + .par = (const uint32_t[]){false}, + }, { + .name = "floor.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_down, false}, + }, { + .name = "lsi", + .translate = translate_ldsti, + .par = (const uint32_t[]){false, false}, + }, { + .name = "lsiu", + .translate = translate_ldsti, + .par = (const uint32_t[]){false, true}, + }, { + .name = "lsx", + .translate = translate_ldstx, + .par = (const uint32_t[]){false, false}, + }, { + .name = "lsxu", + .translate = translate_ldstx, + .par = (const uint32_t[]){false, true}, + }, { + .name = "madd.s", + .translate = translate_madd_s, + }, { + .name = "mov.s", + .translate = translate_mov_s, + }, { + .name = "moveqz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movf.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + }, { + .name = "movgez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_GE}, + }, { + .name = "movltz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "movnez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "movt.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_NE}, + }, { + .name = "msub.s", + .translate = translate_msub_s, + }, { + .name = "mul.s", + .translate = translate_mul_s, + }, { + .name = "neg.s", + .translate = translate_neg_s, + }, { + .name = "oeq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OEQ}, + }, { + .name = "ole.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLE}, + }, { + .name = "olt.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLT}, + }, { + .name = "rfr.s", + .translate = translate_rfr_s, + }, { + .name = "round.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_nearest_even, false}, + }, { + .name = "ssi", + .translate = translate_ldsti, + .par = (const uint32_t[]){true, false}, + }, { + .name = "ssiu", + .translate = translate_ldsti, + .par = (const uint32_t[]){true, true}, + }, { + .name = "ssx", + .translate = translate_ldstx, + .par = (const uint32_t[]){true, false}, + }, { + .name = "ssxu", + .translate = translate_ldstx, + .par = (const uint32_t[]){true, true}, + }, { + .name = "sub.s", + .translate = translate_sub_s, + }, { + .name = "trunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, false}, + }, { + .name = "ueq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UEQ}, + }, { + .name = "ufloat.s", + .translate = translate_float_s, + .par = (const uint32_t[]){true}, + }, { + .name = "ule.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULE}, + }, { + .name = "ult.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULT}, + }, { + .name = "un.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UN}, + }, { + .name = "utrunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, true}, + }, { + .name = "wfr.s", + .translate = translate_wfr_s, + }, +}; + +const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = { + .num_opcodes = ARRAY_SIZE(fpu2000_ops), + .opcode = fpu2000_ops, +}; |