diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/openrisc/cpu.c | 16 | ||||
| -rw-r--r-- | target/openrisc/cpu.h | 46 | ||||
| -rw-r--r-- | target/openrisc/gdbstub.c | 4 | ||||
| -rw-r--r-- | target/openrisc/interrupt.c | 11 | ||||
| -rw-r--r-- | target/openrisc/machine.c | 76 | ||||
| -rw-r--r-- | target/openrisc/mmu.c | 24 | ||||
| -rw-r--r-- | target/openrisc/sys_helper.c | 35 | ||||
| -rw-r--r-- | target/openrisc/translate.c | 5 |
8 files changed, 179 insertions, 38 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7fd2b9a216..1d6330cbcc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,8 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr = -1; s->exception_index = -1; - cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; - cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); @@ -65,12 +65,6 @@ static void openrisc_cpu_reset(CPUState *s) #endif } -static inline void set_feature(OpenRISCCPU *cpu, int feature) -{ - cpu->feature |= feature; - cpu->env.cpucfgr = cpu->feature; -} - static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -132,15 +126,15 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); - set_feature(cpu, OPENRISC_FEATURE_OB32S); - set_feature(cpu, OPENRISC_FEATURE_OF32S); + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | + CPUCFGR_EVBARP; } static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); - set_feature(cpu, OPENRISC_FEATURE_OB32S); + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; } typedef struct OpenRISCCPUInfo { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 418a0e6960..2721432c4f 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -111,6 +111,11 @@ enum { CPUCFGR_OF32S = (1 << 7), CPUCFGR_OF64S = (1 << 8), CPUCFGR_OV64S = (1 << 9), + /* CPUCFGR_ND = (1 << 10), */ + /* CPUCFGR_AVRP = (1 << 11), */ + CPUCFGR_EVBARP = (1 << 12), + /* CPUCFGR_ISRP = (1 << 13), */ + /* CPUCFGR_AECSRP = (1 << 14), */ }; /* DMMU configure register */ @@ -135,6 +140,15 @@ enum { IMMUCFGR_HTR = (1 << 11), }; +/* Power management register */ +enum { + PMR_SDF = (15 << 0), + PMR_DME = (1 << 4), + PMR_SME = (1 << 5), + PMR_DCGE = (1 << 6), + PMR_SUME = (1 << 7), +}; + /* Float point control status register */ enum { FPCSR_FPEE = 1, @@ -191,17 +205,6 @@ enum { SR_SCE = (1 << 17), }; -/* OpenRISC Hardware Capabilities */ -enum { - OPENRISC_FEATURE_NSGF = (15 << 0), - OPENRISC_FEATURE_CGF = (1 << 4), - OPENRISC_FEATURE_OB32S = (1 << 5), - OPENRISC_FEATURE_OB64S = (1 << 6), - OPENRISC_FEATURE_OF32S = (1 << 7), - OPENRISC_FEATURE_OF64S = (1 << 8), - OPENRISC_FEATURE_OV64S = (1 << 9), -}; - /* Tick Timer Mode Register */ enum { TTMR_TP = (0xfffffff), @@ -269,7 +272,8 @@ typedef struct CPUOpenRISCTLBContext { #endif typedef struct CPUOpenRISCState { - target_ulong gpr[32]; /* General registers */ + target_ulong shadow_gpr[16][32]; /* Shadow registers */ + target_ulong pc; /* Program counter */ target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ @@ -285,10 +289,11 @@ typedef struct CPUOpenRISCState { uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ - uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ + uint32_t evbar; /* Exception vector base address register */ + uint32_t pmr; /* Power Management Register */ uint32_t fpcsr; /* Float register */ float_status fp_status; @@ -303,6 +308,8 @@ typedef struct CPUOpenRISCState { CPU_COMMON /* Fields from here on are preserved across CPU reset. */ + uint32_t cpucfgr; /* CPU configure register */ + #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; @@ -329,7 +336,6 @@ typedef struct OpenRISCCPU { CPUOpenRISCState env; - uint32_t feature; /* CPU Capabilities */ } OpenRISCCPU; static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) @@ -392,6 +398,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, #define TB_FLAGS_R0_0 2 #define TB_FLAGS_OVE SR_OVE +static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) +{ + return env->shadow_gpr[0][i]; +} + +static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) +{ + env->shadow_gpr[0][i] = val; +} + static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -399,7 +415,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, *pc = env->pc; *cs_base = 0; *flags = (env->dflag - | (env->gpr[0] == 0 ? TB_FLAGS_R0_0 : 0) + | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0) | (env->sr & SR_OVE)); } diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index b18c7e9f05..f9af6507f3 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -28,7 +28,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) CPUOpenRISCState *env = &cpu->env; if (n < 32) { - return gdb_get_reg32(mem_buf, env->gpr[n]); + return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); } else { switch (n) { case 32: /* PPC */ @@ -61,7 +61,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); if (n < 32) { - env->gpr[n] = tmp; + cpu_set_gpr(env, n, tmp); } else { switch (n) { case 32: /* PPC */ diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index a2eec6fb32..3959671c59 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -60,12 +60,21 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_SM; env->sr &= ~SR_IEE; env->sr &= ~SR_TEE; + env->pmr &= ~PMR_DME; + env->pmr &= ~PMR_SME; env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - env->pc = (cs->exception_index << 8); + hwaddr vect_pc = cs->exception_index << 8; + if (env->cpucfgr & CPUCFGR_EVBARP) { + vect_pc |= env->evbar; + } + if (env->sr & SR_EPH) { + vect_pc |= 0xf0000000; + } + env->pc = vect_pc; } else { cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 686eaa30c9..a20cce705d 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,6 +24,63 @@ #include "hw/boards.h" #include "migration/cpu.h" +static int env_post_load(void *opaque, int version_id) +{ + CPUOpenRISCState *env = opaque; + + /* Restore MMU handlers */ + if (env->sr & SR_DME) { + env->tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_data; + } else { + env->tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_nommu; + } + + if (env->sr & SR_IME) { + env->tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_code; + } else { + env->tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_nommu; + } + + + return 0; +} + +static const VMStateDescription vmstate_tlb_entry = { + .name = "tlb_entry", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(mr, OpenRISCTLBEntry), + VMSTATE_UINTTL(tr, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_cpu_tlb = { + .name = "cpu_tlb", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, + ITLB_WAYS, ITLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, + DTLB_WAYS, DTLB_SIZE, 0, + vmstate_tlb_entry, OpenRISCTLBEntry), + VMSTATE_END_OF_LIST() + } +}; + +#define VMSTATE_CPU_TLB(_f, _s) \ + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) + + static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { CPUOpenRISCState *env = opaque; @@ -47,10 +104,11 @@ static const VMStateInfo vmstate_sr = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 4, - .minimum_version_id = 4, + .version_id = 6, + .minimum_version_id = 6, + .post_load = env_post_load, .fields = (VMStateField[]) { - VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32), + VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), VMSTATE_UINTTL(ppc, CPUOpenRISCState), VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState), @@ -79,9 +137,21 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), VMSTATE_UINT32(immucfgr, CPUOpenRISCState), + VMSTATE_UINT32(evbar, CPUOpenRISCState), + VMSTATE_UINT32(pmr, CPUOpenRISCState), VMSTATE_UINT32(esr, CPUOpenRISCState), VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), + + VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + + VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), + VMSTATE_UINT32(ttmr, CPUOpenRISCState), + VMSTATE_UINT32(ttcr, CPUOpenRISCState), + + VMSTATE_UINT32(picmr, CPUOpenRISCState), + VMSTATE_UINT32(picsr, CPUOpenRISCState), + VMSTATE_END_OF_LIST() } }; diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 56b11d3d68..ce2a29dd1a 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, { int ret = TLBRET_MATCH; - if (rw == 2) { /* ITLB */ + if (rw == MMU_INST_FETCH) { /* ITLB */ *physical = 0; ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, prot, address, rw); @@ -221,12 +221,28 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) OpenRISCCPU *cpu = OPENRISC_CPU(cs); hwaddr phys_addr; int prot; + int miss; - if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) { - return -1; + /* Check memory for any kind of address, since during debug the + gdb can ask for anything, check data tlb for address */ + miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + + /* Check instruction tlb */ + if (miss) { + miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, + MMU_INST_FETCH); + } + + /* Last, fall back to a plain address */ + if (miss) { + miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0); } - return phys_addr; + if (miss) { + return -1; + } else { + return phys_addr; + } } void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 60c3193656..abdef5d6a5 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exception.h" #define TO_SPR(group, number) (((group) << 11) + (number)) @@ -39,6 +40,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, env->vr = rb; break; + case TO_SPR(0, 11): /* EVBAR */ + env->evbar = rb; + break; + case TO_SPR(0, 16): /* NPC */ cpu_restore_state(cs, GETPC()); /* ??? Mirror or1ksim in not trashing delayed branch state @@ -88,6 +93,11 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ env->esr = rb; break; + + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx = (spr - 1024); + env->shadow_gpr[idx / 32][idx % 32] = rb; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { @@ -132,6 +142,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(5, 2): /* MACHI */ env->mac = deposit64(env->mac, 32, 32, rb); break; + case TO_SPR(8, 0): /* PMR */ + env->pmr = rb; + if (env->pmr & PMR_DME || env->pmr & PMR_SME) { + cpu_restore_state(cs, GETPC()); + env->pc += 4; + cs->halted = 1; + raise_exception(cpu, EXCP_HALTED); + } + break; case TO_SPR(9, 0): /* PICMR */ env->picmr |= rb; break; @@ -206,6 +225,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; + case TO_SPR(0, 11): /* EVBAR */ + return env->evbar; + case TO_SPR(0, 16): /* NPC (equals PC) */ cpu_restore_state(cs, GETPC()); return env->pc; @@ -226,6 +248,16 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + + case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ + idx = (spr - 1024); + return env->shadow_gpr[idx / 32][idx % 32]; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr; @@ -265,6 +297,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->mac >> 32; break; + case TO_SPR(8, 0): /* PMR */ + return env->pmr; + case TO_SPR(9, 0): /* PICMR */ return env->picmr; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c4cbf205f..e49518e893 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -107,7 +107,8 @@ void openrisc_translate_init(void) "mac"); for (i = 0; i < 32; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, - offsetof(CPUOpenRISCState, gpr[i]), + offsetof(CPUOpenRISCState, + shadow_gpr[0][i]), regnames[i]); } cpu_R0 = cpu_R[0]; @@ -1662,7 +1663,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, "PC=%08x\n", env->pc); for (i = 0; i < 32; ++i) { - cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i], + cpu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), (i % 4) == 3 ? '\n' : ' '); } } |