diff options
Diffstat (limited to 'target')
52 files changed, 534 insertions, 237 deletions
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b3fd6643e8..27192b62e2 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,20 @@ static void alpha_cpu_initfn(Object *obj) #endif } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps alpha_tcg_ops = { + .initialize = alpha_translate_init, + .cpu_exec_interrupt = alpha_cpu_exec_interrupt, + .tlb_fill = alpha_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = alpha_cpu_do_interrupt, + .do_transaction_failed = alpha_cpu_do_transaction_failed, + .do_unaligned_access = alpha_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void alpha_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -217,22 +231,17 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; - cc->do_interrupt = alpha_cpu_do_interrupt; - cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; cc->gdb_write_register = alpha_cpu_gdb_write_register; - cc->tlb_fill = alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = alpha_cpu_do_transaction_failed; - cc->do_unaligned_access = alpha_cpu_do_unaligned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; dc->vmsd = &vmstate_alpha_cpu; #endif cc->disas_set_info = alpha_cpu_disas_set_info; - cc->tcg_initialize = alpha_translate_init; + cc->tcg_ops = &alpha_tcg_ops; cc->gdb_num_core_regs = 67; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40142ac141..8ddb2556f8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -26,6 +26,9 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "internals.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" @@ -54,8 +57,9 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } -static void arm_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) +#ifdef CONFIG_TCG +void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -70,6 +74,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs, env->regs[15] = tb->pc; } } +#endif /* CONFIG_TCG */ static bool arm_cpu_has_work(CPUState *cs) { @@ -588,7 +593,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) found: cs->exception_index = excp_idx; env->exception.target_el = target_el; - cc->do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); return true; } @@ -2240,6 +2245,24 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } +#ifdef CONFIG_TCG +static struct TCGCPUOps arm_tcg_ops = { + .initialize = arm_translate_init, + .synchronize_from_tb = arm_cpu_synchronize_from_tb, + .cpu_exec_interrupt = arm_cpu_exec_interrupt, + .tlb_fill = arm_cpu_tlb_fill, + .debug_excp_handler = arm_debug_excp_handler, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt = arm_cpu_do_interrupt, + .do_transaction_failed = arm_cpu_do_transaction_failed, + .do_unaligned_access = arm_cpu_do_unaligned_access, + .adjust_watchpoint_address = arm_adjust_watchpoint_address, + .debug_check_watchpoint = arm_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc = ARM_CPU_CLASS(oc); @@ -2254,14 +2277,11 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work; - cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; - cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; cc->gdb_read_register = arm_cpu_gdb_read_register; cc->gdb_write_register = arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_interrupt = arm_cpu_do_interrupt; cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs = arm_asidx_from_attrs; cc->vmsd = &vmstate_arm_cpu; @@ -2275,17 +2295,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = arm_disas_set_info; + #ifdef CONFIG_TCG - cc->tcg_initialize = arm_translate_init; - cc->tlb_fill = arm_cpu_tlb_fill; - cc->debug_excp_handler = arm_debug_excp_handler; - cc->debug_check_watchpoint = arm_debug_check_watchpoint; - cc->do_unaligned_access = arm_cpu_do_unaligned_access; -#if !defined(CONFIG_USER_ONLY) - cc->do_transaction_failed = arm_cpu_do_transaction_failed; - cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ -#endif + cc->tcg_ops = &arm_tcg_ops; +#endif /* CONFIG_TCG */ } #ifdef CONFIG_KVM diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5e851028c5..10c5118176 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -805,7 +808,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); - cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 98544db2df..c29b434c60 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -10,11 +10,15 @@ #include "qemu/osdep.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "internals.h" /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifdef CONFIG_TCG static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -33,11 +37,12 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index = EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); ret = true; } return ret; } +#endif /* CONFIG_TCG */ static void arm926_initfn(Object *obj) { @@ -658,17 +663,34 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } +#ifdef CONFIG_TCG +static struct TCGCPUOps arm_v7m_tcg_ops = { + .initialize = arm_translate_init, + .synchronize_from_tb = arm_cpu_synchronize_from_tb, + .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, + .tlb_fill = arm_cpu_tlb_fill, + .debug_excp_handler = arm_debug_excp_handler, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt = arm_v7m_cpu_do_interrupt, + .do_transaction_failed = arm_cpu_do_transaction_failed, + .do_unaligned_access = arm_cpu_do_unaligned_access, + .adjust_watchpoint_address = arm_adjust_watchpoint_address, + .debug_check_watchpoint = arm_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void arm_v7m_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc = ARM_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); acc->info = data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt = arm_v7m_cpu_do_interrupt; -#endif +#ifdef CONFIG_TCG + cc->tcg_ops = &arm_v7m_tcg_ops; +#endif /* CONFIG_TCG */ - cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; cc->gdb_core_xml_file = "arm-m-profile.xml"; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 47e266d7e6..1a64bd748c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9969,6 +9969,10 @@ static void handle_semihosting(CPUState *cs) * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. + * + * Note: this is used for both TCG (as the do_interrupt tcg op), + * and KVM to re-inject guest debug exceptions, and to + * inject a Synchronous-External-Abort. */ void arm_cpu_do_interrupt(CPUState *cs) { diff --git a/target/arm/internals.h b/target/arm/internals.h index 853fa88fd6..448982dd2f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -171,6 +171,12 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); +#ifdef CONFIG_TCG +void arm_cpu_synchronize_from_tb(CPUState *cs, + const struct TranslationBlock *tb); +#endif /* CONFIG_TCG */ + + enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3c37fc4fb6..dff85f6db9 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -946,7 +946,6 @@ static void kvm_inject_arm_sea(CPUState *c) { ARMCPU *cpu = ARM_CPU(c); CPUARMState *env = &cpu->env; - CPUClass *cc = CPU_GET_CLASS(c); uint32_t esr; bool same_el; @@ -962,7 +961,7 @@ static void kvm_inject_arm_sea(CPUState *c) env->exception.syndrome = esr; - cc->do_interrupt(c); + arm_cpu_do_interrupt(c); } #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ @@ -1493,7 +1492,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) { int hsr_ec = syn_get_ec(debug_exit->hsr); ARMCPU *cpu = ARM_CPU(cs); - CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = &cpu->env; /* Ensure PC is synchronised */ @@ -1547,7 +1545,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) env->exception.vaddress = debug_exit->far; env->exception.target_el = 1; qemu_mutex_lock_iothread(); - cc->do_interrupt(cs); + arm_cpu_do_interrupt(cs); qemu_mutex_unlock_iothread(); return false; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 6f3d5a9e4a..fa0f8e0e80 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,19 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps avr_tcg_ops = { + .initialize = avr_cpu_tcg_init, + .synchronize_from_tb = avr_cpu_synchronize_from_tb, + .cpu_exec_interrupt = avr_cpu_exec_interrupt, + .tlb_fill = avr_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = avr_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void avr_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -198,21 +211,17 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = avr_cpu_class_by_name; cc->has_work = avr_cpu_has_work; - cc->do_interrupt = avr_cpu_do_interrupt; - cc->cpu_exec_interrupt = avr_cpu_exec_interrupt; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; cc->memory_rw_debug = avr_cpu_memory_rw_debug; cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; - cc->tlb_fill = avr_cpu_tlb_fill; cc->vmsd = &vms_avr_cpu; cc->disas_set_info = avr_cpu_disas_set_info; - cc->tcg_initialize = avr_cpu_tcg_init; - cc->synchronize_from_tb = avr_cpu_synchronize_from_tb; cc->gdb_read_register = avr_cpu_gdb_read_register; cc->gdb_write_register = avr_cpu_gdb_write_register; cc->gdb_num_core_regs = 35; cc->gdb_core_xml_file = "avr-cpu.xml"; + cc->tcg_ops = &avr_tcg_ops; } /* diff --git a/target/avr/helper.c b/target/avr/helper.c index d96d14372b..65880b9928 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" @@ -34,7 +35,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_RESET) { if (cpu_interrupts_enabled(env)) { cs->exception_index = EXCP_RESET; - cc->do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); cs->interrupt_request &= ~CPU_INTERRUPT_RESET; @@ -45,7 +46,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (cpu_interrupts_enabled(env) && env->intsrc != 0) { int index = ctz32(env->intsrc); cs->exception_index = EXCP_INT(index); - cc->do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); env->intsrc &= env->intsrc - 1; /* clear the interrupt */ cs->interrupt_request &= ~CPU_INTERRUPT_HARD; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index cff6b9eabf..ed983380fc 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,15 +193,36 @@ static void cris_cpu_initfn(Object *obj) #endif } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps crisv10_tcg_ops = { + .initialize = cris_initialize_crisv10_tcg, + .cpu_exec_interrupt = cris_cpu_exec_interrupt, + .tlb_fill = cris_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = crisv10_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + +static struct TCGCPUOps crisv32_tcg_ops = { + .initialize = cris_initialize_tcg, + .cpu_exec_interrupt = cris_cpu_exec_interrupt, + .tlb_fill = cris_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = cris_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void crisv8_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); ccc->vr = 8; - cc->do_interrupt = crisv10_cpu_do_interrupt; cc->gdb_read_register = crisv10_cpu_gdb_read_register; - cc->tcg_initialize = cris_initialize_crisv10_tcg; + cc->tcg_ops = &crisv10_tcg_ops; } static void crisv9_cpu_class_init(ObjectClass *oc, void *data) @@ -210,9 +231,8 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data) CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); ccc->vr = 9; - cc->do_interrupt = crisv10_cpu_do_interrupt; cc->gdb_read_register = crisv10_cpu_gdb_read_register; - cc->tcg_initialize = cris_initialize_crisv10_tcg; + cc->tcg_ops = &crisv10_tcg_ops; } static void crisv10_cpu_class_init(ObjectClass *oc, void *data) @@ -221,9 +241,8 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data) CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); ccc->vr = 10; - cc->do_interrupt = crisv10_cpu_do_interrupt; cc->gdb_read_register = crisv10_cpu_gdb_read_register; - cc->tcg_initialize = cris_initialize_crisv10_tcg; + cc->tcg_ops = &crisv10_tcg_ops; } static void crisv11_cpu_class_init(ObjectClass *oc, void *data) @@ -232,9 +251,8 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); ccc->vr = 11; - cc->do_interrupt = crisv10_cpu_do_interrupt; cc->gdb_read_register = crisv10_cpu_gdb_read_register; - cc->tcg_initialize = cris_initialize_crisv10_tcg; + cc->tcg_ops = &crisv10_tcg_ops; } static void crisv17_cpu_class_init(ObjectClass *oc, void *data) @@ -243,16 +261,17 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data) CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); ccc->vr = 17; - cc->do_interrupt = crisv10_cpu_do_interrupt; cc->gdb_read_register = crisv10_cpu_gdb_read_register; - cc->tcg_initialize = cris_initialize_crisv10_tcg; + cc->tcg_ops = &crisv10_tcg_ops; } static void crisv32_cpu_class_init(ObjectClass *oc, void *data) { + CPUClass *cc = CPU_CLASS(oc); CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); ccc->vr = 32; + cc->tcg_ops = &crisv32_tcg_ops; } static void cris_cpu_class_init(ObjectClass *oc, void *data) @@ -268,13 +287,10 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work; - cc->do_interrupt = cris_cpu_do_interrupt; - cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; cc->gdb_write_register = cris_cpu_gdb_write_register; - cc->tlb_fill = cris_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; dc->vmsd = &vmstate_cris_cpu; @@ -284,7 +300,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = cris_disas_set_info; - cc->tcg_initialize = cris_initialize_tcg; } #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/cris/helper.c b/target/cris/helper.c index ed45c3d9b7..7e3bb58fe1 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" #include "mmu.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" @@ -299,7 +300,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { cs->exception_index = EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); ret = true; } if (interrupt_request & CPU_INTERRUPT_NMI) { @@ -311,7 +312,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } if ((env->pregs[PR_CCS] & m_flag_archval)) { cs->exception_index = EXCP_NMI; - cc->do_interrupt(cs); + cc->tcg_ops->do_interrupt(cs); ret = true; } } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e28f047d10..d8fad52d1f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -71,6 +71,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) info->print_insn = print_insn_hppa; } +#ifndef CONFIG_USER_ONLY static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -87,6 +88,7 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_loop_exit_restore(cs, retaddr); } +#endif /* CONFIG_USER_ONLY */ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { @@ -129,6 +131,20 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps hppa_tcg_ops = { + .initialize = hppa_translate_init, + .synchronize_from_tb = hppa_cpu_synchronize_from_tb, + .cpu_exec_interrupt = hppa_cpu_exec_interrupt, + .tlb_fill = hppa_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = hppa_cpu_do_interrupt, + .do_unaligned_access = hppa_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void hppa_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -140,23 +156,17 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = hppa_cpu_class_by_name; cc->has_work = hppa_cpu_has_work; - cc->do_interrupt = hppa_cpu_do_interrupt; - cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt; cc->dump_state = hppa_cpu_dump_state; cc->set_pc = hppa_cpu_set_pc; - cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; cc->gdb_read_register = hppa_cpu_gdb_read_register; cc->gdb_write_register = hppa_cpu_gdb_write_register; - cc->tlb_fill = hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; dc->vmsd = &vmstate_hppa_cpu; #endif - cc->do_unaligned_access = hppa_cpu_do_unaligned_access; cc->disas_set_info = hppa_cpu_disas_set_info; - cc->tcg_initialize = hppa_translate_init; - cc->gdb_num_core_regs = 128; + cc->tcg_ops = &hppa_tcg_ops; } static const TypeInfo hppa_cpu_type_info = { diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-accel-ops.c index f72c85bd49..136630e9b2 100644 --- a/target/i386/hax/hax-cpus.c +++ b/target/i386/hax/hax-accel-ops.c @@ -26,7 +26,7 @@ #include "sysemu/cpus.h" #include "qemu/guest-random.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" static void *hax_cpu_thread_fn(void *arg) { @@ -74,12 +74,29 @@ static void hax_start_vcpu_thread(CPUState *cpu) #endif } -const CpusAccel hax_cpus = { - .create_vcpu_thread = hax_start_vcpu_thread, - .kick_vcpu_thread = hax_kick_vcpu_thread, +static void hax_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread = hax_start_vcpu_thread; + ops->kick_vcpu_thread = hax_kick_vcpu_thread; + + ops->synchronize_post_reset = hax_cpu_synchronize_post_reset; + ops->synchronize_post_init = hax_cpu_synchronize_post_init; + ops->synchronize_state = hax_cpu_synchronize_state; + ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm; +} - .synchronize_post_reset = hax_cpu_synchronize_post_reset, - .synchronize_post_init = hax_cpu_synchronize_post_init, - .synchronize_state = hax_cpu_synchronize_state, - .synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm, +static const TypeInfo hax_accel_ops_type = { + .name = ACCEL_OPS_NAME("hax"), + + .parent = TYPE_ACCEL_OPS, + .class_init = hax_accel_ops_class_init, + .abstract = true, }; + +static void hax_accel_ops_register_types(void) +{ + type_register_static(&hax_accel_ops_type); +} +type_init(hax_accel_ops_register_types); diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-accel-ops.h index ee8ab7a631..c7698519cd 100644 --- a/target/i386/hax/hax-cpus.h +++ b/target/i386/hax/hax-accel-ops.h @@ -12,8 +12,6 @@ #include "sysemu/cpus.h" -extern const CpusAccel hax_cpus; - #include "hax-interface.h" #include "hax-i386.h" diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index fecfe8cd6e..bf65ed6fa9 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -28,12 +28,12 @@ #include "exec/address-spaces.h" #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "hw/boards.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" #define DEBUG_HAX 0 @@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms) !ret ? "working" : "not working", !ret ? "fast virt" : "emulation"); } - if (ret == 0) { - cpus_register_accel(&hax_cpus); - } return ret; } diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c index 71e637cf16..35495f5e82 100644 --- a/target/i386/hax/hax-mem.c +++ b/target/i386/hax/hax-mem.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" #include "qemu/queue.h" #define DEBUG_HAX_MEM 0 diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c index 735a749d4b..ac1a51096e 100644 --- a/target/i386/hax/hax-posix.c +++ b/target/i386/hax/hax-posix.c @@ -15,7 +15,7 @@ #include <sys/ioctl.h> #include "sysemu/cpus.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" hax_fd hax_mod_open(void) { diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 6c82dfb54f..59afa213a6 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" /* * return 0 when success, -1 when driver not loaded, diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h index a5ce12d663..b1f5d4f32f 100644 --- a/target/i386/hax/hax-windows.h +++ b/target/i386/hax/hax-windows.h @@ -23,7 +23,7 @@ #include <winioctl.h> #include <windef.h> -#include "hax-cpus.h" +#include "hax-accel-ops.h" #define HAX_INVALID_FD INVALID_HANDLE_VALUE diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build index 77ea431b30..d6c520fb6b 100644 --- a/target/i386/hax/meson.build +++ b/target/i386/hax/meson.build @@ -1,7 +1,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', - 'hax-cpus.c', + 'hax-accel-ops.c', )) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c')) diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-accel-ops.c index 817b3d7452..cbaad238e0 100644 --- a/target/i386/hvf/hvf-cpus.c +++ b/target/i386/hvf/hvf-accel-ops.c @@ -55,7 +55,7 @@ #include "target/i386/cpu.h" #include "qemu/guest-random.h" -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" /* * The HVF-specific vCPU thread function. This one should only run when the host @@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } -const CpusAccel hvf_cpus = { - .create_vcpu_thread = hvf_start_vcpu_thread, +static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread = hvf_start_vcpu_thread; + + ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset; + ops->synchronize_post_init = hvf_cpu_synchronize_post_init; + ops->synchronize_state = hvf_cpu_synchronize_state; + ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hvf_accel_ops_type = { + .name = ACCEL_OPS_NAME("hvf"), - .synchronize_post_reset = hvf_cpu_synchronize_post_reset, - .synchronize_post_init = hvf_cpu_synchronize_post_init, - .synchronize_state = hvf_cpu_synchronize_state, - .synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm, + .parent = TYPE_ACCEL_OPS, + .class_init = hvf_accel_ops_class_init, + .abstract = true, }; +static void hvf_accel_ops_register_types(void) +{ + type_register_static(&hvf_accel_ops_type); +} +type_init(hvf_accel_ops_register_types); diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-accel-ops.h index ced31b82c0..8f992da168 100644 --- a/target/i386/hvf/hvf-cpus.h +++ b/target/i386/hvf/hvf-accel-ops.h @@ -12,8 +12,6 @@ #include "sysemu/cpus.h" -extern const CpusAccel hvf_cpus; - int hvf_init_vcpu(CPUState *); int hvf_vcpu_exec(CPUState *); void hvf_cpu_synchronize_state(CPUState *); diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index e0edffd077..50b914fd67 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -16,7 +16,7 @@ #ifndef HVF_I386_H #define HVF_I386_H -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/hvf.h" #include "cpu.h" #include "x86.h" diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ed9356565c..5b90dcdf88 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -69,10 +69,10 @@ #include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" HVFState *hvf_state; @@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms) hvf_state = s; memory_listener_register(&hvf_memory_listener, &address_space_memory); - cpus_register_accel(&hvf_cpus); return 0; } diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index 409c9a3f14..e9eb5a5da8 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -1,6 +1,6 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( 'hvf.c', - 'hvf-cpus.c', + 'hvf-accel-ops.c', 'x86.c', 'x86_cpuid.c', 'x86_decode.c', diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 6f04478b3a..d66dfd7669 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -28,7 +28,7 @@ #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" // TODO: taskswitch handling diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index bbec412b6c..0d7533742e 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -32,7 +32,7 @@ #include <Hypervisor/hv.h> #include <Hypervisor/hv_vmx.h> -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 4fa013720e..1e125d2175 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -57,16 +57,22 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip = tb->pc - tb->cs_base; } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps x86_tcg_ops = { + .initialize = tcg_x86_init, + .synchronize_from_tb = x86_cpu_synchronize_from_tb, + .cpu_exec_enter = x86_cpu_exec_enter, + .cpu_exec_exit = x86_cpu_exec_exit, + .cpu_exec_interrupt = x86_cpu_exec_interrupt, + .do_interrupt = x86_cpu_do_interrupt, + .tlb_fill = x86_cpu_tlb_fill, +#ifndef CONFIG_USER_ONLY + .debug_excp_handler = breakpoint_handler, +#endif /* !CONFIG_USER_ONLY */ +}; + void tcg_cpu_common_class_init(CPUClass *cc) { - cc->do_interrupt = x86_cpu_do_interrupt; - cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; - cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; - cc->cpu_exec_enter = x86_cpu_exec_enter; - cc->cpu_exec_exit = x86_cpu_exec_exit; - cc->tcg_initialize = tcg_x86_init; - cc->tlb_fill = x86_cpu_tlb_fill; -#ifndef CONFIG_USER_ONLY - cc->debug_excp_handler = breakpoint_handler; -#endif + cc->tcg_ops = &x86_tcg_ops; } diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build index d8aa683999..95fc31eb81 100644 --- a/target/i386/whpx/meson.build +++ b/target/i386/whpx/meson.build @@ -1,5 +1,5 @@ i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-apic.c', - 'whpx-cpus.c', + 'whpx-accel-ops.c', )) diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-accel-ops.c index f7e69881a3..6bc47c5309 100644 --- a/target/i386/whpx/whpx-cpus.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -16,7 +16,7 @@ #include "sysemu/whpx.h" #include "whpx-internal.h" -#include "whpx-cpus.h" +#include "whpx-accel-ops.h" static void *whpx_cpu_thread_fn(void *arg) { @@ -83,12 +83,29 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) } } -const CpusAccel whpx_cpus = { - .create_vcpu_thread = whpx_start_vcpu_thread, - .kick_vcpu_thread = whpx_kick_vcpu_thread, +static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread = whpx_start_vcpu_thread; + ops->kick_vcpu_thread = whpx_kick_vcpu_thread; + + ops->synchronize_post_reset = whpx_cpu_synchronize_post_reset; + ops->synchronize_post_init = whpx_cpu_synchronize_post_init; + ops->synchronize_state = whpx_cpu_synchronize_state; + ops->synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm; +} - .synchronize_post_reset = whpx_cpu_synchronize_post_reset, - .synchronize_post_init = whpx_cpu_synchronize_post_init, - .synchronize_state = whpx_cpu_synchronize_state, - .synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm, +static const TypeInfo whpx_accel_ops_type = { + .name = ACCEL_OPS_NAME("whpx"), + + .parent = TYPE_ACCEL_OPS, + .class_init = whpx_accel_ops_class_init, + .abstract = true, }; + +static void whpx_accel_ops_register_types(void) +{ + type_register_static(&whpx_accel_ops_type); +} +type_init(whpx_accel_ops_register_types); diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-accel-ops.h index bdb367d1d0..2dee6d61ea 100644 --- a/target/i386/whpx/whpx-cpus.h +++ b/target/i386/whpx/whpx-accel-ops.h @@ -12,8 +12,6 @@ #include "sysemu/cpus.h" -extern const CpusAccel whpx_cpus; - int whpx_init_vcpu(CPUState *cpu); int whpx_vcpu_exec(CPUState *cpu); void whpx_destroy_vcpu(CPUState *cpu); diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 985ceba8f8..f0a35df3bb 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "exec/ioport.h" #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/whpx.h" #include "sysemu/cpus.h" #include "sysemu/runstate.h" @@ -28,8 +28,11 @@ #include "migration/blocker.h" #include <winerror.h> -#include "whpx-cpus.h" #include "whpx-internal.h" +#include "whpx-accel-ops.h" + +#include <WinHvPlatform.h> +#include <WinHvEmulation.h> #define HYPERV_APIC_BUS_FREQUENCY (200000000ULL) @@ -1846,8 +1849,6 @@ static int whpx_accel_init(MachineState *ms) whpx_memory_init(); - cpus_register_accel(&whpx_cpus); - printf("Windows Hypervisor Platform accelerator is operational\n"); return 0; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c50ad5fa15..c23d72874c 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,19 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model) return oc; } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps lm32_tcg_ops = { + .initialize = lm32_translate_init, + .cpu_exec_interrupt = lm32_cpu_exec_interrupt, + .tlb_fill = lm32_cpu_tlb_fill, + .debug_excp_handler = lm32_debug_excp_handler, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = lm32_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void lm32_cpu_class_init(ObjectClass *oc, void *data) { LM32CPUClass *lcc = LM32_CPU_CLASS(oc); @@ -222,22 +235,18 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = lm32_cpu_class_by_name; cc->has_work = lm32_cpu_has_work; - cc->do_interrupt = lm32_cpu_do_interrupt; - cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt; cc->dump_state = lm32_cpu_dump_state; cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; cc->gdb_write_register = lm32_cpu_gdb_write_register; - cc->tlb_fill = lm32_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs = 32 + 7; cc->gdb_stop_before_watchpoint = true; - cc->debug_excp_handler = lm32_debug_excp_handler; cc->disas_set_info = lm32_cpu_disas_set_info; - cc->tcg_initialize = lm32_translate_init; + cc->tcg_ops = &lm32_tcg_ops; } #define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b811a0bdde..c6fde8132b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -453,6 +453,19 @@ static const VMStateDescription vmstate_m68k_cpu = { }; #endif +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps m68k_tcg_ops = { + .initialize = m68k_tcg_init, + .cpu_exec_interrupt = m68k_cpu_exec_interrupt, + .tlb_fill = m68k_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = m68k_cpu_do_interrupt, + .do_transaction_failed = m68k_cpu_transaction_failed, +#endif /* !CONFIG_USER_ONLY */ +}; + static void m68k_cpu_class_init(ObjectClass *c, void *data) { M68kCPUClass *mcc = M68K_CPU_CLASS(c); @@ -465,22 +478,18 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = m68k_cpu_class_by_name; cc->has_work = m68k_cpu_has_work; - cc->do_interrupt = m68k_cpu_do_interrupt; - cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; cc->gdb_write_register = m68k_cpu_gdb_write_register; - cc->tlb_fill = m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) - cc->do_transaction_failed = m68k_cpu_transaction_failed; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; dc->vmsd = &vmstate_m68k_cpu; #endif cc->disas_set_info = m68k_cpu_disas_set_info; - cc->tcg_initialize = m68k_tcg_init; cc->gdb_num_core_regs = 18; + cc->tcg_ops = &m68k_tcg_ops; } static void m68k_cpu_class_init_cf_core(ObjectClass *c, void *data) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d5e8bfe11f..433ba20203 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,21 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps mb_tcg_ops = { + .initialize = mb_tcg_init, + .synchronize_from_tb = mb_cpu_synchronize_from_tb, + .cpu_exec_interrupt = mb_cpu_exec_interrupt, + .tlb_fill = mb_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = mb_cpu_do_interrupt, + .do_transaction_failed = mb_cpu_transaction_failed, + .do_unaligned_access = mb_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void mb_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -364,17 +379,13 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; - cc->do_interrupt = mb_cpu_do_interrupt; - cc->do_unaligned_access = mb_cpu_do_unaligned_access; - cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; + cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; - cc->synchronize_from_tb = mb_cpu_synchronize_from_tb; cc->gdb_read_register = mb_cpu_gdb_read_register; cc->gdb_write_register = mb_cpu_gdb_write_register; - cc->tlb_fill = mb_cpu_tlb_fill; + #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = mb_cpu_transaction_failed; cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug; dc->vmsd = &vmstate_mb_cpu; #endif @@ -382,7 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_num_core_regs = 32 + 27; cc->disas_set_info = mb_disas_set_info; - cc->tcg_initialize = mb_tcg_init; + cc->tcg_ops = &mb_tcg_ops; } static const TypeInfo mb_cpu_type_info = { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4c4548233c..ad163ead62 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -257,6 +257,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) } } +#ifdef CONFIG_TCG static void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -267,6 +268,7 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } +#endif /* CONFIG_TCG */ static bool mips_cpu_has_work(CPUState *cs) { @@ -661,6 +663,26 @@ static Property mips_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +/* + * NB: cannot be const, as some elements are changed for specific + * mips hardware (see hw/mips/jazz.c). + */ +static struct TCGCPUOps mips_tcg_ops = { + .initialize = mips_tcg_init, + .synchronize_from_tb = mips_cpu_synchronize_from_tb, + .cpu_exec_interrupt = mips_cpu_exec_interrupt, + .tlb_fill = mips_cpu_tlb_fill, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt = mips_cpu_do_interrupt, + .do_transaction_failed = mips_cpu_do_transaction_failed, + .do_unaligned_access = mips_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -674,27 +696,20 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; - cc->do_interrupt = mips_cpu_do_interrupt; - cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; - cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = mips_cpu_do_transaction_failed; - cc->do_unaligned_access = mips_cpu_do_unaligned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; cc->vmsd = &vmstate_mips_cpu; #endif cc->disas_set_info = mips_cpu_disas_set_info; -#ifdef CONFIG_TCG - cc->tcg_initialize = mips_tcg_init; - cc->tlb_fill = mips_cpu_tlb_fill; -#endif - cc->gdb_num_core_regs = 73; cc->gdb_stop_before_watchpoint = true; +#ifdef CONFIG_TCG + cc->tcg_ops = &mips_tcg_ops; +#endif /* CONFIG_TCG */ } static const TypeInfo mips_cpu_type_info = { diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 6e0443ccb7..83bec34d36 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,17 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) return oc; } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps moxie_tcg_ops = { + .initialize = moxie_translate_init, + .tlb_fill = moxie_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = moxie_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void moxie_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -107,16 +118,14 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = moxie_cpu_class_by_name; cc->has_work = moxie_cpu_has_work; - cc->do_interrupt = moxie_cpu_do_interrupt; cc->dump_state = moxie_cpu_dump_state; cc->set_pc = moxie_cpu_set_pc; - cc->tlb_fill = moxie_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug; cc->vmsd = &vmstate_moxie_cpu; #endif cc->disas_set_info = moxie_cpu_disas_set_info; - cc->tcg_initialize = moxie_translate_init; + cc->tcg_ops = &moxie_tcg_ops; } static void moxielite_initfn(Object *obj) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 58688e1623..e9c9fc3a38 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,18 @@ static Property nios2_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps nios2_tcg_ops = { + .initialize = nios2_tcg_init, + .cpu_exec_interrupt = nios2_cpu_exec_interrupt, + .tlb_fill = nios2_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = nios2_cpu_do_interrupt, + .do_unaligned_access = nios2_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; static void nios2_cpu_class_init(ObjectClass *oc, void *data) { @@ -221,20 +233,16 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = nios2_cpu_class_by_name; cc->has_work = nios2_cpu_has_work; - cc->do_interrupt = nios2_cpu_do_interrupt; - cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt; cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->disas_set_info = nios2_cpu_disas_set_info; - cc->tlb_fill = nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access = nios2_cpu_do_unaligned_access; cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug; #endif cc->gdb_read_register = nios2_cpu_gdb_read_register; cc->gdb_write_register = nios2_cpu_gdb_write_register; cc->gdb_num_core_regs = 49; - cc->tcg_initialize = nios2_tcg_init; + cc->tcg_ops = &nios2_tcg_ops; } static const TypeInfo nios2_cpu_type_info = { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b0bdfbe4fe..2c64842f46 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,18 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps openrisc_tcg_ops = { + .initialize = openrisc_translate_init, + .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, + .tlb_fill = openrisc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = openrisc_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void openrisc_cpu_class_init(ObjectClass *oc, void *data) { OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); @@ -186,20 +198,17 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; - cc->do_interrupt = openrisc_cpu_do_interrupt; - cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; cc->gdb_write_register = openrisc_cpu_gdb_write_register; - cc->tlb_fill = openrisc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; dc->vmsd = &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs = 32 + 3; - cc->tcg_initialize = openrisc_translate_init; cc->disas_set_info = openrisc_disas_set_info; + cc->tcg_ops = &openrisc_tcg_ops; } /* Sort alphabetically by type name, except for "any". */ diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 3c05a17343..9867d0a6e4 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10700,6 +10700,7 @@ static void ppc_cpu_reset(DeviceState *dev) } #ifndef CONFIG_USER_ONLY + static bool ppc_cpu_is_big_endian(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -10710,6 +10711,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs) return !msr_le; } +#ifdef CONFIG_TCG static void ppc_cpu_exec_enter(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -10731,7 +10733,9 @@ static void ppc_cpu_exec_exit(CPUState *cs) vhc->cpu_exec_exit(cpu->vhyp, cpu); } } -#endif +#endif /* CONFIG_TCG */ + +#endif /* !CONFIG_USER_ONLY */ static void ppc_cpu_instance_init(Object *obj) { @@ -10823,6 +10827,23 @@ static Property ppc_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps ppc_tcg_ops = { + .initialize = ppc_translate_init, + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, + .tlb_fill = ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = ppc_cpu_do_interrupt, + .cpu_exec_enter = ppc_cpu_exec_enter, + .cpu_exec_exit = ppc_cpu_exec_exit, + .do_unaligned_access = ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void ppc_cpu_class_init(ObjectClass *oc, void *data) { PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); @@ -10841,14 +10862,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = ppc_cpu_class_by_name; cc->has_work = ppc_cpu_has_work; - cc->do_interrupt = ppc_cpu_do_interrupt; - cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt; cc->dump_state = ppc_cpu_dump_state; cc->dump_statistics = ppc_cpu_dump_statistics; cc->set_pc = ppc_cpu_set_pc; cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_write_register = ppc_cpu_gdb_write_register; - cc->do_unaligned_access = ppc_cpu_do_unaligned_access; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_ppc_cpu; @@ -10877,18 +10895,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->virtio_is_big_endian = ppc_cpu_is_big_endian; #endif -#ifdef CONFIG_TCG - cc->tcg_initialize = ppc_translate_init; - cc->tlb_fill = ppc_cpu_tlb_fill; -#endif -#ifndef CONFIG_USER_ONLY - cc->cpu_exec_enter = ppc_cpu_exec_enter; - cc->cpu_exec_exit = ppc_cpu_exec_exit; -#endif - cc->disas_set_info = ppc_disas_set_info; dc->fw_name = "PowerPC,UNKNOWN"; + +#ifdef CONFIG_TCG + cc->tcg_ops = &ppc_tcg_ops; +#endif /* CONFIG_TCG */ } static const TypeInfo ppc_cpu_type_info = { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27788021eb..16f1a34238 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -580,6 +580,21 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return NULL; } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps riscv_tcg_ops = { + .initialize = riscv_translate_init, + .synchronize_from_tb = riscv_cpu_synchronize_from_tb, + .cpu_exec_interrupt = riscv_cpu_exec_interrupt, + .tlb_fill = riscv_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = riscv_cpu_do_interrupt, + .do_transaction_failed = riscv_cpu_do_transaction_failed, + .do_unaligned_access = riscv_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -593,11 +608,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; - cc->do_interrupt = riscv_cpu_do_interrupt; - cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; - cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; cc->gdb_read_register = riscv_cpu_gdb_read_register; cc->gdb_write_register = riscv_cpu_gdb_write_register; cc->gdb_num_core_regs = 33; @@ -609,18 +621,14 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = riscv_cpu_do_transaction_failed; - cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; -#ifdef CONFIG_TCG - cc->tcg_initialize = riscv_translate_init; - cc->tlb_fill = riscv_cpu_tlb_fill; -#endif + cc->tcg_ops = &riscv_tcg_ops; + device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f8350f5f78..2f43939fb6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -671,7 +671,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif +#endif /* !CONFIG_USER_ONLY */ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 2bb14144a7..7ac6618b26 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,19 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps rx_tcg_ops = { + .initialize = rx_translate_init, + .synchronize_from_tb = rx_cpu_synchronize_from_tb, + .cpu_exec_interrupt = rx_cpu_exec_interrupt, + .tlb_fill = rx_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = rx_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void rx_cpu_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -186,20 +199,17 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) cc->class_by_name = rx_cpu_class_by_name; cc->has_work = rx_cpu_has_work; - cc->do_interrupt = rx_cpu_do_interrupt; - cc->cpu_exec_interrupt = rx_cpu_exec_interrupt; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; - cc->synchronize_from_tb = rx_cpu_synchronize_from_tb; + cc->gdb_read_register = rx_cpu_gdb_read_register; cc->gdb_write_register = rx_cpu_gdb_write_register; cc->get_phys_page_debug = rx_cpu_get_phys_page_debug; cc->disas_set_info = rx_cpu_disas_set_info; - cc->tcg_initialize = rx_translate_init; - cc->tlb_fill = rx_cpu_tlb_fill; cc->gdb_num_core_regs = 26; cc->gdb_core_xml_file = "rx-core.xml"; + cc->tcg_ops = &rx_tcg_ops; } static const TypeInfo rx_cpu_info = { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7da70afbf2..d35eb39a1b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,22 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps s390_tcg_ops = { + .initialize = s390x_translate_init, + .tlb_fill = s390_cpu_tlb_fill, + +#if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt = s390_cpu_exec_interrupt, + .do_interrupt = s390_cpu_do_interrupt, + .debug_excp_handler = s390x_cpu_debug_excp_handler, + .do_unaligned_access = s390x_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void s390_cpu_class_init(ObjectClass *oc, void *data) { S390CPUClass *scc = S390_CPU_CLASS(oc); @@ -495,9 +511,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) scc->reset = s390_cpu_reset; cc->class_by_name = s390_cpu_class_by_name, cc->has_work = s390_cpu_has_work; -#ifdef CONFIG_TCG - cc->do_interrupt = s390_cpu_do_interrupt; -#endif cc->dump_state = s390_cpu_dump_state; cc->set_pc = s390_cpu_set_pc; cc->gdb_read_register = s390_cpu_gdb_read_register; @@ -507,23 +520,17 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->vmsd = &vmstate_s390_cpu; cc->get_crash_info = s390_cpu_get_crash_info; cc->write_elf64_note = s390_cpu_write_elf64_note; -#ifdef CONFIG_TCG - cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; - cc->debug_excp_handler = s390x_cpu_debug_excp_handler; - cc->do_unaligned_access = s390x_cpu_do_unaligned_access; -#endif #endif cc->disas_set_info = s390_cpu_disas_set_info; -#ifdef CONFIG_TCG - cc->tcg_initialize = s390x_translate_init; - cc->tlb_fill = s390_cpu_tlb_fill; -#endif - cc->gdb_num_core_regs = S390_NUM_CORE_REGS; cc->gdb_core_xml_file = "s390x-core64.xml"; cc->gdb_arch_name = s390_gdb_arch_name; s390_cpu_model_class_register_props(oc); + +#ifdef CONFIG_TCG + cc->tcg_ops = &s390_tcg_ops; +#endif /* CONFIG_TCG */ } static const TypeInfo s390_cpu_type_info = { diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 9cf66d3690..ce16af394b 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -634,4 +634,4 @@ void HELPER(monitor_call)(CPUS390XState *env, uint64_t monitor_code, } } -#endif /* CONFIG_USER_ONLY */ +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1e0f05a15b..a78d283bc8 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -206,6 +206,20 @@ static const VMStateDescription vmstate_sh_cpu = { .unmigratable = 1, }; +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps superh_tcg_ops = { + .initialize = sh4_translate_init, + .synchronize_from_tb = superh_cpu_synchronize_from_tb, + .cpu_exec_interrupt = superh_cpu_exec_interrupt, + .tlb_fill = superh_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = superh_cpu_do_interrupt, + .do_unaligned_access = superh_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void superh_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -219,24 +233,19 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = superh_cpu_class_by_name; cc->has_work = superh_cpu_has_work; - cc->do_interrupt = superh_cpu_do_interrupt; - cc->cpu_exec_interrupt = superh_cpu_exec_interrupt; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; - cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; cc->gdb_read_register = superh_cpu_gdb_read_register; cc->gdb_write_register = superh_cpu_gdb_write_register; - cc->tlb_fill = superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access = superh_cpu_do_unaligned_access; cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; #endif cc->disas_set_info = superh_cpu_disas_set_info; - cc->tcg_initialize = sh4_translate_init; cc->gdb_num_core_regs = 59; dc->vmsd = &vmstate_sh_cpu; + cc->tcg_ops = &superh_tcg_ops; } #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 6f14e370ed..aece2c7dc8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,23 @@ static Property sparc_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps sparc_tcg_ops = { + .initialize = sparc_tcg_init, + .synchronize_from_tb = sparc_cpu_synchronize_from_tb, + .cpu_exec_interrupt = sparc_cpu_exec_interrupt, + .tlb_fill = sparc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = sparc_cpu_do_interrupt, + .do_transaction_failed = sparc_cpu_do_transaction_failed, + .do_unaligned_access = sparc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void sparc_cpu_class_init(ObjectClass *oc, void *data) { SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); @@ -863,31 +880,25 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; cc->has_work = sparc_cpu_has_work; - cc->do_interrupt = sparc_cpu_do_interrupt; - cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug; #endif cc->set_pc = sparc_cpu_set_pc; - cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb; cc->gdb_read_register = sparc_cpu_gdb_read_register; cc->gdb_write_register = sparc_cpu_gdb_write_register; - cc->tlb_fill = sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = sparc_cpu_do_transaction_failed; - cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_sparc_cpu; #endif cc->disas_set_info = cpu_sparc_disas_set_info; - cc->tcg_initialize = sparc_tcg_init; #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs = 86; #else cc->gdb_num_core_regs = 72; #endif + cc->tcg_ops = &sparc_tcg_ops; } static const TypeInfo sparc_cpu_type_info = { diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 1fee87c094..d969c2f133 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -134,6 +134,18 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps tilegx_tcg_ops = { + .initialize = tilegx_tcg_init, + .cpu_exec_interrupt = tilegx_cpu_exec_interrupt, + .tlb_fill = tilegx_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = tilegx_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void tilegx_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -147,13 +159,10 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = tilegx_cpu_class_by_name; cc->has_work = tilegx_cpu_has_work; - cc->do_interrupt = tilegx_cpu_do_interrupt; - cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt; cc->dump_state = tilegx_cpu_dump_state; cc->set_pc = tilegx_cpu_set_pc; - cc->tlb_fill = tilegx_cpu_tlb_fill; cc->gdb_num_core_regs = 0; - cc->tcg_initialize = tilegx_tcg_init; + cc->tcg_ops = &tilegx_tcg_ops; } static const TypeInfo tilegx_cpu_type_info = { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 4bff1d4718..0b1e139bcb 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,14 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps tricore_tcg_ops = { + .initialize = tricore_tcg_init, + .synchronize_from_tb = tricore_cpu_synchronize_from_tb, + .tlb_fill = tricore_cpu_tlb_fill, +}; + static void tricore_cpu_class_init(ObjectClass *c, void *data) { TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c); @@ -162,10 +170,8 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) cc->dump_state = tricore_cpu_dump_state; cc->set_pc = tricore_cpu_set_pc; - cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug; - cc->tcg_initialize = tricore_tcg_init; - cc->tlb_fill = tricore_cpu_tlb_fill; + cc->tcg_ops = &tricore_tcg_ops; } #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index b27fb9689f..0258884f84 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,18 @@ static const VMStateDescription vmstate_uc32_cpu = { .unmigratable = 1, }; +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps uc32_tcg_ops = { + .initialize = uc32_translate_init, + .cpu_exec_interrupt = uc32_cpu_exec_interrupt, + .tlb_fill = uc32_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = uc32_cpu_do_interrupt, +#endif /* !CONFIG_USER_ONLY */ +}; + static void uc32_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -131,14 +143,11 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = uc32_cpu_class_by_name; cc->has_work = uc32_cpu_has_work; - cc->do_interrupt = uc32_cpu_do_interrupt; - cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; - cc->tlb_fill = uc32_cpu_tlb_fill; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; - cc->tcg_initialize = uc32_translate_init; dc->vmsd = &vmstate_uc32_cpu; + cc->tcg_ops = &uc32_tcg_ops; } #define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 88a32268a1..e2b2c7a71c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,21 @@ static const VMStateDescription vmstate_xtensa_cpu = { .unmigratable = 1, }; +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps xtensa_tcg_ops = { + .initialize = xtensa_translate_init, + .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, + .tlb_fill = xtensa_cpu_tlb_fill, + .debug_excp_handler = xtensa_breakpoint_handler, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = xtensa_cpu_do_interrupt, + .do_transaction_failed = xtensa_cpu_do_transaction_failed, + .do_unaligned_access = xtensa_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void xtensa_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -194,23 +209,17 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = xtensa_cpu_class_by_name; cc->has_work = xtensa_cpu_has_work; - cc->do_interrupt = xtensa_cpu_do_interrupt; - cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; cc->gdb_read_register = xtensa_cpu_gdb_read_register; cc->gdb_write_register = xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint = true; - cc->tlb_fill = xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; - cc->do_transaction_failed = xtensa_cpu_do_transaction_failed; #endif - cc->debug_excp_handler = xtensa_breakpoint_handler; cc->disas_set_info = xtensa_cpu_disas_set_info; - cc->tcg_initialize = xtensa_translate_init; dc->vmsd = &vmstate_xtensa_cpu; + cc->tcg_ops = &xtensa_tcg_ops; } static const TypeInfo xtensa_cpu_type_info = { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 05e2b7f70a..eeffee297d 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -#else +#else /* !CONFIG_USER_ONLY */ void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall) qemu_cpu_kick(cpu); } } -#endif +#endif /* !CONFIG_USER_ONLY */ |