diff options
Diffstat (limited to 'target')
27 files changed, 7386 insertions, 4615 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 13813fb213..ab3e1a0361 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -406,6 +406,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..d844ea21d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3105,33 +3108,44 @@ static inline uint64_t arm_sctlr(CPUARMState *env, int el) } } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { - return -#ifdef CONFIG_USER_ONLY - /* In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - arm_sctlr_b(env) || -#endif - ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); } else { int cur_el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, cur_el); - - return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); } } @@ -3140,15 +3154,18 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) @@ -3159,13 +3176,14 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. + * Not cached, because VECLEN+VECSTRIDE are not cached. */ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* @@ -3174,15 +3192,15 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ /* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ @@ -3194,7 +3212,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) @@ -3280,6 +3298,12 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); /** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + +/** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. */ diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bca80bdc38..b4cd680fc4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1025,6 +1025,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + helper_rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1036,10 +1037,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + helper_rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab7..63815fc4cf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4174,6 +4174,16 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); + + if (ri->type & ARM_CP_SUPPRESS_TB_END) { + /* + * Normally we would always end the TB on an SCTLR write; see the + * comment in ARMCPRegInfo sctlr initialization below for why Xscale + * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild + * of hflags from the translator, so do it here. + */ + arm_rebuild_hflags(env); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -7998,6 +8008,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + arm_rebuild_hflags(env); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -8345,6 +8356,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); + helper_rebuild_hflags_a64(env, new_el); env->pc = addr; @@ -11026,15 +11038,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif -ARMMMUIdx arm_mmu_idx(CPUARMState *env) +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { - int el; - if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } - el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { @@ -11042,6 +11051,11 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) } } +ARMMMUIdx arm_mmu_idx(CPUARMState *env) +{ + return arm_mmu_idx_el(env, arm_current_el(env)); +} + int cpu_mmu_index(CPUARMState *env, bool ifetch) { return arm_to_core_mmu_idx(arm_mmu_idx(env)); @@ -11054,171 +11068,276 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif -void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) +static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + bool sctlr_b = arm_sctlr_b(env); + + if (sctlr_b) { + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + } + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + +static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); uint32_t flags = 0; - if (is_a64(env)) { - ARMCPU *cpu = env_archcpu(env); - uint64_t sctlr; + /* v8M always enables the fpu. */ + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + if (arm_v7m_is_handler_mode(env)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + } - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } + /* + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN + * is suppressing them because the requested execution priority + * is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + } - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; +static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +{ + int flags = 0; - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } + flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, + arm_debug_target_el(env)); + return flags; +} - sctlr = arm_sctlr(env, current_el); +static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + uint32_t flags = rebuild_hflags_aprofile(env); - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } + if (arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } - flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); - } +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx) +{ + uint32_t flags = rebuild_hflags_aprofile(env); + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); } else { - *pc = env->regs[15]; - flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); - flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } - /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); - } + tbid = p0.tbi; + tbii = tbid & !p0.tbid; } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* + * If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } + zcr_len = sve_zcr_len_for_el(env, el); } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } - if (arm_cpu_data_is_big_endian(env)) { + + sctlr = arm_sctlr(env, el); + + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); - if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } } - /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is - * suppressing them because the requested execution priority is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - arm_feature(env, ARM_FEATURE_M) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); - } + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} - if (arm_feature(env, ARM_FEATURE_M) && - (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no active - * FP context; we must create a new FP context before executing - * any FP insn. - */ - flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); +static uint32_t rebuild_hflags_internal(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); } +} - if (arm_feature(env, ARM_FEATURE_M)) { - bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags = rebuild_hflags_internal(env); +} + +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); +} + +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + uint32_t flags = env->hflags; + uint32_t pstate_for_ss; - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + *cs_base = 0; +#ifdef CONFIG_DEBUG_TCG + assert(flags == rebuild_hflags_internal(env)); +#endif + + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { + *pc = env->pc; + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } - } + pstate_for_ss = env->pstate; + } else { + *pc = env->regs[15]; - if (!arm_feature(env, ARM_FEATURE_M)) { - int target_el = arm_debug_target_el(env); + if (arm_feature(env, ARM_FEATURE_M)) { + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + != env->v7m.secure) { + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context before + * executing any FP insn. + */ + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + } + } else { + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, + XSCALE_CPAR, env->cp15.c15_cpar); + } else { + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, + env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, + env->vfp.vec_stride); + } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } + } + + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); + pstate_for_ss = env->uncached_cpsr; + } - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el); + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. + */ + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && + (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } *pflags = flags; - *cs_base = 0; } #ifdef TARGET_AARCH64 diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a77..3d4ec267a2 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -90,6 +90,10 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..f5313dd3d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -950,6 +950,15 @@ void arm_cpu_update_virq(ARMCPU *cpu); void arm_cpu_update_vfiq(ARMCPU *cpu); /** + * arm_mmu_idx_el: + * @env: The cpu environment + * @el: The EL to use. + * + * Return the full ARMMMUIdx for the translation regime for EL. + */ +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); + +/** * arm_mmu_idx: * @env: The cpu environment * diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 27cd2f3f96..f2512e448e 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -494,6 +494,7 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, dest & 1); env->thumb = 1; env->regs[15] = dest & ~1; + arm_rebuild_hflags(env); } void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) @@ -555,6 +556,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, 0); env->thumb = 1; env->regs[15] = dest; + arm_rebuild_hflags(env); } static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, @@ -895,6 +897,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, env->regs[14] = lr; env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + arm_rebuild_hflags(env); } static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, @@ -1765,6 +1768,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Otherwise, we have a successful exception exit. */ arm_clear_exclusive(env); + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } @@ -1837,6 +1841,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) xpsr_write(env, 0, XPSR_IT); env->thumb = newpc & 1; env->regs[15] = newpc & ~1; + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); return true; @@ -1959,6 +1964,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; + arm_rebuild_hflags(env); return true; gen_invep: diff --git a/target/arm/machine.c b/target/arm/machine.c index 5c36707a7c..eb28b2381b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -756,6 +756,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd0238..b529d6c1bf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -224,6 +224,7 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) void HELPER(setend)(CPUARMState *env) { env->uncached_cpsr ^= CPSR_E; + arm_rebuild_hflags(env); } /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. @@ -387,6 +388,8 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { cpsr_write(env, val, mask, CPSRWriteByInstr); + /* TODO: Not all cpsr bits are relevant to hflags. */ + arm_rebuild_hflags(env); } /* Write the CPSR for a 32-bit exception return */ @@ -404,6 +407,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) * state. Do the masking now. */ env->regs[15] &= (env->thumb ? ~1 : ~3); + arm_rebuild_hflags(env); qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..d4bebbe629 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 698c594e8c..2ea9da7637 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - /* I/O operations must end the TB here (whether read or write) */ - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && + (ri->type & ARM_CP_IO)); + + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } @@ -8045,7 +8063,9 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, case 2: tl = load_reg(s, a->ra); th = load_reg(s, a->rd); - t1 = tcg_const_i32(0); + /* Sign-extend the 32-bit product to 64 bits. */ + t1 = tcg_temp_new_i32(); + tcg_gen_sari_i32(t1, t0, 31); tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -8307,7 +8327,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) { - TCGv_i32 addr, reg; + TCGv_i32 addr, reg, el; if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -8317,6 +8337,9 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) gen_helper_v7m_msr(cpu_env, addr, reg); tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); + el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_m32(cpu_env, el); + tcg_temp_free_i32(el); gen_lookup_tb(s); return true; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b635302859..a624163ac2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2725,6 +2725,53 @@ static X86CPUDefinition builtin_x86_defs[] = { .model_id = "Intel Xeon Processor (Icelake)", }, { + .name = "Denverton", + .level = 21, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 95, + .stepping = 1, + .features[FEAT_1_EDX] = + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | + CPUID_SSE | CPUID_SSE2, + .features[FEAT_1_ECX] = + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | + CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | + CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | + CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | + CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | + CPUID_7_0_EDX_SPEC_CTRL_SSBD, + /* + * Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .features[FEAT_ARCH_CAPABILITIES] = + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, + .xlevel = 0x80000008, + .model_id = "Intel Atom Processor (Denverton)", + }, + { .name = "Snowridge", .level = 27, .vendor = CPUID_VENDOR_INTEL, diff --git a/target/mips/helper.c b/target/mips/helper.c index a2b6459b05..781930a7dd 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -39,8 +39,8 @@ enum { #if !defined(CONFIG_USER_ONLY) /* no MMU emulation */ -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, } /* fixed mapping MMU emulation */ -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { if (address <= (int32_t)0x7FFFFFFFUL) { - if (!(env->CP0_Status & (1 << CP0St_ERL))) + if (!(env->CP0_Status & (1 << CP0St_ERL))) { *physical = address + 0x40000000UL; - else + } else { *physical = address; - } else if (address <= (int32_t)0xBFFFFFFFUL) + } + } else if (address <= (int32_t)0xBFFFFFFFUL) { *physical = address & 0x1FFFFFFF; - else + } else { *physical = address; + } *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type) +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type) { uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; @@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { *physical = tlb->PFN[n] | (address & (mask >> 1)); *prot = PAGE_READ; - if (n ? tlb->D1 : tlb->D0) + if (n ? tlb->D1 : tlb->D0) { *prot |= PAGE_WRITE; + } if (!(n ? tlb->XI1 : tlb->XI0)) { *prot |= PAGE_EXEC; } @@ -130,7 +133,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) int32_t adetlb_mask; switch (mmu_idx) { - case 3 /* ERL */: + case 3: /* ERL */ /* If EU is set, always unmapped */ if (eu) { return 0; @@ -204,7 +207,7 @@ static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, pa & ~(hwaddr)segmask); } -static int get_physical_address (CPUMIPSState *env, hwaddr *physical, +static int get_physical_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong real_address, int rw, int access_type, int mmu_idx) { @@ -252,14 +255,15 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, } else { segctl = env->CP0_SegCtl2 >> 16; } - ret = get_segctl_physical_address(env, physical, prot, real_address, rw, - access_type, mmu_idx, segctl, - 0x3FFFFFFF); + ret = get_segctl_physical_address(env, physical, prot, + real_address, rw, access_type, + mmu_idx, segctl, 0x3FFFFFFF); #if defined(TARGET_MIPS64) } else if (address < 0x4000000000000000ULL) { /* xuseg */ if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -267,7 +271,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, /* xsseg */ if ((supervisor_mode || kernel_mode) && SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -307,7 +312,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, /* xkseg */ if (kernel_mode && KX && address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, + real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -328,8 +334,10 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, access_type, mmu_idx, env->CP0_SegCtl0 >> 16, 0x1FFFFFFF); } else { - /* kseg3 */ - /* XXX: debug segment is not emulated */ + /* + * kseg3 + * XXX: debug segment is not emulated + */ ret = get_segctl_physical_address(env, physical, prot, real_address, rw, access_type, mmu_idx, env->CP0_SegCtl0, 0x1FFFFFFF); @@ -515,9 +523,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, #if defined(TARGET_MIPS64) env->CP0_EntryHi &= env->SEGMask; env->CP0_XContext = - /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | - /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | - /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); + (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */ + (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */ + (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */ #endif cs->exception_index = exception; env->error_code = error_code; @@ -945,7 +953,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } #ifndef CONFIG_USER_ONLY -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + int rw) { hwaddr physical; int prot; @@ -1005,7 +1014,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { }; #endif -target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc(CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -1013,8 +1022,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env) isa_mode = !!(env->hflags & MIPS_HFLAG_M16); bad_pc = env->active_tc.PC | isa_mode; if (env->hflags & MIPS_HFLAG_BMASK) { - /* If the exception was raised from a delay slot, come back to - the jump. */ + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); } @@ -1022,14 +1033,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env) } #if !defined(CONFIG_USER_ONLY) -static void set_hflags_for_handler (CPUMIPSState *env) +static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ env->hflags &= ~(MIPS_HFLAG_M16); /* ...except that microMIPS lets you choose. */ if (env->insn_flags & ASE_MICROMIPS) { - env->hflags |= (!!(env->CP0_Config3 - & (1 << CP0C3_ISA_ON_EXC)) + env->hflags |= (!!(env->CP0_Config3 & + (1 << CP0C3_ISA_ON_EXC)) << MIPS_HFLAG_M16_SHIFT); } } @@ -1096,10 +1107,12 @@ void mips_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; - /* Debug single step cannot be raised inside a delay slot and - resume will always occur on the next instruction - (but we assume the pc has always been updated during - code translation). */ + /* + * Debug single step cannot be raised inside a delay slot and + * resume will always occur on the next instruction + * (but we assume the pc has always been updated during + * code translation). + */ env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); goto enter_debug_mode; case EXCP_DINT: @@ -1111,7 +1124,8 @@ void mips_cpu_do_interrupt(CPUState *cs) case EXCP_DBp: env->CP0_Debug |= 1 << CP0DB_DBp; /* Setup DExcCode - SDBBP instruction */ - env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC; + env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | + (9 << CP0DB_DEC); goto set_DEPC; case EXCP_DDBS: env->CP0_Debug |= 1 << CP0DB_DDBS; @@ -1132,8 +1146,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); /* EJTAG probe trap enable is not implemented... */ - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &= ~(1U << CP0Ca_BD); + } env->active_tc.PC = env->exception_base + 0x480; set_hflags_for_handler(env); break; @@ -1159,8 +1174,9 @@ void mips_cpu_do_interrupt(CPUState *cs) } env->hflags |= MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); - if (!(env->CP0_Status & (1 << CP0St_EXL))) + if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_Cause &= ~(1U << CP0Ca_BD); + } env->active_tc.PC = env->exception_base; set_hflags_for_handler(env); break; @@ -1176,12 +1192,16 @@ void mips_cpu_do_interrupt(CPUState *cs) uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* For VEIC mode, the external interrupt controller feeds - * the vector through the CP0Cause IP lines. */ + /* + * For VEIC mode, the external interrupt controller feeds + * the vector through the CP0Cause IP lines. + */ vector = pending; } else { - /* Vectored Interrupts - * Mask with Status.IM7-IM0 to get enabled interrupts. */ + /* + * Vectored Interrupts + * Mask with Status.IM7-IM0 to get enabled interrupts. + */ pending &= (env->CP0_Status >> CP0St_IM) & 0xff; /* Find the highest-priority interrupt. */ while (pending >>= 1) { @@ -1354,7 +1374,8 @@ void mips_cpu_do_interrupt(CPUState *cs) env->active_tc.PC += offset; set_hflags_for_handler(env); - env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); + env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | + (cause << CP0Ca_EC); break; default: abort(); @@ -1390,7 +1411,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } #if !defined(CONFIG_USER_ONLY) -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs = env_cpu(env); r4k_tlb_t *tlb; @@ -1400,16 +1421,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) target_ulong mask; tlb = &env->tlb->mmu.r4k.tlb[idx]; - /* The qemu TLB is flushed when the ASID changes, so no need to - flush these entries again. */ + /* + * The qemu TLB is flushed when the ASID changes, so no need to + * flush these entries again. + */ if (tlb->G == 0 && tlb->ASID != ASID) { return; } if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { - /* For tlbwr, we can shadow the discarded entry into - a new (fake) TLB entry, as long as the guest can not - tell that it's there. */ + /* + * For tlbwr, we can shadow the discarded entry into + * a new (fake) TLB entry, as long as the guest can not + * tell that it's there. + */ env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; env->tlb->tlb_in_use++; return; diff --git a/target/mips/helper.h b/target/mips/helper.h index d615c83c54..7b8ad74d67 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -822,6 +822,39 @@ DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) @@ -877,6 +910,31 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) @@ -887,11 +945,80 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) + DEF_HELPER_3(msa_move_v, void, env, i32, i32) DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) @@ -929,29 +1056,13 @@ DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_asub_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32) @@ -963,19 +1074,7 @@ DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hadd_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hadd_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index a2052baa57..4065cfe4f7 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -805,7 +805,490 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) * +---------------+----------------------------------------------------------+ */ -/* TODO: insert Int Add group helpers here */ + +static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; + uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; + return abs_arg1 + abs_arg2; +} + +void helper_msa_add_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_add_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_add_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_add_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_add_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_add_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_add_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_add_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_add_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_add_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_add_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_add_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_add_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_add_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_add_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_add_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_add_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_add_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_add_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_add_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_add_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_add_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_add_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_add_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_add_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_add_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_add_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_add_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_add_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_add_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_add_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_add_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_add_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_add_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t max_int = (uint64_t)DF_MAX_INT(df); + uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; + uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; + if (abs_arg1 > max_int || abs_arg2 > max_int) { + return (int64_t)max_int; + } else { + return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int; + } +} + +void helper_msa_adds_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_adds_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_adds_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_adds_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_adds_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_adds_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_adds_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_adds_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_adds_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_adds_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_adds_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_adds_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_adds_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_adds_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_adds_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_adds_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_adds_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_adds_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_adds_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_adds_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_adds_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_adds_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_adds_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_adds_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_adds_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_adds_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_adds_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_adds_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_adds_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_adds_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_adds_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_adds_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_adds_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_adds_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int64_t max_int = DF_MAX_INT(df); + int64_t min_int = DF_MIN_INT(df); + if (arg1 < 0) { + return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int; + } else { + return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int; + } +} + +void helper_msa_adds_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_adds_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_adds_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_adds_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_adds_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_adds_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_adds_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_adds_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_adds_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_adds_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_adds_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_adds_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_adds_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_adds_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_adds_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_adds_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_adds_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_adds_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_adds_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_adds_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_adds_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_adds_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_adds_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_adds_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_adds_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_adds_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_adds_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_adds_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_adds_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_adds_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_adds_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_adds_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_adds_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_adds_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) +{ + uint64_t max_uint = DF_MAX_UINT(df); + uint64_t u_arg1 = UNSIGNED(arg1, df); + uint64_t u_arg2 = UNSIGNED(arg2, df); + return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; +} + +void helper_msa_adds_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_adds_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_adds_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_adds_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_adds_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_adds_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_adds_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_adds_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_adds_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_adds_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_adds_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_adds_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_adds_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_adds_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_adds_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_adds_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_adds_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_adds_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_adds_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_adds_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_adds_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_adds_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_adds_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_adds_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_adds_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_adds_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_adds_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_adds_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_adds_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_adds_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_adds_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_adds_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_adds_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_adds_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 + arg2; +} + +void helper_msa_addv_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_addv_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_addv_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_addv_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_addv_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_addv_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_addv_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_addv_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_addv_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_addv_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_addv_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_addv_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_addv_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_addv_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_addv_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_addv_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_addv_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_addv_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_addv_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_addv_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_addv_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_addv_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_addv_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_addv_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_addv_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_addv_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_addv_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_addv_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_addv_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_addv_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_addv_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_addv_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_addv_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_addv_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +#define SIGNED_EVEN(a, df) \ + ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2)) + +#define UNSIGNED_EVEN(a, df) \ + ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2)) + +#define SIGNED_ODD(a, df) \ + ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) + +#define UNSIGNED_ODD(a, df) \ + ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) + + +static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df); +} + +void helper_msa_hadd_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_hadd_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_hadd_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_hadd_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_hadd_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_hadd_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_hadd_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_hadd_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_hadd_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hadd_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_hadd_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_hadd_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_hadd_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_hadd_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hadd_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_hadd_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_hadd_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df); +} + +void helper_msa_hadd_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_hadd_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_hadd_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_hadd_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_hadd_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_hadd_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_hadd_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_hadd_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_hadd_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hadd_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_hadd_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_hadd_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_hadd_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_hadd_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hadd_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_hadd_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_hadd_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} /* @@ -1158,28 +1641,38 @@ static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2) return arg1 == arg2 ? -1 : 0; } +static inline int8_t msa_ceq_b(int8_t arg1, int8_t arg2) +{ + return arg1 == arg2 ? -1 : 0; +} + void helper_msa_ceq_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->b[0] = msa_ceq_df(DF_BYTE, pws->b[0], pwt->b[0]); - pwd->b[1] = msa_ceq_df(DF_BYTE, pws->b[1], pwt->b[1]); - pwd->b[2] = msa_ceq_df(DF_BYTE, pws->b[2], pwt->b[2]); - pwd->b[3] = msa_ceq_df(DF_BYTE, pws->b[3], pwt->b[3]); - pwd->b[4] = msa_ceq_df(DF_BYTE, pws->b[4], pwt->b[4]); - pwd->b[5] = msa_ceq_df(DF_BYTE, pws->b[5], pwt->b[5]); - pwd->b[6] = msa_ceq_df(DF_BYTE, pws->b[6], pwt->b[6]); - pwd->b[7] = msa_ceq_df(DF_BYTE, pws->b[7], pwt->b[7]); - pwd->b[8] = msa_ceq_df(DF_BYTE, pws->b[8], pwt->b[8]); - pwd->b[9] = msa_ceq_df(DF_BYTE, pws->b[9], pwt->b[9]); - pwd->b[10] = msa_ceq_df(DF_BYTE, pws->b[10], pwt->b[10]); - pwd->b[11] = msa_ceq_df(DF_BYTE, pws->b[11], pwt->b[11]); - pwd->b[12] = msa_ceq_df(DF_BYTE, pws->b[12], pwt->b[12]); - pwd->b[13] = msa_ceq_df(DF_BYTE, pws->b[13], pwt->b[13]); - pwd->b[14] = msa_ceq_df(DF_BYTE, pws->b[14], pwt->b[14]); - pwd->b[15] = msa_ceq_df(DF_BYTE, pws->b[15], pwt->b[15]); + pwd->b[0] = msa_ceq_b(pws->b[0], pwt->b[0]); + pwd->b[1] = msa_ceq_b(pws->b[1], pwt->b[1]); + pwd->b[2] = msa_ceq_b(pws->b[2], pwt->b[2]); + pwd->b[3] = msa_ceq_b(pws->b[3], pwt->b[3]); + pwd->b[4] = msa_ceq_b(pws->b[4], pwt->b[4]); + pwd->b[5] = msa_ceq_b(pws->b[5], pwt->b[5]); + pwd->b[6] = msa_ceq_b(pws->b[6], pwt->b[6]); + pwd->b[7] = msa_ceq_b(pws->b[7], pwt->b[7]); + pwd->b[8] = msa_ceq_b(pws->b[8], pwt->b[8]); + pwd->b[9] = msa_ceq_b(pws->b[9], pwt->b[9]); + pwd->b[10] = msa_ceq_b(pws->b[10], pwt->b[10]); + pwd->b[11] = msa_ceq_b(pws->b[11], pwt->b[11]); + pwd->b[12] = msa_ceq_b(pws->b[12], pwt->b[12]); + pwd->b[13] = msa_ceq_b(pws->b[13], pwt->b[13]); + pwd->b[14] = msa_ceq_b(pws->b[14], pwt->b[14]); + pwd->b[15] = msa_ceq_b(pws->b[15], pwt->b[15]); +} + +static inline int16_t msa_ceq_h(int16_t arg1, int16_t arg2) +{ + return arg1 == arg2 ? -1 : 0; } void helper_msa_ceq_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) @@ -1188,14 +1681,19 @@ void helper_msa_ceq_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->h[0] = msa_ceq_df(DF_HALF, pws->h[0], pwt->h[0]); - pwd->h[1] = msa_ceq_df(DF_HALF, pws->h[1], pwt->h[1]); - pwd->h[2] = msa_ceq_df(DF_HALF, pws->h[2], pwt->h[2]); - pwd->h[3] = msa_ceq_df(DF_HALF, pws->h[3], pwt->h[3]); - pwd->h[4] = msa_ceq_df(DF_HALF, pws->h[4], pwt->h[4]); - pwd->h[5] = msa_ceq_df(DF_HALF, pws->h[5], pwt->h[5]); - pwd->h[6] = msa_ceq_df(DF_HALF, pws->h[6], pwt->h[6]); - pwd->h[7] = msa_ceq_df(DF_HALF, pws->h[7], pwt->h[7]); + pwd->h[0] = msa_ceq_h(pws->h[0], pwt->h[0]); + pwd->h[1] = msa_ceq_h(pws->h[1], pwt->h[1]); + pwd->h[2] = msa_ceq_h(pws->h[2], pwt->h[2]); + pwd->h[3] = msa_ceq_h(pws->h[3], pwt->h[3]); + pwd->h[4] = msa_ceq_h(pws->h[4], pwt->h[4]); + pwd->h[5] = msa_ceq_h(pws->h[5], pwt->h[5]); + pwd->h[6] = msa_ceq_h(pws->h[6], pwt->h[6]); + pwd->h[7] = msa_ceq_h(pws->h[7], pwt->h[7]); +} + +static inline int32_t msa_ceq_w(int32_t arg1, int32_t arg2) +{ + return arg1 == arg2 ? -1 : 0; } void helper_msa_ceq_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) @@ -1204,10 +1702,15 @@ void helper_msa_ceq_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->w[0] = msa_ceq_df(DF_WORD, pws->w[0], pwt->w[0]); - pwd->w[1] = msa_ceq_df(DF_WORD, pws->w[1], pwt->w[1]); - pwd->w[2] = msa_ceq_df(DF_WORD, pws->w[2], pwt->w[2]); - pwd->w[3] = msa_ceq_df(DF_WORD, pws->w[3], pwt->w[3]); + pwd->w[0] = msa_ceq_w(pws->w[0], pwt->w[0]); + pwd->w[1] = msa_ceq_w(pws->w[1], pwt->w[1]); + pwd->w[2] = msa_ceq_w(pws->w[2], pwt->w[2]); + pwd->w[3] = msa_ceq_w(pws->w[3], pwt->w[3]); +} + +static inline int64_t msa_ceq_d(int64_t arg1, int64_t arg2) +{ + return arg1 == arg2 ? -1 : 0; } void helper_msa_ceq_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) @@ -1216,8 +1719,8 @@ void helper_msa_ceq_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->d[0] = msa_ceq_df(DF_DOUBLE, pws->d[0], pwt->d[0]); - pwd->d[1] = msa_ceq_df(DF_DOUBLE, pws->d[1], pwt->d[1]); + pwd->d[0] = msa_ceq_d(pws->d[0], pwt->d[0]); + pwd->d[1] = msa_ceq_d(pws->d[1], pwt->d[1]); } static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2) @@ -1369,6 +1872,11 @@ static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) return arg1 < arg2 ? -1 : 0; } +static inline int8_t msa_clt_s_b(int8_t arg1, int8_t arg2) +{ + return arg1 < arg2 ? -1 : 0; +} + void helper_msa_clt_s_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) { @@ -1376,22 +1884,27 @@ void helper_msa_clt_s_b(CPUMIPSState *env, wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->b[0] = msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[0]); - pwd->b[1] = msa_clt_s_df(DF_BYTE, pws->b[1], pwt->b[1]); - pwd->b[2] = msa_clt_s_df(DF_BYTE, pws->b[2], pwt->b[2]); - pwd->b[3] = msa_clt_s_df(DF_BYTE, pws->b[3], pwt->b[3]); - pwd->b[4] = msa_clt_s_df(DF_BYTE, pws->b[4], pwt->b[4]); - pwd->b[5] = msa_clt_s_df(DF_BYTE, pws->b[5], pwt->b[5]); - pwd->b[6] = msa_clt_s_df(DF_BYTE, pws->b[6], pwt->b[6]); - pwd->b[7] = msa_clt_s_df(DF_BYTE, pws->b[7], pwt->b[7]); - pwd->b[8] = msa_clt_s_df(DF_BYTE, pws->b[8], pwt->b[8]); - pwd->b[9] = msa_clt_s_df(DF_BYTE, pws->b[9], pwt->b[9]); - pwd->b[10] = msa_clt_s_df(DF_BYTE, pws->b[10], pwt->b[10]); - pwd->b[11] = msa_clt_s_df(DF_BYTE, pws->b[11], pwt->b[11]); - pwd->b[12] = msa_clt_s_df(DF_BYTE, pws->b[12], pwt->b[12]); - pwd->b[13] = msa_clt_s_df(DF_BYTE, pws->b[13], pwt->b[13]); - pwd->b[14] = msa_clt_s_df(DF_BYTE, pws->b[14], pwt->b[14]); - pwd->b[15] = msa_clt_s_df(DF_BYTE, pws->b[15], pwt->b[15]); + pwd->b[0] = msa_clt_s_b(pws->b[0], pwt->b[0]); + pwd->b[1] = msa_clt_s_b(pws->b[1], pwt->b[1]); + pwd->b[2] = msa_clt_s_b(pws->b[2], pwt->b[2]); + pwd->b[3] = msa_clt_s_b(pws->b[3], pwt->b[3]); + pwd->b[4] = msa_clt_s_b(pws->b[4], pwt->b[4]); + pwd->b[5] = msa_clt_s_b(pws->b[5], pwt->b[5]); + pwd->b[6] = msa_clt_s_b(pws->b[6], pwt->b[6]); + pwd->b[7] = msa_clt_s_b(pws->b[7], pwt->b[7]); + pwd->b[8] = msa_clt_s_b(pws->b[8], pwt->b[8]); + pwd->b[9] = msa_clt_s_b(pws->b[9], pwt->b[9]); + pwd->b[10] = msa_clt_s_b(pws->b[10], pwt->b[10]); + pwd->b[11] = msa_clt_s_b(pws->b[11], pwt->b[11]); + pwd->b[12] = msa_clt_s_b(pws->b[12], pwt->b[12]); + pwd->b[13] = msa_clt_s_b(pws->b[13], pwt->b[13]); + pwd->b[14] = msa_clt_s_b(pws->b[14], pwt->b[14]); + pwd->b[15] = msa_clt_s_b(pws->b[15], pwt->b[15]); +} + +static inline int16_t msa_clt_s_h(int16_t arg1, int16_t arg2) +{ + return arg1 < arg2 ? -1 : 0; } void helper_msa_clt_s_h(CPUMIPSState *env, @@ -1401,14 +1914,19 @@ void helper_msa_clt_s_h(CPUMIPSState *env, wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->h[0] = msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[0]); - pwd->h[1] = msa_clt_s_df(DF_HALF, pws->h[1], pwt->h[1]); - pwd->h[2] = msa_clt_s_df(DF_HALF, pws->h[2], pwt->h[2]); - pwd->h[3] = msa_clt_s_df(DF_HALF, pws->h[3], pwt->h[3]); - pwd->h[4] = msa_clt_s_df(DF_HALF, pws->h[4], pwt->h[4]); - pwd->h[5] = msa_clt_s_df(DF_HALF, pws->h[5], pwt->h[5]); - pwd->h[6] = msa_clt_s_df(DF_HALF, pws->h[6], pwt->h[6]); - pwd->h[7] = msa_clt_s_df(DF_HALF, pws->h[7], pwt->h[7]); + pwd->h[0] = msa_clt_s_h(pws->h[0], pwt->h[0]); + pwd->h[1] = msa_clt_s_h(pws->h[1], pwt->h[1]); + pwd->h[2] = msa_clt_s_h(pws->h[2], pwt->h[2]); + pwd->h[3] = msa_clt_s_h(pws->h[3], pwt->h[3]); + pwd->h[4] = msa_clt_s_h(pws->h[4], pwt->h[4]); + pwd->h[5] = msa_clt_s_h(pws->h[5], pwt->h[5]); + pwd->h[6] = msa_clt_s_h(pws->h[6], pwt->h[6]); + pwd->h[7] = msa_clt_s_h(pws->h[7], pwt->h[7]); +} + +static inline int32_t msa_clt_s_w(int32_t arg1, int32_t arg2) +{ + return arg1 < arg2 ? -1 : 0; } void helper_msa_clt_s_w(CPUMIPSState *env, @@ -1418,10 +1936,15 @@ void helper_msa_clt_s_w(CPUMIPSState *env, wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->w[0] = msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[0]); - pwd->w[1] = msa_clt_s_df(DF_WORD, pws->w[1], pwt->w[1]); - pwd->w[2] = msa_clt_s_df(DF_WORD, pws->w[2], pwt->w[2]); - pwd->w[3] = msa_clt_s_df(DF_WORD, pws->w[3], pwt->w[3]); + pwd->w[0] = msa_clt_s_w(pws->w[0], pwt->w[0]); + pwd->w[1] = msa_clt_s_w(pws->w[1], pwt->w[1]); + pwd->w[2] = msa_clt_s_w(pws->w[2], pwt->w[2]); + pwd->w[3] = msa_clt_s_w(pws->w[3], pwt->w[3]); +} + +static inline int64_t msa_clt_s_d(int64_t arg1, int64_t arg2) +{ + return arg1 < arg2 ? -1 : 0; } void helper_msa_clt_s_d(CPUMIPSState *env, @@ -1431,8 +1954,8 @@ void helper_msa_clt_s_d(CPUMIPSState *env, wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->d[0] = msa_clt_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); - pwd->d[1] = msa_clt_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); + pwd->d[0] = msa_clt_s_d(pws->d[0], pwt->d[0]); + pwd->d[1] = msa_clt_s_d(pws->d[1], pwt->d[1]); } static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2) @@ -1736,7 +2259,444 @@ void helper_msa_div_u_d(CPUMIPSState *env, * +---------------+----------------------------------------------------------+ */ -/* TODO: insert Int Max Min group helpers here */ +static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; + uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; + return abs_arg1 > abs_arg2 ? arg1 : arg2; +} + +void helper_msa_max_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_max_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_max_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_max_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_max_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_max_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_max_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_max_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_max_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_max_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_max_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_max_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_max_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_max_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_max_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_max_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_max_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_max_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_max_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_max_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_max_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_max_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_max_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_max_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_max_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_max_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_max_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_max_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_max_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_max_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_max_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 > arg2 ? arg1 : arg2; +} + +void helper_msa_max_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_max_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_max_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_max_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_max_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_max_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_max_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_max_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_max_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_max_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_max_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_max_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_max_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_max_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_max_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_max_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_max_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_max_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_max_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_max_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_max_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_max_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_max_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_max_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_max_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_max_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_max_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_max_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_max_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_max_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_max_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 = UNSIGNED(arg1, df); + uint64_t u_arg2 = UNSIGNED(arg2, df); + return u_arg1 > u_arg2 ? arg1 : arg2; +} + +void helper_msa_max_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_max_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_max_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_max_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_max_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_max_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_max_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_max_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_max_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_max_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_max_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_max_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_max_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_max_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_max_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_max_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_max_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_max_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_max_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_max_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_max_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_max_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_max_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_max_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_max_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_max_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_max_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_max_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_max_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_max_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_max_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_max_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_max_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_max_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; + uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; + return abs_arg1 < abs_arg2 ? arg1 : arg2; +} + +void helper_msa_min_a_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_min_a_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_min_a_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_min_a_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_min_a_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_min_a_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_min_a_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_min_a_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_min_a_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_min_a_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_min_a_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_min_a_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_min_a_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_min_a_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_min_a_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_min_a_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_min_a_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_a_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_min_a_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_min_a_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_min_a_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_min_a_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_min_a_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_min_a_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_min_a_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_min_a_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_a_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_min_a_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_min_a_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_min_a_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_min_a_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_a_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_min_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_min_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return arg1 < arg2 ? arg1 : arg2; +} + +void helper_msa_min_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_min_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_min_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_min_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_min_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_min_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_min_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_min_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_min_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_min_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_min_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_min_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_min_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_min_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_min_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_min_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_min_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_min_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_min_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_min_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_min_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_min_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_min_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_min_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_min_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_min_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_min_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_min_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_min_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_min_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_min_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 = UNSIGNED(arg1, df); + uint64_t u_arg2 = UNSIGNED(arg2, df); + return u_arg1 < u_arg2 ? arg1 : arg2; +} + +void helper_msa_min_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_min_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_min_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_min_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_min_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_min_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_min_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_min_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_min_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_min_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_min_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_min_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_min_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_min_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_min_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_min_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_min_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_min_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_min_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_min_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_min_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_min_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_min_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_min_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_min_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_min_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_min_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_min_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_min_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_min_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_min_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_min_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_min_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_min_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} /* @@ -1968,7 +2928,252 @@ void helper_msa_mod_u_d(CPUMIPSState *env, * +---------------+----------------------------------------------------------+ */ -/* TODO: insert Int Subtract group helpers here */ + +static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + /* signed compare */ + return (arg1 < arg2) ? + (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2); +} + +void helper_msa_asub_s_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_asub_s_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_asub_s_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_asub_s_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_asub_s_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_asub_s_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_asub_s_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_asub_s_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_asub_s_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_asub_s_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_asub_s_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_asub_s_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_asub_s_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_asub_s_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_asub_s_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_asub_s_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_asub_s_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_asub_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_asub_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_asub_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_asub_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_asub_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_asub_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_asub_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_asub_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_asub_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_asub_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_asub_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_asub_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_asub_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_asub_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_asub_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_asub_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_asub_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) +{ + uint64_t u_arg1 = UNSIGNED(arg1, df); + uint64_t u_arg2 = UNSIGNED(arg2, df); + /* unsigned compare */ + return (u_arg1 < u_arg2) ? + (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2); +} + +void helper_msa_asub_u_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_asub_u_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_asub_u_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_asub_u_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_asub_u_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_asub_u_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_asub_u_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_asub_u_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_asub_u_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_asub_u_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_asub_u_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_asub_u_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_asub_u_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_asub_u_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_asub_u_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_asub_u_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_asub_u_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_asub_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_asub_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_asub_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_asub_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_asub_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_asub_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_asub_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_asub_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_asub_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_asub_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_asub_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_asub_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_asub_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_asub_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_asub_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_asub_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_asub_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +/* TODO: insert the rest of Int Subtract group helpers here */ + + +static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df); +} + +void helper_msa_hsub_s_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_hsub_s_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_hsub_s_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_hsub_s_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_hsub_s_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_hsub_s_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_hsub_s_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_hsub_s_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_hsub_s_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hsub_s_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_hsub_s_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_hsub_s_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_hsub_s_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_hsub_s_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hsub_s_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_hsub_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_hsub_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df); +} + +void helper_msa_hsub_u_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_hsub_u_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_hsub_u_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_hsub_u_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_hsub_u_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_hsub_u_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_hsub_u_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_hsub_u_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_hsub_u_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_hsub_u_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_hsub_u_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_hsub_u_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_hsub_u_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_hsub_u_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_hsub_u_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_hsub_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_hsub_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} /* @@ -1995,7 +3200,421 @@ void helper_msa_mod_u_d(CPUMIPSState *env, * +---------------+----------------------------------------------------------+ */ -/* TODO: insert Interleave group helpers here */ + +void helper_msa_ilvev_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] = pws->b[9]; + pwd->b[9] = pwt->b[9]; + pwd->b[10] = pws->b[11]; + pwd->b[11] = pwt->b[11]; + pwd->b[12] = pws->b[13]; + pwd->b[13] = pwt->b[13]; + pwd->b[14] = pws->b[15]; + pwd->b[15] = pwt->b[15]; + pwd->b[0] = pws->b[1]; + pwd->b[1] = pwt->b[1]; + pwd->b[2] = pws->b[3]; + pwd->b[3] = pwt->b[3]; + pwd->b[4] = pws->b[5]; + pwd->b[5] = pwt->b[5]; + pwd->b[6] = pws->b[7]; + pwd->b[7] = pwt->b[7]; +#else + pwd->b[15] = pws->b[14]; + pwd->b[14] = pwt->b[14]; + pwd->b[13] = pws->b[12]; + pwd->b[12] = pwt->b[12]; + pwd->b[11] = pws->b[10]; + pwd->b[10] = pwt->b[10]; + pwd->b[9] = pws->b[8]; + pwd->b[8] = pwt->b[8]; + pwd->b[7] = pws->b[6]; + pwd->b[6] = pwt->b[6]; + pwd->b[5] = pws->b[4]; + pwd->b[4] = pwt->b[4]; + pwd->b[3] = pws->b[2]; + pwd->b[2] = pwt->b[2]; + pwd->b[1] = pws->b[0]; + pwd->b[0] = pwt->b[0]; +#endif +} + +void helper_msa_ilvev_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] = pws->h[5]; + pwd->h[5] = pwt->h[5]; + pwd->h[6] = pws->h[7]; + pwd->h[7] = pwt->h[7]; + pwd->h[0] = pws->h[1]; + pwd->h[1] = pwt->h[1]; + pwd->h[2] = pws->h[3]; + pwd->h[3] = pwt->h[3]; +#else + pwd->h[7] = pws->h[6]; + pwd->h[6] = pwt->h[6]; + pwd->h[5] = pws->h[4]; + pwd->h[4] = pwt->h[4]; + pwd->h[3] = pws->h[2]; + pwd->h[2] = pwt->h[2]; + pwd->h[1] = pws->h[0]; + pwd->h[0] = pwt->h[0]; +#endif +} + +void helper_msa_ilvev_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] = pws->w[3]; + pwd->w[3] = pwt->w[3]; + pwd->w[0] = pws->w[1]; + pwd->w[1] = pwt->w[1]; +#else + pwd->w[3] = pws->w[2]; + pwd->w[2] = pwt->w[2]; + pwd->w[1] = pws->w[0]; + pwd->w[0] = pwt->w[0]; +#endif +} + +void helper_msa_ilvev_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[1] = pws->d[0]; + pwd->d[0] = pwt->d[0]; +} + + +void helper_msa_ilvod_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] = pwt->b[6]; + pwd->b[6] = pws->b[6]; + pwd->b[5] = pwt->b[4]; + pwd->b[4] = pws->b[4]; + pwd->b[3] = pwt->b[2]; + pwd->b[2] = pws->b[2]; + pwd->b[1] = pwt->b[0]; + pwd->b[0] = pws->b[0]; + pwd->b[15] = pwt->b[14]; + pwd->b[14] = pws->b[14]; + pwd->b[13] = pwt->b[12]; + pwd->b[12] = pws->b[12]; + pwd->b[11] = pwt->b[10]; + pwd->b[10] = pws->b[10]; + pwd->b[9] = pwt->b[8]; + pwd->b[8] = pws->b[8]; +#else + pwd->b[0] = pwt->b[1]; + pwd->b[1] = pws->b[1]; + pwd->b[2] = pwt->b[3]; + pwd->b[3] = pws->b[3]; + pwd->b[4] = pwt->b[5]; + pwd->b[5] = pws->b[5]; + pwd->b[6] = pwt->b[7]; + pwd->b[7] = pws->b[7]; + pwd->b[8] = pwt->b[9]; + pwd->b[9] = pws->b[9]; + pwd->b[10] = pwt->b[11]; + pwd->b[11] = pws->b[11]; + pwd->b[12] = pwt->b[13]; + pwd->b[13] = pws->b[13]; + pwd->b[14] = pwt->b[15]; + pwd->b[15] = pws->b[15]; +#endif +} + +void helper_msa_ilvod_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] = pwt->h[2]; + pwd->h[2] = pws->h[2]; + pwd->h[1] = pwt->h[0]; + pwd->h[0] = pws->h[0]; + pwd->h[7] = pwt->h[6]; + pwd->h[6] = pws->h[6]; + pwd->h[5] = pwt->h[4]; + pwd->h[4] = pws->h[4]; +#else + pwd->h[0] = pwt->h[1]; + pwd->h[1] = pws->h[1]; + pwd->h[2] = pwt->h[3]; + pwd->h[3] = pws->h[3]; + pwd->h[4] = pwt->h[5]; + pwd->h[5] = pws->h[5]; + pwd->h[6] = pwt->h[7]; + pwd->h[7] = pws->h[7]; +#endif +} + +void helper_msa_ilvod_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] = pwt->w[0]; + pwd->w[0] = pws->w[0]; + pwd->w[3] = pwt->w[2]; + pwd->w[2] = pws->w[2]; +#else + pwd->w[0] = pwt->w[1]; + pwd->w[1] = pws->w[1]; + pwd->w[2] = pwt->w[3]; + pwd->w[3] = pws->w[3]; +#endif +} + +void helper_msa_ilvod_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = pwt->d[1]; + pwd->d[1] = pws->d[1]; +} + + +void helper_msa_ilvl_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] = pwt->b[15]; + pwd->b[6] = pws->b[15]; + pwd->b[5] = pwt->b[14]; + pwd->b[4] = pws->b[14]; + pwd->b[3] = pwt->b[13]; + pwd->b[2] = pws->b[13]; + pwd->b[1] = pwt->b[12]; + pwd->b[0] = pws->b[12]; + pwd->b[15] = pwt->b[11]; + pwd->b[14] = pws->b[11]; + pwd->b[13] = pwt->b[10]; + pwd->b[12] = pws->b[10]; + pwd->b[11] = pwt->b[9]; + pwd->b[10] = pws->b[9]; + pwd->b[9] = pwt->b[8]; + pwd->b[8] = pws->b[8]; +#else + pwd->b[0] = pwt->b[8]; + pwd->b[1] = pws->b[8]; + pwd->b[2] = pwt->b[9]; + pwd->b[3] = pws->b[9]; + pwd->b[4] = pwt->b[10]; + pwd->b[5] = pws->b[10]; + pwd->b[6] = pwt->b[11]; + pwd->b[7] = pws->b[11]; + pwd->b[8] = pwt->b[12]; + pwd->b[9] = pws->b[12]; + pwd->b[10] = pwt->b[13]; + pwd->b[11] = pws->b[13]; + pwd->b[12] = pwt->b[14]; + pwd->b[13] = pws->b[14]; + pwd->b[14] = pwt->b[15]; + pwd->b[15] = pws->b[15]; +#endif +} + +void helper_msa_ilvl_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] = pwt->h[7]; + pwd->h[2] = pws->h[7]; + pwd->h[1] = pwt->h[6]; + pwd->h[0] = pws->h[6]; + pwd->h[7] = pwt->h[5]; + pwd->h[6] = pws->h[5]; + pwd->h[5] = pwt->h[4]; + pwd->h[4] = pws->h[4]; +#else + pwd->h[0] = pwt->h[4]; + pwd->h[1] = pws->h[4]; + pwd->h[2] = pwt->h[5]; + pwd->h[3] = pws->h[5]; + pwd->h[4] = pwt->h[6]; + pwd->h[5] = pws->h[6]; + pwd->h[6] = pwt->h[7]; + pwd->h[7] = pws->h[7]; +#endif +} + +void helper_msa_ilvl_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] = pwt->w[3]; + pwd->w[0] = pws->w[3]; + pwd->w[3] = pwt->w[2]; + pwd->w[2] = pws->w[2]; +#else + pwd->w[0] = pwt->w[2]; + pwd->w[1] = pws->w[2]; + pwd->w[2] = pwt->w[3]; + pwd->w[3] = pws->w[3]; +#endif +} + +void helper_msa_ilvl_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = pwt->d[1]; + pwd->d[1] = pws->d[1]; +} + + +void helper_msa_ilvr_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] = pws->b[0]; + pwd->b[9] = pwt->b[0]; + pwd->b[10] = pws->b[1]; + pwd->b[11] = pwt->b[1]; + pwd->b[12] = pws->b[2]; + pwd->b[13] = pwt->b[2]; + pwd->b[14] = pws->b[3]; + pwd->b[15] = pwt->b[3]; + pwd->b[0] = pws->b[4]; + pwd->b[1] = pwt->b[4]; + pwd->b[2] = pws->b[5]; + pwd->b[3] = pwt->b[5]; + pwd->b[4] = pws->b[6]; + pwd->b[5] = pwt->b[6]; + pwd->b[6] = pws->b[7]; + pwd->b[7] = pwt->b[7]; +#else + pwd->b[15] = pws->b[7]; + pwd->b[14] = pwt->b[7]; + pwd->b[13] = pws->b[6]; + pwd->b[12] = pwt->b[6]; + pwd->b[11] = pws->b[5]; + pwd->b[10] = pwt->b[5]; + pwd->b[9] = pws->b[4]; + pwd->b[8] = pwt->b[4]; + pwd->b[7] = pws->b[3]; + pwd->b[6] = pwt->b[3]; + pwd->b[5] = pws->b[2]; + pwd->b[4] = pwt->b[2]; + pwd->b[3] = pws->b[1]; + pwd->b[2] = pwt->b[1]; + pwd->b[1] = pws->b[0]; + pwd->b[0] = pwt->b[0]; +#endif +} + +void helper_msa_ilvr_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] = pws->h[0]; + pwd->h[5] = pwt->h[0]; + pwd->h[6] = pws->h[1]; + pwd->h[7] = pwt->h[1]; + pwd->h[0] = pws->h[2]; + pwd->h[1] = pwt->h[2]; + pwd->h[2] = pws->h[3]; + pwd->h[3] = pwt->h[3]; +#else + pwd->h[7] = pws->h[3]; + pwd->h[6] = pwt->h[3]; + pwd->h[5] = pws->h[2]; + pwd->h[4] = pwt->h[2]; + pwd->h[3] = pws->h[1]; + pwd->h[2] = pwt->h[1]; + pwd->h[1] = pws->h[0]; + pwd->h[0] = pwt->h[0]; +#endif +} + +void helper_msa_ilvr_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] = pws->w[0]; + pwd->w[3] = pwt->w[0]; + pwd->w[0] = pws->w[1]; + pwd->w[1] = pwt->w[1]; +#else + pwd->w[3] = pws->w[1]; + pwd->w[2] = pwt->w[1]; + pwd->w[1] = pws->w[0]; + pwd->w[0] = pwt->w[0]; +#endif +} + +void helper_msa_ilvr_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[1] = pws->d[0]; + pwd->d[0] = pwt->d[0]; +} /* @@ -2096,7 +3715,214 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws) * +---------------+----------------------------------------------------------+ */ -/* TODO: insert Pack group helpers here */ + +void helper_msa_pckev_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] = pws->b[9]; + pwd->b[10] = pws->b[13]; + pwd->b[12] = pws->b[1]; + pwd->b[14] = pws->b[5]; + pwd->b[0] = pwt->b[9]; + pwd->b[2] = pwt->b[13]; + pwd->b[4] = pwt->b[1]; + pwd->b[6] = pwt->b[5]; + pwd->b[9] = pws->b[11]; + pwd->b[13] = pws->b[3]; + pwd->b[1] = pwt->b[11]; + pwd->b[5] = pwt->b[3]; + pwd->b[11] = pws->b[15]; + pwd->b[3] = pwt->b[15]; + pwd->b[15] = pws->b[7]; + pwd->b[7] = pwt->b[7]; +#else + pwd->b[15] = pws->b[14]; + pwd->b[13] = pws->b[10]; + pwd->b[11] = pws->b[6]; + pwd->b[9] = pws->b[2]; + pwd->b[7] = pwt->b[14]; + pwd->b[5] = pwt->b[10]; + pwd->b[3] = pwt->b[6]; + pwd->b[1] = pwt->b[2]; + pwd->b[14] = pws->b[12]; + pwd->b[10] = pws->b[4]; + pwd->b[6] = pwt->b[12]; + pwd->b[2] = pwt->b[4]; + pwd->b[12] = pws->b[8]; + pwd->b[4] = pwt->b[8]; + pwd->b[8] = pws->b[0]; + pwd->b[0] = pwt->b[0]; +#endif +} + +void helper_msa_pckev_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] = pws->h[5]; + pwd->h[6] = pws->h[1]; + pwd->h[0] = pwt->h[5]; + pwd->h[2] = pwt->h[1]; + pwd->h[5] = pws->h[7]; + pwd->h[1] = pwt->h[7]; + pwd->h[7] = pws->h[3]; + pwd->h[3] = pwt->h[3]; +#else + pwd->h[7] = pws->h[6]; + pwd->h[5] = pws->h[2]; + pwd->h[3] = pwt->h[6]; + pwd->h[1] = pwt->h[2]; + pwd->h[6] = pws->h[4]; + pwd->h[2] = pwt->h[4]; + pwd->h[4] = pws->h[0]; + pwd->h[0] = pwt->h[0]; +#endif +} + +void helper_msa_pckev_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] = pws->w[3]; + pwd->w[0] = pwt->w[3]; + pwd->w[3] = pws->w[1]; + pwd->w[1] = pwt->w[1]; +#else + pwd->w[3] = pws->w[2]; + pwd->w[1] = pwt->w[2]; + pwd->w[2] = pws->w[0]; + pwd->w[0] = pwt->w[0]; +#endif +} + +void helper_msa_pckev_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[1] = pws->d[0]; + pwd->d[0] = pwt->d[0]; +} + + +void helper_msa_pckod_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] = pwt->b[6]; + pwd->b[5] = pwt->b[2]; + pwd->b[3] = pwt->b[14]; + pwd->b[1] = pwt->b[10]; + pwd->b[15] = pws->b[6]; + pwd->b[13] = pws->b[2]; + pwd->b[11] = pws->b[14]; + pwd->b[9] = pws->b[10]; + pwd->b[6] = pwt->b[4]; + pwd->b[2] = pwt->b[12]; + pwd->b[14] = pws->b[4]; + pwd->b[10] = pws->b[12]; + pwd->b[4] = pwt->b[0]; + pwd->b[12] = pws->b[0]; + pwd->b[0] = pwt->b[8]; + pwd->b[8] = pws->b[8]; +#else + pwd->b[0] = pwt->b[1]; + pwd->b[2] = pwt->b[5]; + pwd->b[4] = pwt->b[9]; + pwd->b[6] = pwt->b[13]; + pwd->b[8] = pws->b[1]; + pwd->b[10] = pws->b[5]; + pwd->b[12] = pws->b[9]; + pwd->b[14] = pws->b[13]; + pwd->b[1] = pwt->b[3]; + pwd->b[5] = pwt->b[11]; + pwd->b[9] = pws->b[3]; + pwd->b[13] = pws->b[11]; + pwd->b[3] = pwt->b[7]; + pwd->b[11] = pws->b[7]; + pwd->b[7] = pwt->b[15]; + pwd->b[15] = pws->b[15]; +#endif + +} + +void helper_msa_pckod_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] = pwt->h[2]; + pwd->h[1] = pwt->h[6]; + pwd->h[7] = pws->h[2]; + pwd->h[5] = pws->h[6]; + pwd->h[2] = pwt->h[0]; + pwd->h[6] = pws->h[0]; + pwd->h[0] = pwt->h[4]; + pwd->h[4] = pws->h[4]; +#else + pwd->h[0] = pwt->h[1]; + pwd->h[2] = pwt->h[5]; + pwd->h[4] = pws->h[1]; + pwd->h[6] = pws->h[5]; + pwd->h[1] = pwt->h[3]; + pwd->h[5] = pws->h[3]; + pwd->h[3] = pwt->h[7]; + pwd->h[7] = pws->h[7]; +#endif +} + +void helper_msa_pckod_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] = pwt->w[0]; + pwd->w[3] = pws->w[0]; + pwd->w[0] = pwt->w[2]; + pwd->w[2] = pws->w[2]; +#else + pwd->w[0] = pwt->w[1]; + pwd->w[2] = pws->w[1]; + pwd->w[1] = pwt->w[3]; + pwd->w[3] = pws->w[3]; +#endif +} + +void helper_msa_pckod_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = pwt->d[1]; + pwd->d[1] = pws->d[1]; +} /* @@ -2127,7 +3953,382 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws) * +---------------+----------------------------------------------------------+ */ -/* TODO: insert Shift group helpers here */ + +static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 = BIT_POSITION(arg2, df); + return arg1 << b_arg2; +} + +void helper_msa_sll_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_sll_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_sll_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_sll_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_sll_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_sll_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_sll_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_sll_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_sll_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_sll_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_sll_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_sll_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_sll_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_sll_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_sll_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_sll_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_sll_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_sll_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_sll_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_sll_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_sll_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_sll_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_sll_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_sll_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_sll_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_sll_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_sll_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_sll_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_sll_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_sll_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_sll_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_sll_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_sll_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_sll_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 = BIT_POSITION(arg2, df); + return arg1 >> b_arg2; +} + +void helper_msa_sra_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_sra_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_sra_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_sra_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_sra_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_sra_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_sra_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_sra_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_sra_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_sra_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_sra_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_sra_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_sra_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_sra_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_sra_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_sra_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_sra_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_sra_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_sra_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_sra_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_sra_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_sra_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_sra_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_sra_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_sra_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_sra_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_sra_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_sra_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_sra_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_sra_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_sra_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_sra_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_sra_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_sra_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + int32_t b_arg2 = BIT_POSITION(arg2, df); + if (b_arg2 == 0) { + return arg1; + } else { + int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1; + return (arg1 >> b_arg2) + r_bit; + } +} + +void helper_msa_srar_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_srar_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_srar_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_srar_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_srar_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_srar_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_srar_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_srar_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_srar_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_srar_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_srar_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_srar_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_srar_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_srar_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_srar_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_srar_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_srar_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_srar_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_srar_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_srar_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_srar_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_srar_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_srar_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_srar_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_srar_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_srar_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_srar_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_srar_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_srar_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_srar_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_srar_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_srar_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_srar_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_srar_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 = UNSIGNED(arg1, df); + int32_t b_arg2 = BIT_POSITION(arg2, df); + return u_arg1 >> b_arg2; +} + +void helper_msa_srl_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_srl_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_srl_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_srl_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_srl_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_srl_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_srl_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_srl_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_srl_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_srl_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_srl_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_srl_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_srl_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_srl_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_srl_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_srl_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_srl_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_srl_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_srl_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_srl_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_srl_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_srl_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_srl_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_srl_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_srl_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_srl_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_srl_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_srl_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_srl_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_srl_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_srl_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_srl_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_srl_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_srl_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} + + +static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2) +{ + uint64_t u_arg1 = UNSIGNED(arg1, df); + int32_t b_arg2 = BIT_POSITION(arg2, df); + if (b_arg2 == 0) { + return u_arg1; + } else { + uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1; + return (u_arg1 >> b_arg2) + r_bit; + } +} + +void helper_msa_srlr_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] = msa_srlr_df(DF_BYTE, pws->b[0], pwt->b[0]); + pwd->b[1] = msa_srlr_df(DF_BYTE, pws->b[1], pwt->b[1]); + pwd->b[2] = msa_srlr_df(DF_BYTE, pws->b[2], pwt->b[2]); + pwd->b[3] = msa_srlr_df(DF_BYTE, pws->b[3], pwt->b[3]); + pwd->b[4] = msa_srlr_df(DF_BYTE, pws->b[4], pwt->b[4]); + pwd->b[5] = msa_srlr_df(DF_BYTE, pws->b[5], pwt->b[5]); + pwd->b[6] = msa_srlr_df(DF_BYTE, pws->b[6], pwt->b[6]); + pwd->b[7] = msa_srlr_df(DF_BYTE, pws->b[7], pwt->b[7]); + pwd->b[8] = msa_srlr_df(DF_BYTE, pws->b[8], pwt->b[8]); + pwd->b[9] = msa_srlr_df(DF_BYTE, pws->b[9], pwt->b[9]); + pwd->b[10] = msa_srlr_df(DF_BYTE, pws->b[10], pwt->b[10]); + pwd->b[11] = msa_srlr_df(DF_BYTE, pws->b[11], pwt->b[11]); + pwd->b[12] = msa_srlr_df(DF_BYTE, pws->b[12], pwt->b[12]); + pwd->b[13] = msa_srlr_df(DF_BYTE, pws->b[13], pwt->b[13]); + pwd->b[14] = msa_srlr_df(DF_BYTE, pws->b[14], pwt->b[14]); + pwd->b[15] = msa_srlr_df(DF_BYTE, pws->b[15], pwt->b[15]); +} + +void helper_msa_srlr_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] = msa_srlr_df(DF_HALF, pws->h[0], pwt->h[0]); + pwd->h[1] = msa_srlr_df(DF_HALF, pws->h[1], pwt->h[1]); + pwd->h[2] = msa_srlr_df(DF_HALF, pws->h[2], pwt->h[2]); + pwd->h[3] = msa_srlr_df(DF_HALF, pws->h[3], pwt->h[3]); + pwd->h[4] = msa_srlr_df(DF_HALF, pws->h[4], pwt->h[4]); + pwd->h[5] = msa_srlr_df(DF_HALF, pws->h[5], pwt->h[5]); + pwd->h[6] = msa_srlr_df(DF_HALF, pws->h[6], pwt->h[6]); + pwd->h[7] = msa_srlr_df(DF_HALF, pws->h[7], pwt->h[7]); +} + +void helper_msa_srlr_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] = msa_srlr_df(DF_WORD, pws->w[0], pwt->w[0]); + pwd->w[1] = msa_srlr_df(DF_WORD, pws->w[1], pwt->w[1]); + pwd->w[2] = msa_srlr_df(DF_WORD, pws->w[2], pwt->w[2]); + pwd->w[3] = msa_srlr_df(DF_WORD, pws->w[3], pwt->w[3]); +} + +void helper_msa_srlr_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); + wr_t *pws = &(env->active_fpu.fpr[ws].wr); + wr_t *pwt = &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] = msa_srlr_df(DF_DOUBLE, pws->d[0], pwt->d[0]); + pwd->d[1] = msa_srlr_df(DF_DOUBLE, pws->d[1], pwt->d[1]); +} #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \ @@ -2199,40 +4400,11 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, msa_move_v(pwd, pwx); } -static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 + arg2; -} - static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 - arg2; } -static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 > arg2 ? arg1 : arg2; -} - -static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 = UNSIGNED(arg1, df); - uint64_t u_arg2 = UNSIGNED(arg2, df); - return u_arg1 > u_arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return arg1 < arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 = UNSIGNED(arg1, df); - uint64_t u_arg2 = UNSIGNED(arg2, df); - return u_arg1 < u_arg2 ? arg1 : arg2; -} - #define MSA_BINOP_IMM_DF(helper, func) \ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ uint32_t wd, uint32_t ws, int32_t u5) \ @@ -2312,25 +4484,6 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } } -static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 = BIT_POSITION(arg2, df); - return arg1 << b_arg2; -} - -static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 = BIT_POSITION(arg2, df); - return arg1 >> b_arg2; -} - -static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 = UNSIGNED(arg1, df); - int32_t b_arg2 = BIT_POSITION(arg2, df); - return u_arg1 >> b_arg2; -} - static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m) { return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) : @@ -2345,29 +4498,6 @@ static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m) M_MAX_UINT(m + 1); } -static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int32_t b_arg2 = BIT_POSITION(arg2, df); - if (b_arg2 == 0) { - return arg1; - } else { - int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1; - return (arg1 >> b_arg2) + r_bit; - } -} - -static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t u_arg1 = UNSIGNED(arg1, df); - int32_t b_arg2 = BIT_POSITION(arg2, df); - if (b_arg2 == 0) { - return u_arg1; - } else { - uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1; - return (u_arg1 >> b_arg2) + r_bit; - } -} - #define MSA_BINOP_IMMU_DF(helper, func) \ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \ uint32_t ws, uint32_t u5) \ @@ -2456,58 +4586,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl) MSA_TEROP_IMMU_DF(binsri, binsr) #undef MSA_TEROP_IMMU_DF -static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; - uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; - return abs_arg1 > abs_arg2 ? arg1 : arg2; -} - -static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; - uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; - return abs_arg1 < abs_arg2 ? arg1 : arg2; -} - -static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; - uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; - return abs_arg1 + abs_arg2; -} - -static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - uint64_t max_int = (uint64_t)DF_MAX_INT(df); - uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; - uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; - if (abs_arg1 > max_int || abs_arg2 > max_int) { - return (int64_t)max_int; - } else { - return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int; - } -} - -static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - int64_t max_int = DF_MAX_INT(df); - int64_t min_int = DF_MIN_INT(df); - if (arg1 < 0) { - return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int; - } else { - return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int; - } -} - -static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) -{ - uint64_t max_uint = DF_MAX_UINT(df); - uint64_t u_arg1 = UNSIGNED(arg1, df); - uint64_t u_arg2 = UNSIGNED(arg2, df); - return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; -} - static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2) { int64_t max_int = DF_MAX_INT(df); @@ -2560,39 +4638,11 @@ static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2) } } -static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - /* signed compare */ - return (arg1 < arg2) ? - (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2); -} - -static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) -{ - uint64_t u_arg1 = UNSIGNED(arg1, df); - uint64_t u_arg2 = UNSIGNED(arg2, df); - /* unsigned compare */ - return (u_arg1 < u_arg2) ? - (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2); -} - static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2) { return arg1 * arg2; } -#define SIGNED_EVEN(a, df) \ - ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2)) - -#define UNSIGNED_EVEN(a, df) \ - ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2)) - -#define SIGNED_ODD(a, df) \ - ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) - -#define UNSIGNED_ODD(a, df) \ - ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) - #define SIGNED_EXTRACT(e, o, a, df) \ do { \ e = SIGNED_EVEN(a, df); \ @@ -2669,26 +4719,6 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd, } } -static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df); -} - -static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df); -} - -static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df); -} - -static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2) -{ - return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df); -} - static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2) { int64_t q_min = DF_MIN_INT(df); @@ -2764,36 +4794,14 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \ } \ } -MSA_BINOP_DF(sll) -MSA_BINOP_DF(sra) -MSA_BINOP_DF(srl) -MSA_BINOP_DF(addv) MSA_BINOP_DF(subv) -MSA_BINOP_DF(max_s) -MSA_BINOP_DF(max_u) -MSA_BINOP_DF(min_s) -MSA_BINOP_DF(min_u) -MSA_BINOP_DF(max_a) -MSA_BINOP_DF(min_a) -MSA_BINOP_DF(add_a) -MSA_BINOP_DF(adds_a) -MSA_BINOP_DF(adds_s) -MSA_BINOP_DF(adds_u) MSA_BINOP_DF(subs_s) MSA_BINOP_DF(subs_u) MSA_BINOP_DF(subsus_u) MSA_BINOP_DF(subsuu_s) -MSA_BINOP_DF(asub_s) -MSA_BINOP_DF(asub_u) MSA_BINOP_DF(mulv) MSA_BINOP_DF(dotp_s) MSA_BINOP_DF(dotp_u) -MSA_BINOP_DF(srar) -MSA_BINOP_DF(srlr) -MSA_BINOP_DF(hadd_s) -MSA_BINOP_DF(hadd_u) -MSA_BINOP_DF(hsub_s) -MSA_BINOP_DF(hsub_u) MSA_BINOP_DF(mul_q) MSA_BINOP_DF(mulr_q) @@ -3129,535 +5137,6 @@ MSA_FN_DF(vshf_df) #undef MSA_FN_DF -void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - wr_t *pws = &(env->active_fpu.fpr[ws].wr); - wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[8] = pws->b[9]; - pwd->b[9] = pwt->b[9]; - pwd->b[10] = pws->b[11]; - pwd->b[11] = pwt->b[11]; - pwd->b[12] = pws->b[13]; - pwd->b[13] = pwt->b[13]; - pwd->b[14] = pws->b[15]; - pwd->b[15] = pwt->b[15]; - pwd->b[0] = pws->b[1]; - pwd->b[1] = pwt->b[1]; - pwd->b[2] = pws->b[3]; - pwd->b[3] = pwt->b[3]; - pwd->b[4] = pws->b[5]; - pwd->b[5] = pwt->b[5]; - pwd->b[6] = pws->b[7]; - pwd->b[7] = pwt->b[7]; -#else - pwd->b[15] = pws->b[14]; - pwd->b[14] = pwt->b[14]; - pwd->b[13] = pws->b[12]; - pwd->b[12] = pwt->b[12]; - pwd->b[11] = pws->b[10]; - pwd->b[10] = pwt->b[10]; - pwd->b[9] = pws->b[8]; - pwd->b[8] = pwt->b[8]; - pwd->b[7] = pws->b[6]; - pwd->b[6] = pwt->b[6]; - pwd->b[5] = pws->b[4]; - pwd->b[4] = pwt->b[4]; - pwd->b[3] = pws->b[2]; - pwd->b[2] = pwt->b[2]; - pwd->b[1] = pws->b[0]; - pwd->b[0] = pwt->b[0]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[4] = pws->h[5]; - pwd->h[5] = pwt->h[5]; - pwd->h[6] = pws->h[7]; - pwd->h[7] = pwt->h[7]; - pwd->h[0] = pws->h[1]; - pwd->h[1] = pwt->h[1]; - pwd->h[2] = pws->h[3]; - pwd->h[3] = pwt->h[3]; -#else - pwd->h[7] = pws->h[6]; - pwd->h[6] = pwt->h[6]; - pwd->h[5] = pws->h[4]; - pwd->h[4] = pwt->h[4]; - pwd->h[3] = pws->h[2]; - pwd->h[2] = pwt->h[2]; - pwd->h[1] = pws->h[0]; - pwd->h[0] = pwt->h[0]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[2] = pws->w[3]; - pwd->w[3] = pwt->w[3]; - pwd->w[0] = pws->w[1]; - pwd->w[1] = pwt->w[1]; -#else - pwd->w[3] = pws->w[2]; - pwd->w[2] = pwt->w[2]; - pwd->w[1] = pws->w[0]; - pwd->w[0] = pwt->w[0]; -#endif - break; - case DF_DOUBLE: - pwd->d[1] = pws->d[0]; - pwd->d[0] = pwt->d[0]; - break; - default: - assert(0); - } -} - -void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - wr_t *pws = &(env->active_fpu.fpr[ws].wr); - wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[7] = pwt->b[6]; - pwd->b[6] = pws->b[6]; - pwd->b[5] = pwt->b[4]; - pwd->b[4] = pws->b[4]; - pwd->b[3] = pwt->b[2]; - pwd->b[2] = pws->b[2]; - pwd->b[1] = pwt->b[0]; - pwd->b[0] = pws->b[0]; - pwd->b[15] = pwt->b[14]; - pwd->b[14] = pws->b[14]; - pwd->b[13] = pwt->b[12]; - pwd->b[12] = pws->b[12]; - pwd->b[11] = pwt->b[10]; - pwd->b[10] = pws->b[10]; - pwd->b[9] = pwt->b[8]; - pwd->b[8] = pws->b[8]; -#else - pwd->b[0] = pwt->b[1]; - pwd->b[1] = pws->b[1]; - pwd->b[2] = pwt->b[3]; - pwd->b[3] = pws->b[3]; - pwd->b[4] = pwt->b[5]; - pwd->b[5] = pws->b[5]; - pwd->b[6] = pwt->b[7]; - pwd->b[7] = pws->b[7]; - pwd->b[8] = pwt->b[9]; - pwd->b[9] = pws->b[9]; - pwd->b[10] = pwt->b[11]; - pwd->b[11] = pws->b[11]; - pwd->b[12] = pwt->b[13]; - pwd->b[13] = pws->b[13]; - pwd->b[14] = pwt->b[15]; - pwd->b[15] = pws->b[15]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[3] = pwt->h[2]; - pwd->h[2] = pws->h[2]; - pwd->h[1] = pwt->h[0]; - pwd->h[0] = pws->h[0]; - pwd->h[7] = pwt->h[6]; - pwd->h[6] = pws->h[6]; - pwd->h[5] = pwt->h[4]; - pwd->h[4] = pws->h[4]; -#else - pwd->h[0] = pwt->h[1]; - pwd->h[1] = pws->h[1]; - pwd->h[2] = pwt->h[3]; - pwd->h[3] = pws->h[3]; - pwd->h[4] = pwt->h[5]; - pwd->h[5] = pws->h[5]; - pwd->h[6] = pwt->h[7]; - pwd->h[7] = pws->h[7]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[1] = pwt->w[0]; - pwd->w[0] = pws->w[0]; - pwd->w[3] = pwt->w[2]; - pwd->w[2] = pws->w[2]; -#else - pwd->w[0] = pwt->w[1]; - pwd->w[1] = pws->w[1]; - pwd->w[2] = pwt->w[3]; - pwd->w[3] = pws->w[3]; -#endif - break; - case DF_DOUBLE: - pwd->d[0] = pwt->d[1]; - pwd->d[1] = pws->d[1]; - break; - default: - assert(0); - } -} - -void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - wr_t *pws = &(env->active_fpu.fpr[ws].wr); - wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[7] = pwt->b[15]; - pwd->b[6] = pws->b[15]; - pwd->b[5] = pwt->b[14]; - pwd->b[4] = pws->b[14]; - pwd->b[3] = pwt->b[13]; - pwd->b[2] = pws->b[13]; - pwd->b[1] = pwt->b[12]; - pwd->b[0] = pws->b[12]; - pwd->b[15] = pwt->b[11]; - pwd->b[14] = pws->b[11]; - pwd->b[13] = pwt->b[10]; - pwd->b[12] = pws->b[10]; - pwd->b[11] = pwt->b[9]; - pwd->b[10] = pws->b[9]; - pwd->b[9] = pwt->b[8]; - pwd->b[8] = pws->b[8]; -#else - pwd->b[0] = pwt->b[8]; - pwd->b[1] = pws->b[8]; - pwd->b[2] = pwt->b[9]; - pwd->b[3] = pws->b[9]; - pwd->b[4] = pwt->b[10]; - pwd->b[5] = pws->b[10]; - pwd->b[6] = pwt->b[11]; - pwd->b[7] = pws->b[11]; - pwd->b[8] = pwt->b[12]; - pwd->b[9] = pws->b[12]; - pwd->b[10] = pwt->b[13]; - pwd->b[11] = pws->b[13]; - pwd->b[12] = pwt->b[14]; - pwd->b[13] = pws->b[14]; - pwd->b[14] = pwt->b[15]; - pwd->b[15] = pws->b[15]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[3] = pwt->h[7]; - pwd->h[2] = pws->h[7]; - pwd->h[1] = pwt->h[6]; - pwd->h[0] = pws->h[6]; - pwd->h[7] = pwt->h[5]; - pwd->h[6] = pws->h[5]; - pwd->h[5] = pwt->h[4]; - pwd->h[4] = pws->h[4]; -#else - pwd->h[0] = pwt->h[4]; - pwd->h[1] = pws->h[4]; - pwd->h[2] = pwt->h[5]; - pwd->h[3] = pws->h[5]; - pwd->h[4] = pwt->h[6]; - pwd->h[5] = pws->h[6]; - pwd->h[6] = pwt->h[7]; - pwd->h[7] = pws->h[7]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[1] = pwt->w[3]; - pwd->w[0] = pws->w[3]; - pwd->w[3] = pwt->w[2]; - pwd->w[2] = pws->w[2]; -#else - pwd->w[0] = pwt->w[2]; - pwd->w[1] = pws->w[2]; - pwd->w[2] = pwt->w[3]; - pwd->w[3] = pws->w[3]; -#endif - break; - case DF_DOUBLE: - pwd->d[0] = pwt->d[1]; - pwd->d[1] = pws->d[1]; - break; - default: - assert(0); - } -} - -void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - wr_t *pws = &(env->active_fpu.fpr[ws].wr); - wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[8] = pws->b[0]; - pwd->b[9] = pwt->b[0]; - pwd->b[10] = pws->b[1]; - pwd->b[11] = pwt->b[1]; - pwd->b[12] = pws->b[2]; - pwd->b[13] = pwt->b[2]; - pwd->b[14] = pws->b[3]; - pwd->b[15] = pwt->b[3]; - pwd->b[0] = pws->b[4]; - pwd->b[1] = pwt->b[4]; - pwd->b[2] = pws->b[5]; - pwd->b[3] = pwt->b[5]; - pwd->b[4] = pws->b[6]; - pwd->b[5] = pwt->b[6]; - pwd->b[6] = pws->b[7]; - pwd->b[7] = pwt->b[7]; -#else - pwd->b[15] = pws->b[7]; - pwd->b[14] = pwt->b[7]; - pwd->b[13] = pws->b[6]; - pwd->b[12] = pwt->b[6]; - pwd->b[11] = pws->b[5]; - pwd->b[10] = pwt->b[5]; - pwd->b[9] = pws->b[4]; - pwd->b[8] = pwt->b[4]; - pwd->b[7] = pws->b[3]; - pwd->b[6] = pwt->b[3]; - pwd->b[5] = pws->b[2]; - pwd->b[4] = pwt->b[2]; - pwd->b[3] = pws->b[1]; - pwd->b[2] = pwt->b[1]; - pwd->b[1] = pws->b[0]; - pwd->b[0] = pwt->b[0]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[4] = pws->h[0]; - pwd->h[5] = pwt->h[0]; - pwd->h[6] = pws->h[1]; - pwd->h[7] = pwt->h[1]; - pwd->h[0] = pws->h[2]; - pwd->h[1] = pwt->h[2]; - pwd->h[2] = pws->h[3]; - pwd->h[3] = pwt->h[3]; -#else - pwd->h[7] = pws->h[3]; - pwd->h[6] = pwt->h[3]; - pwd->h[5] = pws->h[2]; - pwd->h[4] = pwt->h[2]; - pwd->h[3] = pws->h[1]; - pwd->h[2] = pwt->h[1]; - pwd->h[1] = pws->h[0]; - pwd->h[0] = pwt->h[0]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[2] = pws->w[0]; - pwd->w[3] = pwt->w[0]; - pwd->w[0] = pws->w[1]; - pwd->w[1] = pwt->w[1]; -#else - pwd->w[3] = pws->w[1]; - pwd->w[2] = pwt->w[1]; - pwd->w[1] = pws->w[0]; - pwd->w[0] = pwt->w[0]; -#endif - break; - case DF_DOUBLE: - pwd->d[1] = pws->d[0]; - pwd->d[0] = pwt->d[0]; - break; - default: - assert(0); - } -} - -void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - wr_t *pws = &(env->active_fpu.fpr[ws].wr); - wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[8] = pws->b[9]; - pwd->b[10] = pws->b[13]; - pwd->b[12] = pws->b[1]; - pwd->b[14] = pws->b[5]; - pwd->b[0] = pwt->b[9]; - pwd->b[2] = pwt->b[13]; - pwd->b[4] = pwt->b[1]; - pwd->b[6] = pwt->b[5]; - pwd->b[9] = pws->b[11]; - pwd->b[13] = pws->b[3]; - pwd->b[1] = pwt->b[11]; - pwd->b[5] = pwt->b[3]; - pwd->b[11] = pws->b[15]; - pwd->b[3] = pwt->b[15]; - pwd->b[15] = pws->b[7]; - pwd->b[7] = pwt->b[7]; -#else - pwd->b[15] = pws->b[14]; - pwd->b[13] = pws->b[10]; - pwd->b[11] = pws->b[6]; - pwd->b[9] = pws->b[2]; - pwd->b[7] = pwt->b[14]; - pwd->b[5] = pwt->b[10]; - pwd->b[3] = pwt->b[6]; - pwd->b[1] = pwt->b[2]; - pwd->b[14] = pws->b[12]; - pwd->b[10] = pws->b[4]; - pwd->b[6] = pwt->b[12]; - pwd->b[2] = pwt->b[4]; - pwd->b[12] = pws->b[8]; - pwd->b[4] = pwt->b[8]; - pwd->b[8] = pws->b[0]; - pwd->b[0] = pwt->b[0]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[4] = pws->h[5]; - pwd->h[6] = pws->h[1]; - pwd->h[0] = pwt->h[5]; - pwd->h[2] = pwt->h[1]; - pwd->h[5] = pws->h[7]; - pwd->h[1] = pwt->h[7]; - pwd->h[7] = pws->h[3]; - pwd->h[3] = pwt->h[3]; -#else - pwd->h[7] = pws->h[6]; - pwd->h[5] = pws->h[2]; - pwd->h[3] = pwt->h[6]; - pwd->h[1] = pwt->h[2]; - pwd->h[6] = pws->h[4]; - pwd->h[2] = pwt->h[4]; - pwd->h[4] = pws->h[0]; - pwd->h[0] = pwt->h[0]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[2] = pws->w[3]; - pwd->w[0] = pwt->w[3]; - pwd->w[3] = pws->w[1]; - pwd->w[1] = pwt->w[1]; -#else - pwd->w[3] = pws->w[2]; - pwd->w[1] = pwt->w[2]; - pwd->w[2] = pws->w[0]; - pwd->w[0] = pwt->w[0]; -#endif - break; - case DF_DOUBLE: - pwd->d[1] = pws->d[0]; - pwd->d[0] = pwt->d[0]; - break; - default: - assert(0); - } -} - -void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, - uint32_t ws, uint32_t wt) -{ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - wr_t *pws = &(env->active_fpu.fpr[ws].wr); - wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - - switch (df) { - case DF_BYTE: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->b[7] = pwt->b[6]; - pwd->b[5] = pwt->b[2]; - pwd->b[3] = pwt->b[14]; - pwd->b[1] = pwt->b[10]; - pwd->b[15] = pws->b[6]; - pwd->b[13] = pws->b[2]; - pwd->b[11] = pws->b[14]; - pwd->b[9] = pws->b[10]; - pwd->b[6] = pwt->b[4]; - pwd->b[2] = pwt->b[12]; - pwd->b[14] = pws->b[4]; - pwd->b[10] = pws->b[12]; - pwd->b[4] = pwt->b[0]; - pwd->b[12] = pws->b[0]; - pwd->b[0] = pwt->b[8]; - pwd->b[8] = pws->b[8]; -#else - pwd->b[0] = pwt->b[1]; - pwd->b[2] = pwt->b[5]; - pwd->b[4] = pwt->b[9]; - pwd->b[6] = pwt->b[13]; - pwd->b[8] = pws->b[1]; - pwd->b[10] = pws->b[5]; - pwd->b[12] = pws->b[9]; - pwd->b[14] = pws->b[13]; - pwd->b[1] = pwt->b[3]; - pwd->b[5] = pwt->b[11]; - pwd->b[9] = pws->b[3]; - pwd->b[13] = pws->b[11]; - pwd->b[3] = pwt->b[7]; - pwd->b[11] = pws->b[7]; - pwd->b[7] = pwt->b[15]; - pwd->b[15] = pws->b[15]; -#endif - break; - case DF_HALF: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->h[3] = pwt->h[2]; - pwd->h[1] = pwt->h[6]; - pwd->h[7] = pws->h[2]; - pwd->h[5] = pws->h[6]; - pwd->h[2] = pwt->h[0]; - pwd->h[6] = pws->h[0]; - pwd->h[0] = pwt->h[4]; - pwd->h[4] = pws->h[4]; -#else - pwd->h[0] = pwt->h[1]; - pwd->h[2] = pwt->h[5]; - pwd->h[4] = pws->h[1]; - pwd->h[6] = pws->h[5]; - pwd->h[1] = pwt->h[3]; - pwd->h[5] = pws->h[3]; - pwd->h[3] = pwt->h[7]; - pwd->h[7] = pws->h[7]; -#endif - break; - case DF_WORD: -#if defined(HOST_WORDS_BIGENDIAN) - pwd->w[1] = pwt->w[0]; - pwd->w[3] = pws->w[0]; - pwd->w[0] = pwt->w[2]; - pwd->w[2] = pws->w[2]; -#else - pwd->w[0] = pwt->w[1]; - pwd->w[2] = pws->w[1]; - pwd->w[1] = pwt->w[3]; - pwd->w[3] = pws->w[3]; -#endif - break; - case DF_DOUBLE: - pwd->d[0] = pwt->d[1]; - pwd->d[1] = pws->d[1]; - break; - default: - assert(0); - } -} - - void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t ws, uint32_t n) { diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 4de64657ef..18fcee4a78 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -64,8 +64,7 @@ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ int mem_idx, uintptr_t retaddr) \ { \ - switch (mem_idx) \ - { \ + switch (mem_idx) { \ case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \ case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \ default: \ @@ -92,12 +91,17 @@ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ type val, int mem_idx, uintptr_t retaddr) \ { \ - switch (mem_idx) \ - { \ - case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \ - case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \ + switch (mem_idx) { \ + case 0: \ + cpu_##insn##_kernel_ra(env, addr, val, retaddr); \ + break; \ + case 1: \ + cpu_##insn##_super_ra(env, addr, val, retaddr); \ + break; \ default: \ - case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \ + case 2: \ + cpu_##insn##_user_ra(env, addr, val, retaddr); \ + break; \ case 3: \ cpu_##insn##_error_ra(env, addr, val, retaddr); \ break; \ @@ -114,7 +118,8 @@ HELPER_ST(sd, stq, uint64_t) /* 64 bits arithmetic for 32 bits hosts */ static inline uint64_t get_HILO(CPUMIPSState *env) { - return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; + return ((uint64_t)(env->active_tc.HI[0]) << 32) | + (uint32_t)env->active_tc.LO[0]; } static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) @@ -435,9 +440,10 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, } #if defined(TARGET_MIPS64) -/* "half" load and stores. We must do the memory access inline, - or fault handling won't work. */ - +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ #ifdef TARGET_WORDS_BIGENDIAN #define GET_LMASK64(v) ((v) & 7) #else @@ -535,7 +541,7 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { @@ -557,7 +563,7 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { @@ -579,7 +585,7 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { @@ -600,7 +606,7 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { @@ -623,8 +629,10 @@ static bool mips_vpe_is_wfi(MIPSCPU *c) CPUState *cpu = CPU(c); CPUMIPSState *env = &c->env; - /* If the VPE is halted but otherwise active, it means it's waiting for - an interrupt. */ + /* + * If the VPE is halted but otherwise active, it means it's waiting for + * an interrupt.\ + */ return cpu->halted && mips_vpe_active(env); } @@ -638,9 +646,11 @@ static bool mips_vp_is_wfi(MIPSCPU *c) static inline void mips_vpe_wake(MIPSCPU *c) { - /* Don't set ->halted = 0 directly, let it be done via cpu_has_work - because there might be other conditions that state that c should - be sleeping. */ + /* + * Don't set ->halted = 0 directly, let it be done via cpu_has_work + * because there might be other conditions that state that c should + * be sleeping. + */ qemu_mutex_lock_iothread(); cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); qemu_mutex_unlock_iothread(); @@ -650,8 +660,10 @@ static inline void mips_vpe_sleep(MIPSCPU *cpu) { CPUState *cs = CPU(cpu); - /* The VPE was shut off, really go to bed. - Reset any old _WAKE requests. */ + /* + * The VPE was shut off, really go to bed. + * Reset any old _WAKE requests. + */ cs->halted = 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); } @@ -684,9 +696,12 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) * This function will transform @tc into a local index within the * returned #CPUMIPSState. */ -/* FIXME: This code assumes that all VPEs have the same number of TCs, - which depends on runtime setup. Can probably be fixed by - walking the list of CPUMIPSStates. */ + +/* + * FIXME: This code assumes that all VPEs have the same number of TCs, + * which depends on runtime setup. Can probably be fixed by + * walking the list of CPUMIPSStates. + */ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) { MIPSCPU *cpu; @@ -712,17 +727,21 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) return &cpu->env; } -/* The per VPE CP0_Status register shares some fields with the per TC - CP0_TCStatus registers. These fields are wired to the same registers, - so changes to either of them should be reflected on both registers. - - Also, EntryHi shares the bottom 8 bit ASID with TCStauts. - - These helper call synchronizes the regs for a given cpu. */ +/* + * The per VPE CP0_Status register shares some fields with the per TC + * CP0_TCStatus registers. These fields are wired to the same registers, + * so changes to either of them should be reflected on both registers. + * + * Also, EntryHi shares the bottom 8 bit ASID with TCStauts. + * + * These helper call synchronizes the regs for a given cpu. + */ -/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */ -/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, - int tc); */ +/* + * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. + * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, + * int tc); + */ /* Called for updates to CP0_TCStatus. */ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, @@ -805,10 +824,11 @@ target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.CP0_TCStatus; - else + } else { return other->tcs[other_tc].CP0_TCStatus; + } } target_ulong helper_mfc0_tcbind(CPUMIPSState *env) @@ -821,10 +841,11 @@ target_ulong helper_mftc0_tcbind(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.CP0_TCBind; - else + } else { return other->tcs[other_tc].CP0_TCBind; + } } target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) @@ -837,10 +858,11 @@ target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.PC; - else + } else { return other->tcs[other_tc].PC; + } } target_ulong helper_mfc0_tchalt(CPUMIPSState *env) @@ -853,10 +875,11 @@ target_ulong helper_mftc0_tchalt(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.CP0_TCHalt; - else + } else { return other->tcs[other_tc].CP0_TCHalt; + } } target_ulong helper_mfc0_tccontext(CPUMIPSState *env) @@ -869,10 +892,11 @@ target_ulong helper_mftc0_tccontext(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.CP0_TCContext; - else + } else { return other->tcs[other_tc].CP0_TCContext; + } } target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) @@ -885,10 +909,11 @@ target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.CP0_TCSchedule; - else + } else { return other->tcs[other_tc].CP0_TCSchedule; + } } target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) @@ -901,10 +926,11 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.CP0_TCScheFBack; - else + } else { return other->tcs[other_tc].CP0_TCScheFBack; + } } target_ulong helper_mfc0_count(CPUMIPSState *env) @@ -987,8 +1013,9 @@ target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) target_ulong helper_mfc0_debug(CPUMIPSState *env) { target_ulong t0 = env->CP0_Debug; - if (env->hflags & MIPS_HFLAG_DM) + if (env->hflags & MIPS_HFLAG_DM) { t0 |= 1 << CP0DB_DM; + } return t0; } @@ -999,10 +1026,11 @@ target_ulong helper_mftc0_debug(CPUMIPSState *env) int32_t tcstatus; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { tcstatus = other->active_tc.CP0_Debug_tcstatus; - else + } else { tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; + } /* XXX: Might be wrong, check with EJTAG spec. */ return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | @@ -1076,14 +1104,16 @@ void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) uint32_t mask = 0; uint32_t newval; - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | (1 << CP0MVPCo_EVP); - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + } + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (1 << CP0MVPCo_STLB); + } newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); - // TODO: Enable/disable shared TLB, enable/disable VPEs. + /* TODO: Enable/disable shared TLB, enable/disable VPEs. */ env->mvp->CP0_MVPControl = newval; } @@ -1097,10 +1127,12 @@ void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); - /* Yield scheduler intercept not implemented. */ - /* Gating storage scheduler intercept not implemented. */ + /* + * Yield scheduler intercept not implemented. + * Gating storage scheduler intercept not implemented. + */ - // TODO: Enable/disable TCs. + /* TODO: Enable/disable TCs. */ env->CP0_VPEControl = newval; } @@ -1143,13 +1175,14 @@ void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) uint32_t newval; if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { mask |= (0xff << CP0VPEC0_XTC); + } mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); } newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); - // TODO: TC exclusive handling due to ERL/EXL. + /* TODO: TC exclusive handling due to ERL/EXL. */ env->CP0_VPEConf0 = newval; } @@ -1181,7 +1214,7 @@ void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) /* UDI not implemented. */ /* CP2 not implemented. */ - // TODO: Handle FPU (CP1) binding. + /* TODO: Handle FPU (CP1) binding. */ env->CP0_VPEConf1 = newval; } @@ -1233,10 +1266,11 @@ void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.CP0_TCStatus = arg1; - else + } else { other->tcs[other_tc].CP0_TCStatus = arg1; + } sync_c0_tcstatus(other, other_tc, arg1); } @@ -1245,8 +1279,9 @@ void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) uint32_t mask = (1 << CP0TCBd_TBE); uint32_t newval; - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (1 << CP0TCBd_CurVPE); + } newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); env->active_tc.CP0_TCBind = newval; } @@ -1258,8 +1293,9 @@ void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) uint32_t newval; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { mask |= (1 << CP0TCBd_CurVPE); + } if (other_tc == other->current_tc) { newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); other->active_tc.CP0_TCBind = newval; @@ -1304,7 +1340,7 @@ void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) env->active_tc.CP0_TCHalt = arg1 & 0x1; - // TODO: Halt TC / Restart (if allocated+active) TC. + /* TODO: Halt TC / Restart (if allocated+active) TC. */ if (env->active_tc.CP0_TCHalt & 1) { mips_tc_sleep(cpu, env->current_tc); } else { @@ -1318,12 +1354,13 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); MIPSCPU *other_cpu = env_archcpu(other); - // TODO: Halt TC / Restart (if allocated+active) TC. + /* TODO: Halt TC / Restart (if allocated+active) TC. */ - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.CP0_TCHalt = arg1; - else + } else { other->tcs[other_tc].CP0_TCHalt = arg1; + } if (arg1 & 1) { mips_tc_sleep(other_cpu, other_tc); @@ -1342,10 +1379,11 @@ void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.CP0_TCContext = arg1; - else + } else { other->tcs[other_tc].CP0_TCContext = arg1; + } } void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) @@ -1358,10 +1396,11 @@ void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.CP0_TCSchedule = arg1; - else + } else { other->tcs[other_tc].CP0_TCSchedule = arg1; + } } void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) @@ -1374,10 +1413,11 @@ void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.CP0_TCScheFBack = arg1; - else + } else { other->tcs[other_tc].CP0_TCScheFBack = arg1; + } } void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) @@ -1703,9 +1743,15 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) case 3: qemu_log(", ERL\n"); break; - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; - case MIPS_HFLAG_KM: qemu_log("\n"); break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; default: cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; @@ -1860,21 +1906,26 @@ void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1) { int index = arg1 & 0x3f; if (index == 0x3f) { - /* Software may write all ones to INDEX to determine the - maximum value supported. */ + /* + * Software may write all ones to INDEX to determine the + * maximum value supported. + */ env->CP0_MAARI = MIPS_MAAR_MAX - 1; } else if (index < MIPS_MAAR_MAX) { env->CP0_MAARI = index; } - /* Other than the all ones, if the - value written is not supported, then INDEX is unchanged - from its previous value. */ + /* + * Other than the all ones, if the value written is not supported, + * then INDEX is unchanged from its previous value. + */ } void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { - /* Watch exceptions for instructions, data loads, data stores - not implemented. */ + /* + * Watch exceptions for instructions, data loads, data stores + * not implemented. + */ env->CP0_WatchLo[sel] = (arg1 & ~0x7); } @@ -1899,10 +1950,11 @@ void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) { env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); - if (arg1 & (1 << CP0DB_DM)) + if (arg1 & (1 << CP0DB_DM)) { env->hflags |= MIPS_HFLAG_DM; - else + } else { env->hflags &= ~MIPS_HFLAG_DM; + } } void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) @@ -1912,10 +1964,11 @@ void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); /* XXX: Might be wrong, check with EJTAG spec. */ - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.CP0_Debug_tcstatus = val; - else + } else { other->tcs[other_tc].CP0_Debug_tcstatus = val; + } other->CP0_Debug = (other->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); @@ -1944,9 +1997,11 @@ void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) { if (env->hflags & MIPS_HFLAG_ITC_CACHE) { - /* If CACHE instruction is configured for ITC tags then make all - CP0.TagLo bits writable. The actual write to ITC Configuration - Tag will take care of the read-only bits. */ + /* + * If CACHE instruction is configured for ITC tags then make all + * CP0.TagLo bits writable. The actual write to ITC Configuration + * Tag will take care of the read-only bits. + */ env->CP0_TagLo = arg1; } else { env->CP0_TagLo = arg1 & 0xFFFFFCF6; @@ -1974,10 +2029,11 @@ target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.gpr[sel]; - else + } else { return other->tcs[other_tc].gpr[sel]; + } } target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) @@ -1985,10 +2041,11 @@ target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.LO[sel]; - else + } else { return other->tcs[other_tc].LO[sel]; + } } target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) @@ -1996,10 +2053,11 @@ target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.HI[sel]; - else + } else { return other->tcs[other_tc].HI[sel]; + } } target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) @@ -2007,10 +2065,11 @@ target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.ACX[sel]; - else + } else { return other->tcs[other_tc].ACX[sel]; + } } target_ulong helper_mftdsp(CPUMIPSState *env) @@ -2018,10 +2077,11 @@ target_ulong helper_mftdsp(CPUMIPSState *env) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { return other->active_tc.DSPControl; - else + } else { return other->tcs[other_tc].DSPControl; + } } void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2029,10 +2089,11 @@ void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.gpr[sel] = arg1; - else + } else { other->tcs[other_tc].gpr[sel] = arg1; + } } void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2040,10 +2101,11 @@ void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.LO[sel] = arg1; - else + } else { other->tcs[other_tc].LO[sel] = arg1; + } } void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2051,10 +2113,11 @@ void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.HI[sel] = arg1; - else + } else { other->tcs[other_tc].HI[sel] = arg1; + } } void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) @@ -2062,10 +2125,11 @@ void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.ACX[sel] = arg1; - else + } else { other->tcs[other_tc].ACX[sel] = arg1; + } } void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) @@ -2073,22 +2137,23 @@ void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - if (other_tc == other->current_tc) + if (other_tc == other->current_tc) { other->active_tc.DSPControl = arg1; - else + } else { other->tcs[other_tc].DSPControl = arg1; + } } /* MIPS MT functions */ target_ulong helper_dmt(void) { - // TODO - return 0; + /* TODO */ + return 0; } target_ulong helper_emt(void) { - // TODO + /* TODO */ return 0; } @@ -2130,8 +2195,10 @@ target_ulong helper_evpe(CPUMIPSState *env) void helper_fork(target_ulong arg1, target_ulong arg2) { - // arg1 = rt, arg2 = rs - // TODO: store to TC register + /* + * arg1 = rt, arg2 = rs + * TODO: store to TC register + */ } target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) @@ -2149,11 +2216,12 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) } } } else if (arg1 == 0) { - if (0 /* TODO: TC underflow */) { + if (0) { + /* TODO: TC underflow */ env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); do_raise_exception(env, EXCP_THREAD, GETPC()); } else { - // TODO: Deallocate TC + /* TODO: Deallocate TC */ } } else if (arg1 > 0) { /* Yield qualifier inputs not implemented. */ @@ -2193,8 +2261,10 @@ target_ulong helper_evp(CPUMIPSState *env) CPU_FOREACH(other_cs) { MIPSCPU *other_cpu = MIPS_CPU(other_cs); if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) { - /* If the VP is WFI, don't disturb its sleep. - * Otherwise, wake it up. */ + /* + * If the VP is WFI, don't disturb its sleep. + * Otherwise, wake it up. + */ mips_vpe_wake(other_cpu); } } @@ -2206,7 +2276,7 @@ target_ulong helper_evp(CPUMIPSState *env) #ifndef CONFIG_USER_ONLY /* TLB management */ -static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) { /* Discard entries from env->tlb[first] onwards. */ while (env->tlb->tlb_in_use > first) { @@ -2308,8 +2378,10 @@ void r4k_helper_tlbwi(CPUMIPSState *env) XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; - /* Discard cached TLB entries, unless tlbwi is just upgrading access - permissions on the current entry. */ + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || (!tlb->EHINV && EHINV) || (tlb->V0 && !V0) || (tlb->D0 && !D0) || @@ -2370,7 +2442,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) #endif /* Check ASID, virtual page number & size */ if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { - r4k_mips_tlb_flush_extra (env, i); + r4k_mips_tlb_flush_extra(env, i); break; } } @@ -2400,8 +2472,9 @@ void r4k_helper_tlbr(CPUMIPSState *env) tlb = &env->tlb->mmu.r4k.tlb[idx]; /* If this will change the current ASID, flush qemu's TLB. */ - if (ASID != tlb->ASID) + if (ASID != tlb->ASID) { cpu_mips_tlb_flush(env); + } r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); @@ -2476,10 +2549,12 @@ static void debug_pre_eret(CPUMIPSState *env) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) + if (env->CP0_Status & (1 << CP0St_ERL)) { qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - if (env->hflags & MIPS_HFLAG_DM) + } + if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } qemu_log("\n"); } } @@ -2489,17 +2564,25 @@ static void debug_post_eret(CPUMIPSState *env) if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) + if (env->CP0_Status & (1 << CP0St_ERL)) { qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - if (env->hflags & MIPS_HFLAG_DM) + } + if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } switch (cpu_mmu_index(env, false)) { case 3: qemu_log(", ERL\n"); break; - case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; - case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; - case MIPS_HFLAG_KM: qemu_log("\n"); break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; default: cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; @@ -2609,8 +2692,9 @@ void helper_pmon(CPUMIPSState *env, int function) function /= 2; switch (function) { case 2: /* TODO: char inbyte(int waitflag); */ - if (env->active_tc.gpr[4] == 0) + if (env->active_tc.gpr[4] == 0) { env->active_tc.gpr[2] = -1; + } /* Fall through */ case 11: /* TODO: char inbyte (void); */ env->active_tc.gpr[2] = -1; @@ -2636,8 +2720,10 @@ void helper_wait(CPUMIPSState *env) cs->halted = 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* Last instruction in the block, PC was updated before - - no need to recover PC and icount */ + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ raise_exception(env, EXCP_HLT); } @@ -2731,13 +2817,15 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) } break; case 25: - arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); + arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | + ((env->active_fpu.fcr31 >> 23) & 0x1); break; case 26: arg1 = env->active_fpu.fcr31 & 0x0003f07c; break; case 28: - arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); + arg1 = (env->active_fpu.fcr31 & 0x00000f83) | + ((env->active_fpu.fcr31 >> 22) & 0x4); break; default: arg1 = (int32_t)env->active_fpu.fcr31; @@ -2802,19 +2890,24 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { return; } - env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | - ((arg1 & 0x1) << 23); + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | + ((arg1 & 0xfe) << 24) | + ((arg1 & 0x1) << 23); break; case 26: - if (arg1 & 0x007c0000) + if (arg1 & 0x007c0000) { return; - env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); + } + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | + (arg1 & 0x0003f07c); break; case 28: - if (arg1 & 0x007c0000) + if (arg1 & 0x007c0000) { return; - env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | - ((arg1 & 0x4) << 22); + } + env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | + (arg1 & 0x00000f83) | + ((arg1 & 0x4) << 22); break; case 31: env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) | @@ -2828,8 +2921,10 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) } restore_fp_status(env); set_float_exception_flags(0, &env->active_fpu.fp_status); - if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & + GET_FP_CAUSE(env->active_fpu.fcr31)) { do_raise_exception(env, EXCP_FPE, GETPC()); + } } int ieee_ex_to_mips(int xcpt) @@ -2857,7 +2952,8 @@ int ieee_ex_to_mips(int xcpt) static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) { - int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); + int tmp = ieee_ex_to_mips(get_float_exception_flags( + &env->active_fpu.fp_status)); SET_FP_CAUSE(env->active_fpu.fcr31, tmp); @@ -2872,10 +2968,12 @@ static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) } } -/* Float support. - Single precition routines have a "s" suffix, double precision a - "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", - paired single lower "pl", paired single upper "pu". */ +/* + * Float support. + * Single precition routines have a "s" suffix, double precision a + * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", + * paired single lower "pl", paired single upper "pu". + */ /* unary operations, modifying fp status */ uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) @@ -3056,7 +3154,8 @@ uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3071,7 +3170,8 @@ uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3086,7 +3186,8 @@ uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3101,7 +3202,8 @@ uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; - set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); restore_rounding_mode(env); if (get_float_exception_flags(&env->active_fpu.fp_status) @@ -3116,7 +3218,8 @@ uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); + dt2 = float64_to_int64_round_to_zero(fdt0, + &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; @@ -3697,7 +3800,8 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; uint32_t fsth2; - fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; @@ -3737,8 +3841,8 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) } #define FLOAT_RINT(name, bits) \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t fs) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs) \ { \ uint ## bits ## _t fdret; \ \ @@ -3763,8 +3867,8 @@ FLOAT_RINT(rint_d, 64) #define FLOAT_CLASS_POSITIVE_ZERO 0x200 #define FLOAT_CLASS(name, bits) \ -uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \ - float_status *status) \ +uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \ + float_status *status) \ { \ if (float ## bits ## _is_signaling_nan(arg, status)) { \ return FLOAT_CLASS_SIGNALING_NAN; \ @@ -3793,8 +3897,8 @@ uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \ } \ } \ \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t arg) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t arg) \ { \ return float_ ## name(arg, &env->active_fpu.fp_status); \ } @@ -3810,7 +3914,7 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ { \ uint64_t dt2; \ \ - dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ + dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\ update_fcr31(env, GETPC()); \ return dt2; \ } \ @@ -3820,7 +3924,7 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ { \ uint32_t wt2; \ \ - wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ + wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\ update_fcr31(env, GETPC()); \ return wt2; \ } \ @@ -3836,8 +3940,8 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ uint32_t wt2; \ uint32_t wth2; \ \ - wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ - wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ + wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \ + wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \ update_fcr31(env, GETPC()); \ return ((uint64_t)wth2 << 32) | wt2; \ } @@ -3852,7 +3956,8 @@ FLOAT_BINOP(div) uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); + fdt2 = float64_chs(float64_sub(fdt2, float64_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fdt2; } @@ -3860,7 +3965,8 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fst2; } @@ -3874,8 +3980,10 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); - fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_sub(fsth2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3884,7 +3992,8 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); - fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); + fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fdt2; } @@ -3893,7 +4002,8 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return fst2; } @@ -3909,8 +4019,10 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); - fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, + &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3924,8 +4036,8 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; - fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); - fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); + fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3939,16 +4051,16 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; - fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); - fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); + fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } #define FLOAT_MINMAX(name, bits, minmaxfunc) \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs, \ + uint ## bits ## _t ft) \ { \ uint ## bits ## _t fdret; \ \ @@ -4026,10 +4138,10 @@ FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) #undef FLOAT_FMA #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ -uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft, \ - uint ## bits ## _t fd) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs, \ + uint ## bits ## _t ft, \ + uint ## bits ## _t fd) \ { \ uint ## bits ## _t fdret; \ \ @@ -4072,26 +4184,58 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ CLEAR_FP_COND(cc, env->active_fpu); \ } -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. */ -FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0)) -FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) -FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. */ -FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0)) -FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) -FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) -FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called. + */ +FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(ngle, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(seq, float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(lt, float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(nge, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(le, float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) #define FOP_COND_S(op, cond) \ void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ @@ -4119,26 +4263,58 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ CLEAR_FP_COND(cc, env->active_fpu); \ } -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0)) -FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) -FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0)) -FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) -FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) -FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_S(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status)) #define FOP_COND_PS(op, condl, condh) \ void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ @@ -4184,47 +4360,107 @@ void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ CLEAR_FP_COND(cc + 1, env->active_fpu); \ } -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0), - (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0)) -FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) -FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0), - (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0)) -FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) -FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), - float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), - float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), - float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) -FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_PS(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) /* R6 compare operations */ #define FOP_CONDN_D(op, cond) \ -uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \ - uint64_t fdt1) \ +uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1) \ { \ uint64_t c; \ c = cond; \ @@ -4236,50 +4472,90 @@ uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \ } \ } -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. */ -FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0)) -FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))) -FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. */ -FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0)) -FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))) -FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) -FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called.\ + */ +FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) #define FOP_CONDN_S(op, cond) \ -uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \ - uint32_t fst1) \ +uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1) \ { \ uint64_t c; \ c = cond; \ @@ -4291,46 +4567,86 @@ uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \ } \ } -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. */ -FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0)) -FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))) -FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))) -/* NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. */ -FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0)) -FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status))) -FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) - || float32_eq(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) - || float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status) - || float32_le(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) -FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(seq, (float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(slt, (float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sle, (float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sor, (float32_le(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sne, (float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) /* MSA */ /* Data format min and max values */ @@ -4522,7 +4838,7 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, } #define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE) + ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE) static inline void ensure_writable_pages(CPUMIPSState *env, target_ulong addr, diff --git a/target/mips/translate.c b/target/mips/translate.c index 50397167fc..4bff585bd6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5546,78 +5546,181 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) gen_load_fpr64(ctx, t0, rs); gen_load_fpr64(ctx, t1, rt); -#define LMI_HELPER(UP, LO) \ - case OPC_##UP: gen_helper_##LO(t0, t0, t1); break -#define LMI_HELPER_1(UP, LO) \ - case OPC_##UP: gen_helper_##LO(t0, t0); break -#define LMI_DIRECT(UP, LO, OP) \ - case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); break - switch (opc) { - LMI_HELPER(PADDSH, paddsh); - LMI_HELPER(PADDUSH, paddush); - LMI_HELPER(PADDH, paddh); - LMI_HELPER(PADDW, paddw); - LMI_HELPER(PADDSB, paddsb); - LMI_HELPER(PADDUSB, paddusb); - LMI_HELPER(PADDB, paddb); - - LMI_HELPER(PSUBSH, psubsh); - LMI_HELPER(PSUBUSH, psubush); - LMI_HELPER(PSUBH, psubh); - LMI_HELPER(PSUBW, psubw); - LMI_HELPER(PSUBSB, psubsb); - LMI_HELPER(PSUBUSB, psubusb); - LMI_HELPER(PSUBB, psubb); - - LMI_HELPER(PSHUFH, pshufh); - LMI_HELPER(PACKSSWH, packsswh); - LMI_HELPER(PACKSSHB, packsshb); - LMI_HELPER(PACKUSHB, packushb); - - LMI_HELPER(PUNPCKLHW, punpcklhw); - LMI_HELPER(PUNPCKHHW, punpckhhw); - LMI_HELPER(PUNPCKLBH, punpcklbh); - LMI_HELPER(PUNPCKHBH, punpckhbh); - LMI_HELPER(PUNPCKLWD, punpcklwd); - LMI_HELPER(PUNPCKHWD, punpckhwd); - - LMI_HELPER(PAVGH, pavgh); - LMI_HELPER(PAVGB, pavgb); - LMI_HELPER(PMAXSH, pmaxsh); - LMI_HELPER(PMINSH, pminsh); - LMI_HELPER(PMAXUB, pmaxub); - LMI_HELPER(PMINUB, pminub); - - LMI_HELPER(PCMPEQW, pcmpeqw); - LMI_HELPER(PCMPGTW, pcmpgtw); - LMI_HELPER(PCMPEQH, pcmpeqh); - LMI_HELPER(PCMPGTH, pcmpgth); - LMI_HELPER(PCMPEQB, pcmpeqb); - LMI_HELPER(PCMPGTB, pcmpgtb); - - LMI_HELPER(PSLLW, psllw); - LMI_HELPER(PSLLH, psllh); - LMI_HELPER(PSRLW, psrlw); - LMI_HELPER(PSRLH, psrlh); - LMI_HELPER(PSRAW, psraw); - LMI_HELPER(PSRAH, psrah); - - LMI_HELPER(PMULLH, pmullh); - LMI_HELPER(PMULHH, pmulhh); - LMI_HELPER(PMULHUH, pmulhuh); - LMI_HELPER(PMADDHW, pmaddhw); - - LMI_HELPER(PASUBUB, pasubub); - LMI_HELPER_1(BIADD, biadd); - LMI_HELPER_1(PMOVMSKB, pmovmskb); - - LMI_DIRECT(PADDD, paddd, add); - LMI_DIRECT(PSUBD, psubd, sub); - LMI_DIRECT(XOR_CP2, xor, xor); - LMI_DIRECT(NOR_CP2, nor, nor); - LMI_DIRECT(AND_CP2, and, and); - LMI_DIRECT(OR_CP2, or, or); + case OPC_PADDSH: + gen_helper_paddsh(t0, t0, t1); + break; + case OPC_PADDUSH: + gen_helper_paddush(t0, t0, t1); + break; + case OPC_PADDH: + gen_helper_paddh(t0, t0, t1); + break; + case OPC_PADDW: + gen_helper_paddw(t0, t0, t1); + break; + case OPC_PADDSB: + gen_helper_paddsb(t0, t0, t1); + break; + case OPC_PADDUSB: + gen_helper_paddusb(t0, t0, t1); + break; + case OPC_PADDB: + gen_helper_paddb(t0, t0, t1); + break; + + case OPC_PSUBSH: + gen_helper_psubsh(t0, t0, t1); + break; + case OPC_PSUBUSH: + gen_helper_psubush(t0, t0, t1); + break; + case OPC_PSUBH: + gen_helper_psubh(t0, t0, t1); + break; + case OPC_PSUBW: + gen_helper_psubw(t0, t0, t1); + break; + case OPC_PSUBSB: + gen_helper_psubsb(t0, t0, t1); + break; + case OPC_PSUBUSB: + gen_helper_psubusb(t0, t0, t1); + break; + case OPC_PSUBB: + gen_helper_psubb(t0, t0, t1); + break; + + case OPC_PSHUFH: + gen_helper_pshufh(t0, t0, t1); + break; + case OPC_PACKSSWH: + gen_helper_packsswh(t0, t0, t1); + break; + case OPC_PACKSSHB: + gen_helper_packsshb(t0, t0, t1); + break; + case OPC_PACKUSHB: + gen_helper_packushb(t0, t0, t1); + break; + + case OPC_PUNPCKLHW: + gen_helper_punpcklhw(t0, t0, t1); + break; + case OPC_PUNPCKHHW: + gen_helper_punpckhhw(t0, t0, t1); + break; + case OPC_PUNPCKLBH: + gen_helper_punpcklbh(t0, t0, t1); + break; + case OPC_PUNPCKHBH: + gen_helper_punpckhbh(t0, t0, t1); + break; + case OPC_PUNPCKLWD: + gen_helper_punpcklwd(t0, t0, t1); + break; + case OPC_PUNPCKHWD: + gen_helper_punpckhwd(t0, t0, t1); + break; + + case OPC_PAVGH: + gen_helper_pavgh(t0, t0, t1); + break; + case OPC_PAVGB: + gen_helper_pavgb(t0, t0, t1); + break; + case OPC_PMAXSH: + gen_helper_pmaxsh(t0, t0, t1); + break; + case OPC_PMINSH: + gen_helper_pminsh(t0, t0, t1); + break; + case OPC_PMAXUB: + gen_helper_pmaxub(t0, t0, t1); + break; + case OPC_PMINUB: + gen_helper_pminub(t0, t0, t1); + break; + + case OPC_PCMPEQW: + gen_helper_pcmpeqw(t0, t0, t1); + break; + case OPC_PCMPGTW: + gen_helper_pcmpgtw(t0, t0, t1); + break; + case OPC_PCMPEQH: + gen_helper_pcmpeqh(t0, t0, t1); + break; + case OPC_PCMPGTH: + gen_helper_pcmpgth(t0, t0, t1); + break; + case OPC_PCMPEQB: + gen_helper_pcmpeqb(t0, t0, t1); + break; + case OPC_PCMPGTB: + gen_helper_pcmpgtb(t0, t0, t1); + break; + + case OPC_PSLLW: + gen_helper_psllw(t0, t0, t1); + break; + case OPC_PSLLH: + gen_helper_psllh(t0, t0, t1); + break; + case OPC_PSRLW: + gen_helper_psrlw(t0, t0, t1); + break; + case OPC_PSRLH: + gen_helper_psrlh(t0, t0, t1); + break; + case OPC_PSRAW: + gen_helper_psraw(t0, t0, t1); + break; + case OPC_PSRAH: + gen_helper_psrah(t0, t0, t1); + break; + + case OPC_PMULLH: + gen_helper_pmullh(t0, t0, t1); + break; + case OPC_PMULHH: + gen_helper_pmulhh(t0, t0, t1); + break; + case OPC_PMULHUH: + gen_helper_pmulhuh(t0, t0, t1); + break; + case OPC_PMADDHW: + gen_helper_pmaddhw(t0, t0, t1); + break; + + case OPC_PASUBUB: + gen_helper_pasubub(t0, t0, t1); + break; + case OPC_BIADD: + gen_helper_biadd(t0, t0); + break; + case OPC_PMOVMSKB: + gen_helper_pmovmskb(t0, t0); + break; + + case OPC_PADDD: + tcg_gen_add_i64(t0, t0, t1); + break; + case OPC_PSUBD: + tcg_gen_sub_i64(t0, t0, t1); + break; + case OPC_XOR_CP2: + tcg_gen_xor_i64(t0, t0, t1); + break; + case OPC_NOR_CP2: + tcg_gen_nor_i64(t0, t0, t1); + break; + case OPC_AND_CP2: + tcg_gen_and_i64(t0, t0, t1); + break; + case OPC_OR_CP2: + tcg_gen_or_i64(t0, t0, t1); + break; case OPC_PANDN: tcg_gen_andc_i64(t0, t1, t0); @@ -5770,9 +5873,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) return; } -#undef LMI_HELPER -#undef LMI_DIRECT - gen_store_fpr64(ctx, t0, rd); tcg_temp_free_i64(t0); @@ -28466,6 +28566,86 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; } break; + case OPC_ADD_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_addv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_addv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_addv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_addv_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_AVE_S_df: switch (df) { case DF_BYTE: @@ -28642,6 +28822,102 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; } break; + case OPC_MAX_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_MOD_S_df: switch (df) { case DF_BYTE: @@ -28674,14 +28950,213 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; } break; + case OPC_ASUB_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_SLL_df: - gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt); + switch (df) { + case DF_BYTE: + gen_helper_msa_sll_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sll_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sll_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sll_d(cpu_env, twd, tws, twt); + break; + } break; - case OPC_ADDV_df: - gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt); + case OPC_SRA_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sra_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sra_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sra_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sra_d(cpu_env, twd, tws, twt); + break; + } break; - case OPC_ADD_A_df: - gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt); + case OPC_SRAR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srar_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srar_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srar_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srar_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); + break; + } break; case OPC_SUBS_S_df: gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt); @@ -28695,15 +29170,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_VSHF_df: gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_SRA_df: - gen_helper_msa_sra_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBV_df: gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_ADDS_A_df: - gen_helper_msa_adds_a_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBS_U_df: gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt); break; @@ -28713,72 +29182,15 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_SPLAT_df: gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_SRAR_df: - gen_helper_msa_srar_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SRL_df: - gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MAX_S_df: - gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ADDS_S_df: - gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUS_U_df: gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt); break; case OPC_MSUBV_df: gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_PCKEV_df: - gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SRLR_df: - gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MAX_U_df: - gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ADDS_U_df: - gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUU_S_df: gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_PCKOD_df: - gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MIN_S_df: - gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ASUB_S_df: - gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVL_df: - gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MIN_U_df: - gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ASUB_U_df: - gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVR_df: - gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MAX_A_df: - gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVEV_df: - gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MIN_A_df: - gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_ILVOD_df: - gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_DOTP_S_df: case OPC_DOTP_U_df: @@ -28795,6 +29207,58 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; } switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_HADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_DOTP_S_df: gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt); break; @@ -28810,21 +29274,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_DPSUB_S_df: gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_HADD_S_df: - gen_helper_msa_hadd_s_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_DPSUB_U_df: gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_HADD_U_df: - gen_helper_msa_hadd_u_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_HSUB_S_df: - gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_HSUB_U_df: - gen_helper_msa_hsub_u_df(cpu_env, tdf, twd, tws, twt); - break; } break; default: diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 2472a5217a..81d5a7a341 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -590,40 +590,38 @@ static void trans_vsl(DisasContext *ctx) int VT = rD(ctx->opcode); int VA = rA(ctx->opcode); int VB = rB(ctx->opcode); - TCGv_i64 avrA = tcg_temp_new_i64(); - TCGv_i64 avrB = tcg_temp_new_i64(); + TCGv_i64 avr = tcg_temp_new_i64(); TCGv_i64 sh = tcg_temp_new_i64(); - TCGv_i64 shifted = tcg_temp_new_i64(); + TCGv_i64 carry = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64(); - /* Place bits 125-127 of vB in sh. */ - get_avr64(avrB, VB, false); - tcg_gen_andi_i64(sh, avrB, 0x07ULL); + /* Place bits 125-127 of vB in 'sh'. */ + get_avr64(avr, VB, false); + tcg_gen_andi_i64(sh, avr, 0x07ULL); /* - * Save highest sh bits of lower doubleword element of vA in variable - * shifted and perform shift on lower doubleword. + * Save highest 'sh' bits of lower doubleword element of vA in variable + * 'carry' and perform shift on lower doubleword. */ - get_avr64(avrA, VA, false); - tcg_gen_subfi_i64(tmp, 64, sh); - tcg_gen_shr_i64(shifted, avrA, tmp); - tcg_gen_andi_i64(shifted, shifted, 0x7fULL); - tcg_gen_shl_i64(avrA, avrA, sh); - set_avr64(VT, avrA, false); + get_avr64(avr, VA, false); + tcg_gen_subfi_i64(tmp, 32, sh); + tcg_gen_shri_i64(carry, avr, 32); + tcg_gen_shr_i64(carry, carry, tmp); + tcg_gen_shl_i64(avr, avr, sh); + set_avr64(VT, avr, false); /* * Perform shift on higher doubleword element of vA and replace lowest - * sh bits with shifted. + * 'sh' bits with 'carry'. */ - get_avr64(avrA, VA, true); - tcg_gen_shl_i64(avrA, avrA, sh); - tcg_gen_or_i64(avrA, avrA, shifted); - set_avr64(VT, avrA, true); + get_avr64(avr, VA, true); + tcg_gen_shl_i64(avr, avr, sh); + tcg_gen_or_i64(avr, avr, carry); + set_avr64(VT, avr, true); - tcg_temp_free_i64(avrA); - tcg_temp_free_i64(avrB); + tcg_temp_free_i64(avr); tcg_temp_free_i64(sh); - tcg_temp_free_i64(shifted); + tcg_temp_free_i64(carry); tcg_temp_free_i64(tmp); } @@ -639,39 +637,37 @@ static void trans_vsr(DisasContext *ctx) int VT = rD(ctx->opcode); int VA = rA(ctx->opcode); int VB = rB(ctx->opcode); - TCGv_i64 avrA = tcg_temp_new_i64(); - TCGv_i64 avrB = tcg_temp_new_i64(); + TCGv_i64 avr = tcg_temp_new_i64(); TCGv_i64 sh = tcg_temp_new_i64(); - TCGv_i64 shifted = tcg_temp_new_i64(); + TCGv_i64 carry = tcg_temp_new_i64(); TCGv_i64 tmp = tcg_temp_new_i64(); - /* Place bits 125-127 of vB in sh. */ - get_avr64(avrB, VB, false); - tcg_gen_andi_i64(sh, avrB, 0x07ULL); + /* Place bits 125-127 of vB in 'sh'. */ + get_avr64(avr, VB, false); + tcg_gen_andi_i64(sh, avr, 0x07ULL); /* - * Save lowest sh bits of higher doubleword element of vA in variable - * shifted and perform shift on higher doubleword. + * Save lowest 'sh' bits of higher doubleword element of vA in variable + * 'carry' and perform shift on higher doubleword. */ - get_avr64(avrA, VA, true); - tcg_gen_subfi_i64(tmp, 64, sh); - tcg_gen_shl_i64(shifted, avrA, tmp); - tcg_gen_andi_i64(shifted, shifted, 0xfe00000000000000ULL); - tcg_gen_shr_i64(avrA, avrA, sh); - set_avr64(VT, avrA, true); + get_avr64(avr, VA, true); + tcg_gen_subfi_i64(tmp, 32, sh); + tcg_gen_shli_i64(carry, avr, 32); + tcg_gen_shl_i64(carry, carry, tmp); + tcg_gen_shr_i64(avr, avr, sh); + set_avr64(VT, avr, true); /* * Perform shift on lower doubleword element of vA and replace highest - * sh bits with shifted. + * 'sh' bits with 'carry'. */ - get_avr64(avrA, VA, false); - tcg_gen_shr_i64(avrA, avrA, sh); - tcg_gen_or_i64(avrA, avrA, shifted); - set_avr64(VT, avrA, false); + get_avr64(avr, VA, false); + tcg_gen_shr_i64(avr, avr, sh); + tcg_gen_or_i64(avr, avr, carry); + set_avr64(VT, avr, false); - tcg_temp_free_i64(avrA); - tcg_temp_free_i64(avrB); + tcg_temp_free_i64(avr); tcg_temp_free_i64(sh); - tcg_temp_free_i64(shifted); + tcg_temp_free_i64(carry); tcg_temp_free_i64(tmp); } diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 009afc38b9..7e92fb2e15 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -515,6 +515,7 @@ static void cpu_model_from_info(S390CPUModel *model, const CpuModelInfo *info, visitor = qobject_input_visitor_new(info->props); visit_start_struct(visitor, NULL, NULL, 0, errp); if (*errp) { + visit_free(visitor); object_unref(obj); return; } diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c index c24c869e77..0c9d14b4b1 100644 --- a/target/s390x/kvm.c +++ b/target/s390x/kvm.c @@ -320,11 +320,17 @@ void kvm_s390_set_max_pagesize(uint64_t pagesize, Error **errp) cap_hpage_1m = 1; } -int kvm_arch_init(MachineState *ms, KVMState *s) +static void ccw_machine_class_foreach(ObjectClass *oc, void *opaque) { - MachineClass *mc = MACHINE_GET_CLASS(ms); + MachineClass *mc = MACHINE_CLASS(oc); mc->default_cpu_type = S390_CPU_TYPE_NAME("host"); +} + +int kvm_arch_init(MachineState *ms, KVMState *s) +{ + object_class_foreach(ccw_machine_class_foreach, TYPE_S390_CCW_MACHINE, + false, NULL); if (!kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) { error_report("KVM is missing capability KVM_CAP_DEVICE_CTRL - " diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 90b81335f9..c9f3f34750 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -556,9 +556,7 @@ int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, *flags |= PAGE_WRITE_INV; if (is_low_address(raddr) && rw == MMU_DATA_STORE) { /* LAP sets bit 56 */ - *tec = (raddr & TARGET_PAGE_MASK) - | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) - | 0x80; + *tec = (raddr & TARGET_PAGE_MASK) | FS_WRITE | 0x80; return PGM_PROTECTION; } } diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index 5ce7bfb0af..71059f9ca0 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -2132,12 +2132,12 @@ static DisasJumpType op_vs(DisasContext *s, DisasOps *o) static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { - tcg_gen_setcond_i32(TCG_COND_LTU, d, a, b); + tcg_gen_setcond_i32(TCG_COND_GEU, d, a, b); } static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_setcond_i64(TCG_COND_LTU, d, a, b); + tcg_gen_setcond_i64(TCG_COND_GEU, d, a, b); } static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -2151,7 +2151,8 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_gen_andi_i64(th, th, 1); tcg_gen_sub2_i64(tl, th, ah, zero, th, zero); tcg_gen_sub2_i64(tl, th, tl, th, bh, zero); - tcg_gen_andi_i64(dl, th, 1); + /* "invert" the result: -1 -> 0; 0 -> 1 */ + tcg_gen_addi_i64(dl, th, 1); tcg_gen_mov_i64(dh, zero); tcg_temp_free_i64(th); @@ -2186,13 +2187,13 @@ static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) { TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 th = tcg_temp_new_i64(); - tcg_gen_andi_i64(tl, cl, 1); - tcg_gen_sub2_i64(dl, dh, al, ah, bl, bh); - tcg_gen_sub2_i64(dl, dh, dl, dh, tl, zero); + tcg_gen_not_i64(tl, bl); + tcg_gen_not_i64(th, bh); + gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); + tcg_temp_free_i64(th); } static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o) @@ -2213,20 +2214,13 @@ static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); - tcg_gen_andi_i64(tl, cl, 1); - tcg_gen_sub2_i64(tl, th, al, zero, tl, zero); - tcg_gen_sub2_i64(tl, th, tl, th, bl, zero); - tcg_gen_andi_i64(th, th, 1); - tcg_gen_sub2_i64(tl, th, ah, zero, th, zero); - tcg_gen_sub2_i64(tl, th, tl, th, bh, zero); - tcg_gen_andi_i64(dl, th, 1); - tcg_gen_mov_i64(dh, zero); + tcg_gen_not_i64(tl, bl); + tcg_gen_not_i64(th, bh); + gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch); tcg_temp_free_i64(tl); tcg_temp_free_i64(th); - tcg_temp_free_i64(zero); } static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o) diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index 68eaae407b..0d6bc13dd6 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -70,15 +70,17 @@ static void s390_vec_sar(S390Vector *d, const S390Vector *a, uint64_t count) d->doubleword[0] = a->doubleword[0]; d->doubleword[1] = a->doubleword[1]; } else if (count == 64) { + tmp = (int64_t)a->doubleword[0] >> 63; d->doubleword[1] = a->doubleword[0]; - d->doubleword[0] = 0; + d->doubleword[0] = tmp; } else if (count < 64) { tmp = a->doubleword[1] >> count; d->doubleword[1] = deposit64(tmp, 64 - count, count, a->doubleword[0]); d->doubleword[0] = (int64_t)a->doubleword[0] >> count; } else { + tmp = (int64_t)a->doubleword[0] >> 63; d->doubleword[1] = (int64_t)a->doubleword[0] >> (count - 64); - d->doubleword[0] = 0; + d->doubleword[0] = tmp; } } @@ -336,7 +338,7 @@ void HELPER(gvec_vmae##BITS)(void *v1, const void *v2, const void *v3, \ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \ - int##TBITS##_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, j); \ + int##TBITS##_t c = s390_vec_read_element##TBITS(v4, i); \ \ s390_vec_write_element##TBITS(v1, i, a * b + c); \ } \ @@ -354,7 +356,7 @@ void HELPER(gvec_vmale##BITS)(void *v1, const void *v2, const void *v3, \ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \ uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \ uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \ - uint##TBITS##_t c = s390_vec_read_element##BITS(v4, j); \ + uint##TBITS##_t c = s390_vec_read_element##TBITS(v4, i); \ \ s390_vec_write_element##TBITS(v1, i, a * b + c); \ } \ @@ -372,7 +374,7 @@ void HELPER(gvec_vmao##BITS)(void *v1, const void *v2, const void *v3, \ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \ - int##TBITS##_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, j); \ + int##TBITS##_t c = s390_vec_read_element##TBITS(v4, i); \ \ s390_vec_write_element##TBITS(v1, i, a * b + c); \ } \ @@ -390,7 +392,7 @@ void HELPER(gvec_vmalo##BITS)(void *v1, const void *v2, const void *v3, \ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \ uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \ uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \ - uint##TBITS##_t c = s390_vec_read_element##BITS(v4, j); \ + uint##TBITS##_t c = s390_vec_read_element##TBITS(v4, i); \ \ s390_vec_write_element##TBITS(v1, i, a * b + c); \ } \ @@ -488,7 +490,7 @@ void HELPER(gvec_vmlo##BITS)(void *v1, const void *v2, const void *v3, \ { \ int i, j; \ \ - for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \ + for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \ const uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \ const uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \ \ @@ -591,7 +593,7 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3, \ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \ \ - s390_vec_write_element##BITS(v1, i, a < b); \ + s390_vec_write_element##BITS(v1, i, a >= b); \ } \ } DEF_VSCBI(8) diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c index 3a59fefa94..089ed7da5d 100644 --- a/target/xtensa/core-test_mmuhifi_c3.c +++ b/target/xtensa/core-test_mmuhifi_c3.c @@ -27,8 +27,8 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "qemu-common.h" #include "qemu/host-utils.h" #include "core-test_mmuhifi_c3/core-isa.h" @@ -39,7 +39,6 @@ static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = { .name = "test_mmuhifi_c3", - .options = XTENSA_OPTIONS, .gdb_regmap = { .reg = { #include "core-test_mmuhifi_c3/gdb-config.inc.c" diff --git a/target/xtensa/core-test_mmuhifi_c3/core-isa.h b/target/xtensa/core-test_mmuhifi_c3/core-isa.h index 704a31f7c8..838b1b09da 100644 --- a/target/xtensa/core-test_mmuhifi_c3/core-isa.h +++ b/target/xtensa/core-test_mmuhifi_c3/core-isa.h @@ -1,15 +1,37 @@ /* - * Xtensa processor core configuration information. + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration * - * This file is subject to the terms and conditions of version 2.1 of the GNU - * Lesser General Public License as published by the Free Software Foundation. - * - * Copyright (c) 1999-2009 Tensilica Inc. + * See <xtensa/config/core.h>, which includes this file, for more details. */ +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2019 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + #ifndef XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H #define XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H + /**************************************************************************** Parameters Useful for Any Code, USER or PRIVILEGED ****************************************************************************/ @@ -32,6 +54,7 @@ #define XCHAL_HAVE_DEBUG 1 /* debug option */ #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ @@ -59,44 +82,73 @@ #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ #define XCHAL_HAVE_PRID 1 /* processor ID register */ #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 1 /* MX core (Tensilica internal) */ #define XCHAL_HAVE_MP_INTERRUPTS 1 /* interrupt distributor port */ #define XCHAL_HAVE_MP_RUNSTALL 1 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ #define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ #define XCHAL_HAVE_MAC16 0 /* MAC16 package */ #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ -#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ #define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ /*---------------------------------------------------------------------- MISC ----------------------------------------------------------------------*/ +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ #define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ #define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ /* In T1050, applies to selected core load and store instructions (see ISA): */ #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ -#define XCHAL_SW_VERSION 800000 /* sw version of this header */ +#define XCHAL_SW_VERSION 1000006 /* sw version of this header */ #define XCHAL_CORE_ID "test_mmuhifi_c3" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */ -#define XCHAL_CORE_DESCRIPTION "test_mmuhifi_c3" #define XCHAL_BUILD_UNIQUE_ID 0x00005A6A /* 22-bit sw build ID */ /* @@ -136,6 +188,10 @@ #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ #define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */ +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ + @@ -172,6 +228,8 @@ #define XCHAL_ICACHE_ACCESS_SIZE 8 #define XCHAL_DCACHE_ACCESS_SIZE 8 +#define XCHAL_DCACHE_BANKS 1 /* number of banks */ + /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ #define XCHAL_CA_BITS 4 @@ -187,6 +245,8 @@ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + /*---------------------------------------------------------------------- INTERRUPTS and TIMERS @@ -261,6 +321,7 @@ #define XCHAL_INTTYPE_MASK_TIMER 0x00000140 #define XCHAL_INTTYPE_MASK_NMI 0x00000000 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 /* Interrupt numbers assigned to specific interrupt sources: */ #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ @@ -273,7 +334,7 @@ /* - * External interrupt vectors/levels. + * External interrupt mapping. * These macros describe how Xtensa processor interrupt numbers * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) * map to external BInterrupt<n> pins, for those interrupts @@ -281,7 +342,7 @@ * See the Xtensa processor databook for more details. */ -/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ @@ -291,6 +352,16 @@ #define XCHAL_EXTINT6_NUM 9 /* (intlevel 1) */ #define XCHAL_EXTINT7_NUM 10 /* (intlevel 1) */ #define XCHAL_EXTINT8_NUM 11 /* (intlevel 1) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT11_EXTNUM 8 /* (intlevel 1) */ /*---------------------------------------------------------------------- @@ -300,11 +371,13 @@ #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 == XEA1 (old) 2 == XEA2 (new) - 0 == XEAX (extern) */ + 0 == XEAX (extern) or TX */ #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ @@ -344,13 +417,30 @@ /*---------------------------------------------------------------------- - DEBUG + DEBUG MODULE ----------------------------------------------------------------------*/ +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 0 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ #define XCHAL_NUM_IBREAK 0 /* number of IBREAKn regs */ #define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 0 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ /*---------------------------------------------------------------------- diff --git a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c b/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c index 618d30dffa..0bca70b5af 100644 --- a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c +++ b/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c @@ -1,23 +1,25 @@ /* Configuration for the Xtensa architecture for GDB, the GNU debugger. - Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. + Copyright (c) 2003-2019 Tensilica Inc. - This file is part of GDB. + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see <http://www.gnu.org/licenses/>. */ - - /* idx ofs bi sz al targno flags cp typ group name */ + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) @@ -58,8 +60,8 @@ XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0) XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) - XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0) - XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) @@ -137,4 +139,82 @@ XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask19,0,0,0) + XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask20,0,0,0) + XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask21,0,0,0) + XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask22,0,0,0) + XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr, + 0,0,&xtensa_mask23,0,0,0) + XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben, + 0,0,&xtensa_mask24,0,0,0) + XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask25,0,0,0) + XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3, + 0,0,&xtensa_mask26,0,0,0) + XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2, + 0,0,&xtensa_mask27,0,0,0) + XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1, + 0,0,&xtensa_mask28,0,0,0) + XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4, + 0,0,&xtensa_mask29,0,0,0) + XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4, + 0,0,&xtensa_mask30,0,0,0) + XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase, + 0,0,&xtensa_mask31,0,0,0) + XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow, + 0,0,&xtensa_mask32,0,0,0) + XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar, + 0,0,&xtensa_mask33,0,0,0) + XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr, + 0,0,&xtensa_mask34,0,0,0) + XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused, + 0,0,&xtensa_mask35,0,0,0) + XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize, + 0,0,&xtensa_mask36,0,0,0) + XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts, + 0,0,&xtensa_mask37,0,0,0) + XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset, + 0,0,&xtensa_mask38,0,0,0) XTREG_END diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c index 687631b8fb..28561147fc 100644 --- a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c +++ b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c @@ -1,24 +1,26 @@ /* Xtensa configuration-specific ISA information. - Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc. - This file is part of BFD, the Binary File Descriptor library. + Copyright (c) 2003-2019 Tensilica Inc. - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3 of the - License, or (at your option) any later version. + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#include "qemu/osdep.h" #include "xtensa-isa.h" #include "xtensa-isa-internal.h" @@ -32,8 +34,8 @@ static xtensa_sysreg_internal sysregs[] = { { "BR", 4, 0 }, { "PTEVADDR", 83, 0 }, { "DDR", 104, 0 }, - { "176", 176, 0 }, - { "208", 208, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, { "INTERRUPT", 226, 0 }, { "INTCLEAR", 227, 0 }, { "CCOUNT", 234, 0 }, @@ -8634,6 +8636,38 @@ Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) } static unsigned +Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) { unsigned tie_t = 0; @@ -8794,6 +8828,8 @@ enum xtensa_field_id { FIELD_ae_r20, FIELD_ae_r10, FIELD_ae_s20, + FIELD_ae_fld_ohba, + FIELD_ae_fld_ohba2, FIELD_op0_s3, FIELD_ftsf12, FIELD_ftsf13, @@ -9184,7 +9220,7 @@ enum xtensa_interface_id { INTERFACE_RMPINT_In }; - + /* Constant tables. */ /* constant table ai4c */ @@ -9254,1602 +9290,1462 @@ static const unsigned CONST_TBL_b4cu_0[] = { /* Instruction operands. */ static int -Operand_soffsetx4_decode (uint32 *valp) -{ - unsigned soffsetx4_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); - *valp = soffsetx4_0; - return 0; -} - -static int -Operand_soffsetx4_encode (uint32 *valp) -{ - unsigned offset_0, soffsetx4_0; - soffsetx4_0 = *valp; - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; - *valp = offset_0; - return 0; -} - -static int -Operand_soffsetx4_ator (uint32 *valp, uint32 pc) -{ - *valp -= (pc & ~0x3); - return 0; -} - -static int -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) -{ - *valp += (pc & ~0x3); - return 0; -} - -static int -Operand_uimm12x8_decode (uint32 *valp) +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) { - unsigned uimm12x8_0, imm12_0; - imm12_0 = *valp & 0xfff; - uimm12x8_0 = imm12_0 << 3; - *valp = uimm12x8_0; + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; return 0; } static int -Operand_uimm12x8_encode (uint32 *valp) +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) { - unsigned imm12_0, uimm12x8_0; - uimm12x8_0 = *valp; - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); - *valp = imm12_0; + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; return 0; } static int -Operand_simm4_decode (uint32 *valp) +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) { - unsigned simm4_0, mn_0; - mn_0 = *valp & 0xf; - simm4_0 = ((int) mn_0 << 28) >> 28; - *valp = simm4_0; + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; return 0; } static int -Operand_simm4_encode (uint32 *valp) +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) { - unsigned mn_0, simm4_0; - simm4_0 = *valp; - mn_0 = (simm4_0 & 0xf); - *valp = mn_0; + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; return 0; } static int -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_simm4_decode (uint32 *valp) { + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; return 0; } static int -Operand_arr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_simm4_encode (uint32 *valp) { + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; return 0; } static int -Operand_ars_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int -Operand_art_encode (uint32 *valp) +OperandSem_opnd_sem_AR_encode (uint32 *valp) { int error; - error = (*valp & ~0xf) != 0; + error = (*valp >= 32); return error; } static int -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int -Operand_ar0_encode (uint32 *valp) +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) { int error; - error = (*valp & ~0x1f) != 0; + error = (*valp >= 32); return error; } static int -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int -Operand_ar4_encode (uint32 *valp) +OperandSem_opnd_sem_AR_1_encode (uint32 *valp) { int error; - error = (*valp & ~0x1f) != 0; + error = (*valp >= 32); return error; } static int -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int -Operand_ar8_encode (uint32 *valp) +OperandSem_opnd_sem_AR_2_encode (uint32 *valp) { int error; - error = (*valp & ~0x1f) != 0; + error = (*valp >= 32); return error; } static int -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int -Operand_ar12_encode (uint32 *valp) +OperandSem_opnd_sem_AR_3_encode (uint32 *valp) { int error; - error = (*valp & ~0x1f) != 0; + error = (*valp >= 32); return error; } static int -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) { return 0; } static int -Operand_ars_entry_encode (uint32 *valp) +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) { int error; - error = (*valp & ~0x1f) != 0; + error = (*valp >= 32); return error; } static int -Operand_immrx4_decode (uint32 *valp) +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) { - unsigned immrx4_0, r_0; - r_0 = *valp & 0xf; - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; - *valp = immrx4_0; + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; return 0; } static int -Operand_immrx4_encode (uint32 *valp) +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) { - unsigned r_0, immrx4_0; - immrx4_0 = *valp; - r_0 = ((immrx4_0 >> 2) & 0xf); - *valp = r_0; + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; return 0; } static int -Operand_lsi4x4_decode (uint32 *valp) +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) { - unsigned lsi4x4_0, r_0; - r_0 = *valp & 0xf; - lsi4x4_0 = r_0 << 2; - *valp = lsi4x4_0; + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; return 0; } static int -Operand_lsi4x4_encode (uint32 *valp) +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) { - unsigned r_0, lsi4x4_0; - lsi4x4_0 = *valp; - r_0 = ((lsi4x4_0 >> 2) & 0xf); - *valp = r_0; + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; return 0; } static int -Operand_simm7_decode (uint32 *valp) +OperandSem_opnd_sem_simm7_decode (uint32 *valp) { - unsigned simm7_0, imm7_0; - imm7_0 = *valp & 0x7f; - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; - *valp = simm7_0; + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; return 0; } static int -Operand_simm7_encode (uint32 *valp) +OperandSem_opnd_sem_simm7_encode (uint32 *valp) { - unsigned imm7_0, simm7_0; - simm7_0 = *valp; - imm7_0 = (simm7_0 & 0x7f); - *valp = imm7_0; + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; return 0; } static int -Operand_uimm6_decode (uint32 *valp) +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) { - unsigned uimm6_0, imm6_0; - imm6_0 = *valp & 0x3f; - uimm6_0 = 0x4 + (((0) << 6) | imm6_0); - *valp = uimm6_0; + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; return 0; } static int -Operand_uimm6_encode (uint32 *valp) +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) { - unsigned imm6_0, uimm6_0; - uimm6_0 = *valp; - imm6_0 = (uimm6_0 - 0x4) & 0x3f; - *valp = imm6_0; + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; return 0; } static int -Operand_uimm6_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) { - *valp -= pc; + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; return 0; } static int -Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) { - *valp += pc; - return 0; -} - -static int -Operand_ai4const_decode (uint32 *valp) -{ - unsigned ai4const_0, t_0; - t_0 = *valp & 0xf; - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; - *valp = ai4const_0; - return 0; -} - -static int -Operand_ai4const_encode (uint32 *valp) -{ - unsigned t_0, ai4const_0; - ai4const_0 = *valp; - switch (ai4const_0) + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) { - case 0xffffffff: t_0 = 0; break; - case 0x1: t_0 = 0x1; break; - case 0x2: t_0 = 0x2; break; - case 0x3: t_0 = 0x3; break; - case 0x4: t_0 = 0x4; break; - case 0x5: t_0 = 0x5; break; - case 0x6: t_0 = 0x6; break; - case 0x7: t_0 = 0x7; break; - case 0x8: t_0 = 0x8; break; - case 0x9: t_0 = 0x9; break; - case 0xa: t_0 = 0xa; break; - case 0xb: t_0 = 0xb; break; - case 0xc: t_0 = 0xc; break; - case 0xd: t_0 = 0xd; break; - case 0xe: t_0 = 0xe; break; - default: t_0 = 0xf; break; + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; } - *valp = t_0; + *valp = ai4const_in_0; return 0; } static int -Operand_b4const_decode (uint32 *valp) +OperandSem_opnd_sem_b4const_decode (uint32 *valp) { - unsigned b4const_0, r_0; - r_0 = *valp & 0xf; - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; - *valp = b4const_0; + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; return 0; } static int -Operand_b4const_encode (uint32 *valp) +OperandSem_opnd_sem_b4const_encode (uint32 *valp) { - unsigned r_0, b4const_0; - b4const_0 = *valp; - switch (b4const_0) + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) { - case 0xffffffff: r_0 = 0; break; - case 0x1: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; } - *valp = r_0; + *valp = b4const_in_0; return 0; } static int -Operand_b4constu_decode (uint32 *valp) +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) { - unsigned b4constu_0, r_0; - r_0 = *valp & 0xf; - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; - *valp = b4constu_0; + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; return 0; } static int -Operand_b4constu_encode (uint32 *valp) +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) { - unsigned r_0, b4constu_0; - b4constu_0 = *valp; - switch (b4constu_0) + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) { - case 0x8000: r_0 = 0; break; - case 0x10000: r_0 = 0x1; break; - case 0x2: r_0 = 0x2; break; - case 0x3: r_0 = 0x3; break; - case 0x4: r_0 = 0x4; break; - case 0x5: r_0 = 0x5; break; - case 0x6: r_0 = 0x6; break; - case 0x7: r_0 = 0x7; break; - case 0x8: r_0 = 0x8; break; - case 0xa: r_0 = 0x9; break; - case 0xc: r_0 = 0xa; break; - case 0x10: r_0 = 0xb; break; - case 0x20: r_0 = 0xc; break; - case 0x40: r_0 = 0xd; break; - case 0x80: r_0 = 0xe; break; - default: r_0 = 0xf; break; + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; } - *valp = r_0; - return 0; -} - -static int -Operand_uimm8_decode (uint32 *valp) -{ - unsigned uimm8_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8_0 = imm8_0; - *valp = uimm8_0; - return 0; -} - -static int -Operand_uimm8_encode (uint32 *valp) -{ - unsigned imm8_0, uimm8_0; - uimm8_0 = *valp; - imm8_0 = (uimm8_0 & 0xff); - *valp = imm8_0; + *valp = b4constu_in_0; return 0; } static int -Operand_uimm8x2_decode (uint32 *valp) +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) { - unsigned uimm8x2_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x2_0 = imm8_0 << 1; - *valp = uimm8x2_0; + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; return 0; } static int -Operand_uimm8x2_encode (uint32 *valp) +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) { - unsigned imm8_0, uimm8x2_0; - uimm8x2_0 = *valp; - imm8_0 = ((uimm8x2_0 >> 1) & 0xff); - *valp = imm8_0; + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; return 0; } static int -Operand_uimm8x4_decode (uint32 *valp) +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) { - unsigned uimm8x4_0, imm8_0; - imm8_0 = *valp & 0xff; - uimm8x4_0 = imm8_0 << 2; - *valp = uimm8x4_0; + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; return 0; } static int -Operand_uimm8x4_encode (uint32 *valp) +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) { - unsigned imm8_0, uimm8x4_0; - uimm8x4_0 = *valp; - imm8_0 = ((uimm8x4_0 >> 2) & 0xff); - *valp = imm8_0; + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; return 0; } static int -Operand_uimm4x16_decode (uint32 *valp) +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) { - unsigned uimm4x16_0, op2_0; - op2_0 = *valp & 0xf; - uimm4x16_0 = op2_0 << 4; - *valp = uimm4x16_0; + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; return 0; } static int -Operand_uimm4x16_encode (uint32 *valp) +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) { - unsigned op2_0, uimm4x16_0; - uimm4x16_0 = *valp; - op2_0 = ((uimm4x16_0 >> 4) & 0xf); - *valp = op2_0; + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; return 0; } static int -Operand_simm8_decode (uint32 *valp) +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) { - unsigned simm8_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8_0 = ((int) imm8_0 << 24) >> 24; - *valp = simm8_0; + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; return 0; } static int -Operand_simm8_encode (uint32 *valp) +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) { - unsigned imm8_0, simm8_0; - simm8_0 = *valp; - imm8_0 = (simm8_0 & 0xff); - *valp = imm8_0; + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; return 0; } static int -Operand_simm8x256_decode (uint32 *valp) +OperandSem_opnd_sem_simm8_decode (uint32 *valp) { - unsigned simm8x256_0, imm8_0; - imm8_0 = *valp & 0xff; - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; - *valp = simm8x256_0; + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; return 0; } static int -Operand_simm8x256_encode (uint32 *valp) -{ - unsigned imm8_0, simm8x256_0; - simm8x256_0 = *valp; - imm8_0 = ((simm8x256_0 >> 8) & 0xff); - *valp = imm8_0; - return 0; -} - -static int -Operand_simm12b_decode (uint32 *valp) -{ - unsigned simm12b_0, imm12b_0; - imm12b_0 = *valp & 0xfff; - simm12b_0 = ((int) imm12b_0 << 20) >> 20; - *valp = simm12b_0; - return 0; -} - -static int -Operand_simm12b_encode (uint32 *valp) -{ - unsigned imm12b_0, simm12b_0; - simm12b_0 = *valp; - imm12b_0 = (simm12b_0 & 0xfff); - *valp = imm12b_0; - return 0; -} - -static int -Operand_msalp32_decode (uint32 *valp) -{ - unsigned msalp32_0, sal_0; - sal_0 = *valp & 0x1f; - msalp32_0 = 0x20 - sal_0; - *valp = msalp32_0; - return 0; -} - -static int -Operand_msalp32_encode (uint32 *valp) -{ - unsigned sal_0, msalp32_0; - msalp32_0 = *valp; - sal_0 = (0x20 - msalp32_0) & 0x1f; - *valp = sal_0; - return 0; -} - -static int -Operand_op2p1_decode (uint32 *valp) -{ - unsigned op2p1_0, op2_0; - op2_0 = *valp & 0xf; - op2p1_0 = op2_0 + 0x1; - *valp = op2p1_0; - return 0; -} - -static int -Operand_op2p1_encode (uint32 *valp) -{ - unsigned op2_0, op2p1_0; - op2p1_0 = *valp; - op2_0 = (op2p1_0 - 0x1) & 0xf; - *valp = op2_0; - return 0; -} - -static int -Operand_label8_decode (uint32 *valp) -{ - unsigned label8_0, imm8_0; - imm8_0 = *valp & 0xff; - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); - *valp = label8_0; - return 0; -} - -static int -Operand_label8_encode (uint32 *valp) -{ - unsigned imm8_0, label8_0; - label8_0 = *valp; - imm8_0 = (label8_0 - 0x4) & 0xff; - *valp = imm8_0; - return 0; -} - -static int -Operand_label8_ator (uint32 *valp, uint32 pc) -{ - *valp -= pc; - return 0; -} - -static int -Operand_label8_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_simm8_encode (uint32 *valp) { - *valp += pc; + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; return 0; } static int -Operand_ulabel8_decode (uint32 *valp) +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) { - unsigned ulabel8_0, imm8_0; - imm8_0 = *valp & 0xff; - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); - *valp = ulabel8_0; + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; return 0; } static int -Operand_ulabel8_encode (uint32 *valp) +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) { - unsigned imm8_0, ulabel8_0; - ulabel8_0 = *valp; - imm8_0 = (ulabel8_0 - 0x4) & 0xff; - *valp = imm8_0; + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; return 0; } static int -Operand_ulabel8_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) { - *valp -= pc; + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; return 0; } static int -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) { - *valp += pc; + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; return 0; } static int -Operand_label12_decode (uint32 *valp) +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) { - unsigned label12_0, imm12_0; - imm12_0 = *valp & 0xfff; - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); - *valp = label12_0; + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; return 0; } static int -Operand_label12_encode (uint32 *valp) +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) { - unsigned imm12_0, label12_0; - label12_0 = *valp; - imm12_0 = (label12_0 - 0x4) & 0xfff; - *valp = imm12_0; + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; return 0; } static int -Operand_label12_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) { - *valp -= pc; + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; return 0; } static int -Operand_label12_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) { - *valp += pc; + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; return 0; } static int -Operand_soffset_decode (uint32 *valp) +OperandSem_opnd_sem_label8_decode (uint32 *valp) { - unsigned soffset_0, offset_0; - offset_0 = *valp & 0x3ffff; - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); - *valp = soffset_0; + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; return 0; } static int -Operand_soffset_encode (uint32 *valp) +OperandSem_opnd_sem_label8_encode (uint32 *valp) { - unsigned offset_0, soffset_0; - soffset_0 = *valp; - offset_0 = (soffset_0 - 0x4) & 0x3ffff; - *valp = offset_0; + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; return 0; } static int -Operand_soffset_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) { - *valp -= pc; + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; return 0; } static int -Operand_soffset_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) { - *valp += pc; + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; return 0; } static int -Operand_uimm16x4_decode (uint32 *valp) +OperandSem_opnd_sem_label12_decode (uint32 *valp) { - unsigned uimm16x4_0, imm16_0; - imm16_0 = *valp & 0xffff; - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; - *valp = uimm16x4_0; + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; return 0; } static int -Operand_uimm16x4_encode (uint32 *valp) +OperandSem_opnd_sem_label12_encode (uint32 *valp) { - unsigned imm16_0, uimm16x4_0; - uimm16x4_0 = *valp; - imm16_0 = (uimm16x4_0 >> 2) & 0xffff; - *valp = imm16_0; + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; return 0; } static int -Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_soffset_decode (uint32 *valp) { - *valp -= ((pc + 3) & ~0x3); + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; return 0; } static int -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_soffset_encode (uint32 *valp) { - *valp += ((pc + 3) & ~0x3); + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; return 0; } static int -Operand_immt_decode (uint32 *valp) +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) { - unsigned immt_0, t_0; - t_0 = *valp & 0xf; - immt_0 = t_0; - *valp = immt_0; + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; return 0; } static int -Operand_immt_encode (uint32 *valp) +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) { - unsigned t_0, immt_0; - immt_0 = *valp; - t_0 = immt_0 & 0xf; - *valp = t_0; + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; return 0; } static int -Operand_imms_decode (uint32 *valp) +OperandSem_opnd_sem_bbi_decode (uint32 *valp) { - unsigned imms_0, s_0; - s_0 = *valp & 0xf; - imms_0 = s_0; - *valp = imms_0; + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; return 0; } static int -Operand_imms_encode (uint32 *valp) +OperandSem_opnd_sem_bbi_encode (uint32 *valp) { - unsigned s_0, imms_0; - imms_0 = *valp; - s_0 = imms_0 & 0xf; - *valp = s_0; + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; return 0; } static int -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_s_decode (uint32 *valp) { + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; return 0; } static int -Operand_bt_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_s_encode (uint32 *valp) { + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; return 0; } static int -Operand_bs_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) +OperandSem_opnd_sem_immt_decode (uint32 *valp) { + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; return 0; } static int -Operand_br_encode (uint32 *valp) +OperandSem_opnd_sem_immt_encode (uint32 *valp) { - int error; - error = (*valp & ~0xf) != 0; - return error; -} - -static int -Operand_bt2_decode (uint32 *valp) -{ - *valp = *valp << 1; + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; return 0; } static int -Operand_bt2_encode (uint32 *valp) +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) { - int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; - return error; -} - -static int -Operand_bs2_decode (uint32 *valp) -{ - *valp = *valp << 1; return 0; } static int -Operand_bs2_encode (uint32 *valp) +OperandSem_opnd_sem_BR_encode (uint32 *valp) { int error; - error = (*valp & ~(0x7 << 1)) != 0; - *valp = *valp >> 1; + error = (*valp >= 16); return error; } static int -Operand_br2_decode (uint32 *valp) +OperandSem_opnd_sem_BR2_decode (uint32 *valp) { *valp = *valp << 1; return 0; } static int -Operand_br2_encode (uint32 *valp) +OperandSem_opnd_sem_BR2_encode (uint32 *valp) { int error; - error = (*valp & ~(0x7 << 1)) != 0; + error = (*valp >= 16) || ((*valp & 1) != 0); *valp = *valp >> 1; return error; } static int -Operand_bt4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_bt4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_bs4_decode (uint32 *valp) -{ - *valp = *valp << 2; - return 0; -} - -static int -Operand_bs4_encode (uint32 *valp) -{ - int error; - error = (*valp & ~(0x3 << 2)) != 0; - *valp = *valp >> 2; - return error; -} - -static int -Operand_br4_decode (uint32 *valp) +OperandSem_opnd_sem_BR4_decode (uint32 *valp) { *valp = *valp << 2; return 0; } static int -Operand_br4_encode (uint32 *valp) +OperandSem_opnd_sem_BR4_encode (uint32 *valp) { int error; - error = (*valp & ~(0x3 << 2)) != 0; + error = (*valp >= 16) || ((*valp & 3) != 0); *valp = *valp >> 2; return error; } static int -Operand_bt8_decode (uint32 *valp) +OperandSem_opnd_sem_BR8_decode (uint32 *valp) { *valp = *valp << 3; return 0; } static int -Operand_bt8_encode (uint32 *valp) +OperandSem_opnd_sem_BR8_encode (uint32 *valp) { int error; - error = (*valp & ~(0x1 << 3)) != 0; + error = (*valp >= 16) || ((*valp & 7) != 0); *valp = *valp >> 3; return error; } static int -Operand_bs8_decode (uint32 *valp) +OperandSem_opnd_sem_BR16_decode (uint32 *valp) { - *valp = *valp << 3; + *valp = *valp << 4; return 0; } static int -Operand_bs8_encode (uint32 *valp) +OperandSem_opnd_sem_BR16_encode (uint32 *valp) { int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; return error; } static int -Operand_br8_decode (uint32 *valp) +OperandSem_opnd_sem_tp7_decode (uint32 *valp) { - *valp = *valp << 3; + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; return 0; } static int -Operand_br8_encode (uint32 *valp) +OperandSem_opnd_sem_tp7_encode (uint32 *valp) { - int error; - error = (*valp & ~(0x1 << 3)) != 0; - *valp = *valp >> 3; - return error; + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; } static int -Operand_bt16_decode (uint32 *valp) +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) { - *valp = *valp << 4; + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; return 0; } static int -Operand_bt16_encode (uint32 *valp) +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) { - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; } static int -Operand_bs16_decode (uint32 *valp) +OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) { - *valp = *valp << 4; + unsigned ae_samt32_out_0; + unsigned ae_samt32_in_0; + ae_samt32_in_0 = *valp & 0x1f; + ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; + *valp = ae_samt32_out_0; return 0; } static int -Operand_bs16_encode (uint32 *valp) +OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) { - int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; - return error; + unsigned ae_samt32_in_0; + unsigned ae_samt32_out_0; + ae_samt32_out_0 = *valp; + ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); + *valp = ae_samt32_in_0; + return 0; } static int -Operand_br16_decode (uint32 *valp) +OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) { - *valp = *valp << 4; return 0; } static int -Operand_br16_encode (uint32 *valp) +OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) { int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; + error = (*valp >= 8); return error; } static int -Operand_brall_decode (uint32 *valp) +OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) { - *valp = *valp << 4; return 0; } static int -Operand_brall_encode (uint32 *valp) +OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) { int error; - error = (*valp & ~(0 << 4)) != 0; - *valp = *valp >> 4; + error = (*valp >= 4); return error; } static int -Operand_tp7_decode (uint32 *valp) +OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) { - unsigned tp7_0, t_0; - t_0 = *valp & 0xf; - tp7_0 = t_0 + 0x7; - *valp = tp7_0; + unsigned ae_lsimm16_out_0; + unsigned ae_lsimm16_in_0; + ae_lsimm16_in_0 = *valp & 0xf; + ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; + *valp = ae_lsimm16_out_0; return 0; } static int -Operand_tp7_encode (uint32 *valp) +OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) { - unsigned t_0, tp7_0; - tp7_0 = *valp; - t_0 = (tp7_0 - 0x7) & 0xf; - *valp = t_0; + unsigned ae_lsimm16_in_0; + unsigned ae_lsimm16_out_0; + ae_lsimm16_out_0 = *valp; + ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); + *valp = ae_lsimm16_in_0; return 0; } static int -Operand_xt_wbr15_label_decode (uint32 *valp) +OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) { - unsigned xt_wbr15_label_0, xt_wbr15_imm_0; - xt_wbr15_imm_0 = *valp & 0x7fff; - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); - *valp = xt_wbr15_label_0; + unsigned ae_lsimm32_out_0; + unsigned ae_lsimm32_in_0; + ae_lsimm32_in_0 = *valp & 0xf; + ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; + *valp = ae_lsimm32_out_0; return 0; } static int -Operand_xt_wbr15_label_encode (uint32 *valp) +OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) { - unsigned xt_wbr15_imm_0, xt_wbr15_label_0; - xt_wbr15_label_0 = *valp; - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; - *valp = xt_wbr15_imm_0; + unsigned ae_lsimm32_in_0; + unsigned ae_lsimm32_out_0; + ae_lsimm32_out_0 = *valp; + ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); + *valp = ae_lsimm32_in_0; return 0; } static int -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) { - *valp -= pc; + unsigned ae_lsimm64_out_0; + unsigned ae_lsimm64_in_0; + ae_lsimm64_in_0 = *valp & 0xf; + ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; + *valp = ae_lsimm64_out_0; return 0; } static int -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) { - *valp += pc; + unsigned ae_lsimm64_in_0; + unsigned ae_lsimm64_out_0; + ae_lsimm64_out_0 = *valp; + ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); + *valp = ae_lsimm64_in_0; return 0; } static int -Operand_xt_wbr18_label_decode (uint32 *valp) +OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) { - unsigned xt_wbr18_label_0, xt_wbr18_imm_0; - xt_wbr18_imm_0 = *valp & 0x3ffff; - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); - *valp = xt_wbr18_label_0; + unsigned ae_samt64_out_0; + unsigned ae_samt64_in_0; + ae_samt64_in_0 = *valp & 0x3f; + ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; + *valp = ae_samt64_out_0; return 0; } static int -Operand_xt_wbr18_label_encode (uint32 *valp) +OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) { - unsigned xt_wbr18_imm_0, xt_wbr18_label_0; - xt_wbr18_label_0 = *valp; - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; - *valp = xt_wbr18_imm_0; + unsigned ae_samt64_in_0; + unsigned ae_samt64_out_0; + ae_samt64_out_0 = *valp; + ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); + *valp = ae_samt64_in_0; return 0; } static int -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) { - *valp -= pc; + unsigned ae_ohba_out_0; + unsigned ae_ohba_in_0; + ae_ohba_in_0 = *valp & 0xf; + ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); + *valp = ae_ohba_out_0; return 0; } static int -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) { - *valp += pc; + unsigned ae_ohba_in_0; + unsigned ae_ohba_out_0; + ae_ohba_out_0 = *valp; + ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); + *valp = ae_ohba_in_0; return 0; } static int -Operand_ae_samt32_decode (uint32 *valp) +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) { - unsigned ae_samt32_0, ftsf14_0; - ftsf14_0 = *valp & 0x1f; - ae_samt32_0 = (0 << 5) | ftsf14_0; - *valp = ae_samt32_0; + *valp -= (pc & ~0x3); return 0; } static int -Operand_ae_samt32_encode (uint32 *valp) +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) { - unsigned ftsf14_0, ae_samt32_0; - ae_samt32_0 = *valp; - ftsf14_0 = (ae_samt32_0 & 0x1f); - *valp = ftsf14_0; + *valp += (pc & ~0x3); return 0; } static int -Operand_pr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +Operand_uimm6_ator (uint32 *valp, uint32 pc) { + *valp -= pc; return 0; } static int -Operand_pr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED) +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) { + *valp += pc; return 0; } static int -Operand_qr0_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_ae_lsimm16_decode (uint32 *valp) +Operand_label8_ator (uint32 *valp, uint32 pc) { - unsigned ae_lsimm16_0, t_0; - t_0 = *valp & 0xf; - ae_lsimm16_0 = (((int) t_0 << 28) >> 28) << 1; - *valp = ae_lsimm16_0; + *valp -= pc; return 0; } static int -Operand_ae_lsimm16_encode (uint32 *valp) +Operand_label8_rtoa (uint32 *valp, uint32 pc) { - unsigned t_0, ae_lsimm16_0; - ae_lsimm16_0 = *valp; - t_0 = ((ae_lsimm16_0 >> 1) & 0xf); - *valp = t_0; + *valp += pc; return 0; } static int -Operand_ae_lsimm32_decode (uint32 *valp) +Operand_ulabel8_ator (uint32 *valp, uint32 pc) { - unsigned ae_lsimm32_0, t_0; - t_0 = *valp & 0xf; - ae_lsimm32_0 = (((int) t_0 << 28) >> 28) << 2; - *valp = ae_lsimm32_0; + *valp -= pc; return 0; } static int -Operand_ae_lsimm32_encode (uint32 *valp) +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) { - unsigned t_0, ae_lsimm32_0; - ae_lsimm32_0 = *valp; - t_0 = ((ae_lsimm32_0 >> 2) & 0xf); - *valp = t_0; + *valp += pc; return 0; } static int -Operand_ae_lsimm64_decode (uint32 *valp) +Operand_label12_ator (uint32 *valp, uint32 pc) { - unsigned ae_lsimm64_0, t_0; - t_0 = *valp & 0xf; - ae_lsimm64_0 = (((int) t_0 << 28) >> 28) << 3; - *valp = ae_lsimm64_0; + *valp -= pc; return 0; } static int -Operand_ae_lsimm64_encode (uint32 *valp) +Operand_label12_rtoa (uint32 *valp, uint32 pc) { - unsigned t_0, ae_lsimm64_0; - ae_lsimm64_0 = *valp; - t_0 = ((ae_lsimm64_0 >> 3) & 0xf); - *valp = t_0; + *valp += pc; return 0; } static int -Operand_ae_samt64_decode (uint32 *valp) +Operand_soffset_ator (uint32 *valp, uint32 pc) { - unsigned ae_samt64_0, ae_samt_s_t_0; - ae_samt_s_t_0 = *valp & 0x3f; - ae_samt64_0 = (0 << 6) | ae_samt_s_t_0; - *valp = ae_samt64_0; + *valp -= pc; return 0; } static int -Operand_ae_samt64_encode (uint32 *valp) +Operand_soffset_rtoa (uint32 *valp, uint32 pc) { - unsigned ae_samt_s_t_0, ae_samt64_0; - ae_samt64_0 = *valp; - ae_samt_s_t_0 = (ae_samt64_0 & 0x3f); - *valp = ae_samt_s_t_0; + *valp += pc; return 0; } static int -Operand_ae_ohba_decode (uint32 *valp) +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) { - unsigned ae_ohba_0, op1_0; - op1_0 = *valp & 0xf; - ae_ohba_0 = (0 << 5) | (((((op1_0 & 0xf))) == 0) << 4) | ((op1_0 & 0xf)); - *valp = ae_ohba_0; + *valp -= ((pc + 3) & ~0x3); return 0; } static int -Operand_ae_ohba_encode (uint32 *valp) +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) { - unsigned op1_0, ae_ohba_0; - ae_ohba_0 = *valp; - op1_0 = (ae_ohba_0 & 0xf); - *valp = op1_0; + *valp += ((pc + 3) & ~0x3); return 0; } static int -Operand_pr_decode (uint32 *valp ATTRIBUTE_UNUSED) +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) { + *valp -= pc; return 0; } static int -Operand_pr_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - -static int -Operand_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED) +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) { + *valp += pc; return 0; } static int -Operand_qr0_rw_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED) +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) { + *valp -= pc; return 0; } static int -Operand_qr1_w_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x3) != 0; - return error; -} - -static int -Operand_ps_decode (uint32 *valp ATTRIBUTE_UNUSED) +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) { + *valp += pc; return 0; } -static int -Operand_ps_encode (uint32 *valp) -{ - int error; - error = (*valp & ~0x7) != 0; - return error; -} - static xtensa_operand_internal operands[] = { { "soffsetx4", FIELD_offset, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffsetx4_encode, Operand_soffsetx4_decode, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, { "uimm12x8", FIELD_imm12, -1, 0, 0, - Operand_uimm12x8_encode, Operand_uimm12x8_decode, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, 0, 0 }, { "simm4", FIELD_mn, -1, 0, 0, - Operand_simm4_encode, Operand_simm4_decode, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, 0, 0 }, { "arr", FIELD_r, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_arr_encode, Operand_arr_decode, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 0, 0 }, { "ars", FIELD_s, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_ars_encode, Operand_ars_decode, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 0, 0 }, { "*ars_invisible", FIELD_s, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ars_encode, Operand_ars_decode, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 0, 0 }, { "art", FIELD_t, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_art_encode, Operand_art_decode, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 0, 0 }, { "ar0", FIELD__ar0, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar0_encode, Operand_ar0_decode, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, 0, 0 }, { "ar4", FIELD__ar4, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar4_encode, Operand_ar4_decode, + OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, 0, 0 }, { "ar8", FIELD__ar8, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar8_encode, Operand_ar8_decode, + OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, 0, 0 }, { "ar12", FIELD__ar12, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_ar12_encode, Operand_ar12_decode, + OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, 0, 0 }, { "ars_entry", FIELD_s, REGFILE_AR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_ars_entry_encode, Operand_ars_entry_decode, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, 0, 0 }, { "immrx4", FIELD_r, -1, 0, 0, - Operand_immrx4_encode, Operand_immrx4_decode, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, 0, 0 }, { "lsi4x4", FIELD_r, -1, 0, 0, - Operand_lsi4x4_encode, Operand_lsi4x4_decode, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, 0, 0 }, { "simm7", FIELD_imm7, -1, 0, 0, - Operand_simm7_encode, Operand_simm7_decode, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, 0, 0 }, { "uimm6", FIELD_imm6, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm6_encode, Operand_uimm6_decode, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, Operand_uimm6_ator, Operand_uimm6_rtoa }, { "ai4const", FIELD_t, -1, 0, 0, - Operand_ai4const_encode, Operand_ai4const_decode, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, 0, 0 }, { "b4const", FIELD_r, -1, 0, 0, - Operand_b4const_encode, Operand_b4const_decode, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, 0, 0 }, { "b4constu", FIELD_r, -1, 0, 0, - Operand_b4constu_encode, Operand_b4constu_decode, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, 0, 0 }, { "uimm8", FIELD_imm8, -1, 0, 0, - Operand_uimm8_encode, Operand_uimm8_decode, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, 0, 0 }, { "uimm8x2", FIELD_imm8, -1, 0, 0, - Operand_uimm8x2_encode, Operand_uimm8x2_decode, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, 0, 0 }, { "uimm8x4", FIELD_imm8, -1, 0, 0, - Operand_uimm8x4_encode, Operand_uimm8x4_decode, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, 0, 0 }, { "uimm4x16", FIELD_op2, -1, 0, 0, - Operand_uimm4x16_encode, Operand_uimm4x16_decode, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, 0, 0 }, { "simm8", FIELD_imm8, -1, 0, 0, - Operand_simm8_encode, Operand_simm8_decode, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, 0, 0 }, { "simm8x256", FIELD_imm8, -1, 0, 0, - Operand_simm8x256_encode, Operand_simm8x256_decode, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, 0, 0 }, { "simm12b", FIELD_imm12b, -1, 0, 0, - Operand_simm12b_encode, Operand_simm12b_decode, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, 0, 0 }, { "msalp32", FIELD_sal, -1, 0, 0, - Operand_msalp32_encode, Operand_msalp32_decode, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, 0, 0 }, { "op2p1", FIELD_op2, -1, 0, 0, - Operand_op2p1_encode, Operand_op2p1_decode, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, 0, 0 }, { "label8", FIELD_imm8, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label8_encode, Operand_label8_decode, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, Operand_label8_ator, Operand_label8_rtoa }, { "ulabel8", FIELD_imm8, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_ulabel8_encode, Operand_ulabel8_decode, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, Operand_ulabel8_ator, Operand_ulabel8_rtoa }, { "label12", FIELD_imm12, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_label12_encode, Operand_label12_decode, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, Operand_label12_ator, Operand_label12_rtoa }, { "soffset", FIELD_offset, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_soffset_encode, Operand_soffset_decode, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, Operand_soffset_ator, Operand_soffset_rtoa }, { "uimm16x4", FIELD_imm16, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_uimm16x4_encode, Operand_uimm16x4_decode, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, { "immt", FIELD_t, -1, 0, 0, - Operand_immt_encode, Operand_immt_decode, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, 0, 0 }, { "imms", FIELD_s, -1, 0, 0, - Operand_imms_encode, Operand_imms_decode, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, 0, 0 }, { "bt", FIELD_t, REGFILE_BR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_bt_encode, Operand_bt_decode, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, 0, 0 }, { "bs", FIELD_s, REGFILE_BR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_bs_encode, Operand_bs_decode, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, 0, 0 }, { "br", FIELD_r, REGFILE_BR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_br_encode, Operand_br_decode, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, 0, 0 }, { "bt2", FIELD_t2, REGFILE_BR, 2, XTENSA_OPERAND_IS_REGISTER, - Operand_bt2_encode, Operand_bt2_decode, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, 0, 0 }, { "bs2", FIELD_s2, REGFILE_BR, 2, XTENSA_OPERAND_IS_REGISTER, - Operand_bs2_encode, Operand_bs2_decode, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, 0, 0 }, { "br2", FIELD_r2, REGFILE_BR, 2, XTENSA_OPERAND_IS_REGISTER, - Operand_br2_encode, Operand_br2_decode, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, 0, 0 }, { "bt4", FIELD_t4, REGFILE_BR, 4, XTENSA_OPERAND_IS_REGISTER, - Operand_bt4_encode, Operand_bt4_decode, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, 0, 0 }, { "bs4", FIELD_s4, REGFILE_BR, 4, XTENSA_OPERAND_IS_REGISTER, - Operand_bs4_encode, Operand_bs4_decode, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, 0, 0 }, { "br4", FIELD_r4, REGFILE_BR, 4, XTENSA_OPERAND_IS_REGISTER, - Operand_br4_encode, Operand_br4_decode, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, 0, 0 }, { "bt8", FIELD_t8, REGFILE_BR, 8, XTENSA_OPERAND_IS_REGISTER, - Operand_bt8_encode, Operand_bt8_decode, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, 0, 0 }, { "bs8", FIELD_s8, REGFILE_BR, 8, XTENSA_OPERAND_IS_REGISTER, - Operand_bs8_encode, Operand_bs8_decode, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, 0, 0 }, { "br8", FIELD_r8, REGFILE_BR, 8, XTENSA_OPERAND_IS_REGISTER, - Operand_br8_encode, Operand_br8_decode, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, 0, 0 }, { "bt16", FIELD__bt16, REGFILE_BR, 16, XTENSA_OPERAND_IS_REGISTER, - Operand_bt16_encode, Operand_bt16_decode, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 0, 0 }, { "bs16", FIELD__bs16, REGFILE_BR, 16, XTENSA_OPERAND_IS_REGISTER, - Operand_bs16_encode, Operand_bs16_decode, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 0, 0 }, { "br16", FIELD__br16, REGFILE_BR, 16, XTENSA_OPERAND_IS_REGISTER, - Operand_br16_encode, Operand_br16_decode, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 0, 0 }, { "brall", FIELD__brall, REGFILE_BR, 16, XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, - Operand_brall_encode, Operand_brall_decode, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 0, 0 }, { "tp7", FIELD_t, -1, 0, 0, - Operand_tp7_encode, Operand_tp7_decode, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, 0, 0 }, { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, XTENSA_OPERAND_IS_PCRELATIVE, - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, { "ae_samt32", FIELD_ftsf14, -1, 0, 0, - Operand_ae_samt32_encode, Operand_ae_samt32_decode, + OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, 0, 0 }, { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_pr0_encode, Operand_pr0_decode, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 0, 0 }, { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_qr0_encode, Operand_qr0_decode, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 0, 0 }, { "ae_lsimm16", FIELD_t, -1, 0, 0, - Operand_ae_lsimm16_encode, Operand_ae_lsimm16_decode, + OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, 0, 0 }, { "ae_lsimm32", FIELD_t, -1, 0, 0, - Operand_ae_lsimm32_encode, Operand_ae_lsimm32_decode, + OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, 0, 0 }, { "ae_lsimm64", FIELD_t, -1, 0, 0, - Operand_ae_lsimm64_encode, Operand_ae_lsimm64_decode, + OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, 0, 0 }, { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, 0, - Operand_ae_samt64_encode, Operand_ae_samt64_decode, + OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, 0, 0 }, - { "ae_ohba", FIELD_op1, -1, 0, + { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, 0, - Operand_ae_ohba_encode, Operand_ae_ohba_decode, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, + 0, 0 }, + { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, + 0, + OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, 0, 0 }, { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_pr_encode, Operand_pr_decode, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 0, 0 }, { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_qr0_rw_encode, Operand_qr0_rw_decode, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 0, 0 }, { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_qr1_w_encode, Operand_qr1_w_decode, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, + 0, 0 }, + { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 0, 0 }, { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, XTENSA_OPERAND_IS_REGISTER, - Operand_ps_encode, Operand_ps_decode, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, + 0, 0 }, + { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 0, 0 }, { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, - { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, - { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, @@ -10861,11 +10757,8 @@ static xtensa_operand_internal operands[] = { { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, - { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, - { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, - { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, @@ -10898,6 +10791,8 @@ static xtensa_operand_internal operands[] = { { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, + { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, @@ -11249,6 +11144,7 @@ enum xtensa_operand_id { OPERAND_uimm8x2, OPERAND_uimm8x4, OPERAND_uimm4x16, + OPERAND_uimmrx4, OPERAND_simm8, OPERAND_simm8x256, OPERAND_simm12b, @@ -11259,6 +11155,11 @@ enum xtensa_operand_id { OPERAND_label12, OPERAND_soffset, OPERAND_uimm16x4, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, OPERAND_immt, OPERAND_imms, OPERAND_bt, @@ -11283,21 +11184,25 @@ enum xtensa_operand_id { OPERAND_ae_samt32, OPERAND_pr0, OPERAND_qr0, + OPERAND_mac_qr0, OPERAND_ae_lsimm16, OPERAND_ae_lsimm32, OPERAND_ae_lsimm64, OPERAND_ae_samt64, OPERAND_ae_ohba, + OPERAND_ae_ohba2, OPERAND_pr, + OPERAND_cvt_pr, OPERAND_qr0_rw, + OPERAND_mac_qr0_rw, OPERAND_qr1_w, + OPERAND_mac_qr1_w, OPERAND_ps, + OPERAND_alupppb_ps, OPERAND_t, OPERAND_bbi4, - OPERAND_bbi, OPERAND_imm12, OPERAND_imm8, - OPERAND_s, OPERAND_imm12b, OPERAND_imm16, OPERAND_m, @@ -11309,11 +11214,8 @@ enum xtensa_operand_id { OPERAND_r, OPERAND_sa4, OPERAND_sae4, - OPERAND_sae, OPERAND_sal, - OPERAND_sargt, OPERAND_sas4, - OPERAND_sas, OPERAND_sr, OPERAND_st, OPERAND_thi3, @@ -11346,6 +11248,8 @@ enum xtensa_operand_id { OPERAND_ae_r20, OPERAND_ae_r10, OPERAND_ae_s20, + OPERAND_ae_fld_ohba, + OPERAND_ae_fld_ohba2, OPERAND_op0_s3, OPERAND_ftsf12, OPERAND_ftsf13, @@ -12316,29 +12220,29 @@ static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { { { STATE_LITBEN }, 'm' } }; -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { { { OPERAND_art }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { { { OPERAND_art }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = { +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { { { OPERAND_art }, 'o' } }; -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { { { STATE_PSEXCM }, 'i' }, { { STATE_PSRING }, 'i' } }; @@ -14759,7 +14663,7 @@ static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' } + { { OPERAND_cvt_pr }, 'i' } }; static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { @@ -14768,7 +14672,7 @@ static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_pr }, 'i' } + { { OPERAND_cvt_pr }, 'i' } }; static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { @@ -14918,7 +14822,7 @@ static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { - { { OPERAND_ps }, 'o' }, + { { OPERAND_alupppb_ps }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' }, { { OPERAND_bt2 }, 'o' } @@ -14929,7 +14833,7 @@ static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { - { { OPERAND_ps }, 'o' }, + { { OPERAND_alupppb_ps }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' }, { { OPERAND_bt2 }, 'o' } @@ -15458,7 +15362,7 @@ static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15469,7 +15373,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15479,7 +15383,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15489,7 +15393,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15500,7 +15404,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15510,7 +15414,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15520,7 +15424,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15531,7 +15435,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15541,7 +15445,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15551,7 +15455,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15562,7 +15466,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15572,7 +15476,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15582,7 +15486,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15593,7 +15497,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15603,7 +15507,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15613,7 +15517,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15624,7 +15528,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15634,7 +15538,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15644,7 +15548,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15655,7 +15559,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15665,7 +15569,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15675,7 +15579,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15686,7 +15590,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15696,7 +15600,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15706,7 +15610,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15717,7 +15621,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15727,7 +15631,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15737,7 +15641,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15748,7 +15652,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15758,7 +15662,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15768,7 +15672,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15779,7 +15683,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15789,7 +15693,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15799,7 +15703,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15810,7 +15714,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15820,7 +15724,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15830,7 +15734,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15841,7 +15745,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15852,7 +15756,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15863,7 +15767,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15874,7 +15778,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15885,7 +15789,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15896,7 +15800,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15907,7 +15811,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15918,7 +15822,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15929,7 +15833,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15940,7 +15844,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15951,7 +15855,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15962,7 +15866,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15973,7 +15877,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15984,7 +15888,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -15995,7 +15899,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16006,8 +15910,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16016,8 +15920,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16026,8 +15930,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16036,8 +15940,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16046,8 +15950,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16056,8 +15960,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16066,8 +15970,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16076,8 +15980,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16086,8 +15990,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16096,8 +16000,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16106,8 +16010,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16116,8 +16020,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16126,8 +16030,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16136,8 +16040,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16146,8 +16050,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16156,8 +16060,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16166,8 +16070,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16176,8 +16080,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16186,8 +16090,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16196,8 +16100,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16206,8 +16110,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16216,8 +16120,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16226,8 +16130,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16236,8 +16140,8 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { - { { OPERAND_qr1_w }, 'm' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'm' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' } }; @@ -16246,10 +16150,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16258,10 +16162,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16270,10 +16174,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16282,10 +16186,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16294,10 +16198,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16306,10 +16210,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16318,10 +16222,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16330,10 +16234,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16342,10 +16246,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16354,10 +16258,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16366,10 +16270,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16378,10 +16282,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16390,10 +16294,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16402,10 +16306,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16414,10 +16318,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16426,10 +16330,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16438,10 +16342,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16450,10 +16354,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16462,10 +16366,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16474,10 +16378,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16486,10 +16390,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16498,10 +16402,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16510,10 +16414,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16522,10 +16426,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16534,10 +16438,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16546,10 +16450,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16558,10 +16462,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16570,10 +16474,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16582,10 +16486,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16594,10 +16498,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16606,10 +16510,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16618,10 +16522,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16630,10 +16534,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16642,10 +16546,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16654,10 +16558,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16666,10 +16570,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16678,10 +16582,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16690,10 +16594,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16702,10 +16606,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16714,10 +16618,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16726,10 +16630,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16738,10 +16642,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16750,10 +16654,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16762,10 +16666,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16774,10 +16678,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16786,10 +16690,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16798,10 +16702,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16810,10 +16714,10 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, - { { OPERAND_qr0_rw }, 'i' }, + { { OPERAND_mac_qr1_w }, 'o' }, + { { OPERAND_mac_qr0_rw }, 'i' }, { { OPERAND_pr }, 'i' }, - { { OPERAND_qr0 }, 'i' }, + { { OPERAND_mac_qr0 }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16822,7 +16726,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16832,7 +16736,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16842,7 +16746,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16852,7 +16756,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16862,7 +16766,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16872,7 +16776,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16882,7 +16786,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16892,7 +16796,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16902,7 +16806,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16912,7 +16816,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16922,7 +16826,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16932,7 +16836,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16942,7 +16846,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16952,7 +16856,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16962,7 +16866,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16972,7 +16876,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'o' }, + { { OPERAND_mac_qr1_w }, 'o' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16982,7 +16886,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -16992,7 +16896,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17002,7 +16906,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17012,7 +16916,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17022,7 +16926,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17032,7 +16936,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17042,7 +16946,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17052,7 +16956,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17062,7 +16966,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17072,7 +16976,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17082,7 +16986,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17092,7 +16996,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17102,7 +17006,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17112,7 +17016,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17122,7 +17026,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17132,7 +17036,7 @@ static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { }; static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { - { { OPERAND_qr1_w }, 'm' }, + { { OPERAND_mac_qr1_w }, 'm' }, { { OPERAND_pr }, 'i' }, { { OPERAND_pr0 }, 'i' } }; @@ -17215,7 +17119,7 @@ static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { { { OPERAND_arr }, 'o' }, - { { OPERAND_ae_ohba }, 'i' } + { { OPERAND_ae_ohba2 }, 'i' } }; static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { @@ -17239,7 +17143,7 @@ static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { { { OPERAND_arr }, 'o' }, { { OPERAND_ars }, 'i' }, - { { OPERAND_ae_ohba }, 'i' } + { { OPERAND_ae_ohba2 }, 'i' } }; static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { @@ -17349,8 +17253,6 @@ static xtensa_iclass_internal iclasses[] = { 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_syscall */, 0, 0, 0, 0 }, - { 0, 0 /* xt_iclass_simcall */, - 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_call12_args, 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_call8_args, @@ -17467,6 +17369,8 @@ static xtensa_iclass_internal iclasses[] = { 0, 0, 0, 0 }, { 1, Iclass_xt_iclass_return_args, 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s16i_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_s32i_args, @@ -17529,12 +17433,12 @@ static xtensa_iclass_internal iclasses[] = { 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_litbase_args, 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_176_args, - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_wsr_176_args, - 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 }, - { 1, Iclass_xt_iclass_rsr_208_args, - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ps_args, 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ps_args, @@ -18524,7 +18428,6 @@ enum xtensa_iclass_id { ICLASS_xt_iclass_rfe, ICLASS_xt_iclass_rfde, ICLASS_xt_iclass_syscall, - ICLASS_xt_iclass_simcall, ICLASS_xt_iclass_call12, ICLASS_xt_iclass_call8, ICLASS_xt_iclass_call4, @@ -18583,6 +18486,7 @@ enum xtensa_iclass_id { ICLASS_xt_iclass_neg, ICLASS_xt_iclass_nop, ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, ICLASS_xt_iclass_s16i, ICLASS_xt_iclass_s32i, ICLASS_xt_iclass_s8i, @@ -18614,9 +18518,9 @@ enum xtensa_iclass_id { ICLASS_xt_iclass_rsr_litbase, ICLASS_xt_iclass_wsr_litbase, ICLASS_xt_iclass_xsr_litbase, - ICLASS_xt_iclass_rsr_176, - ICLASS_xt_iclass_wsr_176, - ICLASS_xt_iclass_rsr_208, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, ICLASS_xt_iclass_rsr_ps, ICLASS_xt_iclass_wsr_ps, ICLASS_xt_iclass_xsr_ps, @@ -19138,12 +19042,6 @@ Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) } static void -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) -{ - slotbuf[0] = 0x5100; -} - -static void Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x35; @@ -20032,6 +19930,12 @@ Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) } static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x5002; @@ -20344,19 +20248,19 @@ Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) } static void -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x3b000; } static void -Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x13b000; } static void -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0x3d000; } @@ -24175,10 +24079,6 @@ static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 }; -static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 -}; - static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 }; @@ -24555,6 +24455,10 @@ static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 }; +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 +}; + static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode }; @@ -24703,16 +24607,16 @@ static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { - Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0 +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 }; -static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { - Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0 +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 }; -static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { - Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0 +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 }; static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { @@ -26873,9 +26777,6 @@ static xtensa_opcode_internal opcodes[] = { { "syscall", ICLASS_xt_iclass_syscall, 0, Opcode_syscall_encode_fns, 0, 0 }, - { "simcall", ICLASS_xt_iclass_simcall, - 0, - Opcode_simcall_encode_fns, 0, 0 }, { "call12", ICLASS_xt_iclass_call12, XTENSA_OPCODE_IS_CALL, Opcode_call12_encode_fns, 0, 0 }, @@ -27158,6 +27059,9 @@ static xtensa_opcode_internal opcodes[] = { { "ret", ICLASS_xt_iclass_return, XTENSA_OPCODE_IS_JUMP, Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, { "s16i", ICLASS_xt_iclass_s16i, 0, Opcode_s16i_encode_fns, 0, 0 }, @@ -27269,15 +27173,15 @@ static xtensa_opcode_internal opcodes[] = { { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, 0, Opcode_xsr_litbase_encode_fns, 0, 0 }, - { "rsr.176", ICLASS_xt_iclass_rsr_176, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, 0, - Opcode_rsr_176_encode_fns, 0, 0 }, - { "wsr.176", ICLASS_xt_iclass_wsr_176, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, 0, - Opcode_wsr_176_encode_fns, 0, 0 }, - { "rsr.208", ICLASS_xt_iclass_rsr_208, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, 0, - Opcode_rsr_208_encode_fns, 0, 0 }, + Opcode_rsr_configid1_encode_fns, 0, 0 }, { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 0, Opcode_rsr_ps_encode_fns, 0, 0 }, @@ -28836,7 +28740,6 @@ enum xtensa_opcode_id { OPCODE_RFE, OPCODE_RFDE, OPCODE_SYSCALL, - OPCODE_SIMCALL, OPCODE_CALL12, OPCODE_CALL8, OPCODE_CALL4, @@ -28931,6 +28834,7 @@ enum xtensa_opcode_id { OPCODE_ABS, OPCODE_NOP, OPCODE_RET, + OPCODE_SIMCALL, OPCODE_S16I, OPCODE_S32I, OPCODE_S8I, @@ -28968,9 +28872,9 @@ enum xtensa_opcode_id { OPCODE_RSR_LITBASE, OPCODE_WSR_LITBASE, OPCODE_XSR_LITBASE, - OPCODE_RSR_176, - OPCODE_WSR_176, - OPCODE_RSR_208, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, OPCODE_RSR_PS, OPCODE_WSR_PS, OPCODE_XSR_PS, @@ -29496,1327 +29400,1252 @@ enum xtensa_opcode_id { static int Slot_inst_decode (const xtensa_insnbuf insn) { - switch (Field_op0_Slot_inst_get (insn)) + if (Field_op0_Slot_inst_get (insn) == 0) { - case 0: - switch (Field_op1_Slot_inst_get (insn)) + if (Field_op1_Slot_inst_get (insn) == 0) { - case 0: - switch (Field_op2_Slot_inst_get (insn)) + if (Field_op2_Slot_inst_get (insn) == 0) { - case 0: - switch (Field_r_Slot_inst_get (insn)) + if (Field_r_Slot_inst_get (insn) == 0) { - case 0: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_n_Slot_inst_get (insn) == 0) - return OPCODE_ILL; - break; - case 2: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return OPCODE_RET; - case 1: - return OPCODE_RETW; - case 2: - return OPCODE_JX; - } - break; - case 3: - switch (Field_n_Slot_inst_get (insn)) - { - case 0: - return OPCODE_CALLX0; - case 1: - return OPCODE_CALLX4; - case 2: - return OPCODE_CALLX8; - case 3: - return OPCODE_CALLX12; - } - break; - } - break; - case 1: - return OPCODE_MOVSP; - case 2: - if (Field_s_Slot_inst_get (insn) == 0) - { - switch (Field_t_Slot_inst_get (insn)) - { - case 0: - return OPCODE_ISYNC; - case 1: - return OPCODE_RSYNC; - case 2: - return OPCODE_ESYNC; - case 3: - return OPCODE_DSYNC; - case 8: - return OPCODE_EXCW; - case 12: - return OPCODE_MEMW; - case 13: - return OPCODE_EXTW; - case 15: - return OPCODE_NOP; - } - } - break; - case 3: - switch (Field_t_Slot_inst_get (insn)) + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) { - case 0: - switch (Field_s_Slot_inst_get (insn)) - { - case 0: - return OPCODE_RFE; - case 2: - return OPCODE_RFDE; - case 4: - return OPCODE_RFWO; - case 5: - return OPCODE_RFWU; - } - break; - case 1: - return OPCODE_RFI; + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; } - break; - case 4: - return OPCODE_BREAK; - case 5: - switch (Field_s_Slot_inst_get (insn)) + if (Field_m_Slot_inst_get (insn) == 3) { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SYSCALL; - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SIMCALL; - break; + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; } - break; - case 6: - return OPCODE_RSIL; - case 7: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_WAITI; - break; - case 8: - return OPCODE_ANY4; - case 9: - return OPCODE_ALL4; - case 10: - return OPCODE_ANY8; - case 11: - return OPCODE_ALL8; } - break; - case 1: - return OPCODE_AND; - case 2: - return OPCODE_OR; - case 3: - return OPCODE_XOR; - case 4: - switch (Field_r_Slot_inst_get (insn)) + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) { - case 0: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSR; - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSL; - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8L; - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SSA8B; - break; - case 4: - if (Field_thi3_Slot_inst_get (insn) == 0) - return OPCODE_SSAI; - break; - case 6: - return OPCODE_RER; - case 7: - return OPCODE_WER; - case 8: if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_ROTW; - break; - case 14: - return OPCODE_NSA; - case 15: - return OPCODE_NSAU; + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } } - break; - case 5: - switch (Field_r_Slot_inst_get (insn)) + if (Field_r_Slot_inst_get (insn) == 3) { - case 1: - return OPCODE_HWWITLBA; - case 3: - return OPCODE_RITLB0; - case 4: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IITLB; - break; - case 5: - return OPCODE_PITLB; - case 6: - return OPCODE_WITLB; - case 7: - return OPCODE_RITLB1; - case 9: - return OPCODE_HWWDTLBA; - case 11: - return OPCODE_RDTLB0; - case 12: if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_IDTLB; - break; - case 13: - return OPCODE_PDTLB; - case 14: - return OPCODE_WDTLB; - case 15: - return OPCODE_RDTLB1; + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; } - break; - case 6: - switch (Field_s_Slot_inst_get (insn)) + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) { - case 0: - return OPCODE_NEG; - case 1: - return OPCODE_ABS; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; } - break; - case 8: - return OPCODE_ADD; - case 9: - return OPCODE_ADDX2; - case 10: - return OPCODE_ADDX4; - case 11: - return OPCODE_ADDX8; - case 12: - return OPCODE_SUB; - case 13: - return OPCODE_SUBX2; - case 14: - return OPCODE_SUBX4; - case 15: - return OPCODE_SUBX8; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; } - break; - case 1: - switch (Field_op2_Slot_inst_get (insn)) + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) { - case 0: - case 1: - return OPCODE_SLLI; - case 2: - case 3: - return OPCODE_SRAI; - case 4: - return OPCODE_SRLI; - case 6: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return OPCODE_XSR_LBEG; - case 1: - return OPCODE_XSR_LEND; - case 2: - return OPCODE_XSR_LCOUNT; - case 3: - return OPCODE_XSR_SAR; - case 4: - return OPCODE_XSR_BR; - case 5: - return OPCODE_XSR_LITBASE; - case 12: - return OPCODE_XSR_SCOMPARE1; - case 72: - return OPCODE_XSR_WINDOWBASE; - case 73: - return OPCODE_XSR_WINDOWSTART; - case 83: - return OPCODE_XSR_PTEVADDR; - case 90: - return OPCODE_XSR_RASID; - case 91: - return OPCODE_XSR_ITLBCFG; - case 92: - return OPCODE_XSR_DTLBCFG; - case 99: - return OPCODE_XSR_ATOMCTL; - case 104: - return OPCODE_XSR_DDR; - case 177: - return OPCODE_XSR_EPC1; - case 178: - return OPCODE_XSR_EPC2; - case 192: - return OPCODE_XSR_DEPC; - case 194: - return OPCODE_XSR_EPS2; - case 209: - return OPCODE_XSR_EXCSAVE1; - case 210: - return OPCODE_XSR_EXCSAVE2; - case 224: - return OPCODE_XSR_CPENABLE; - case 228: - return OPCODE_XSR_INTENABLE; - case 230: - return OPCODE_XSR_PS; - case 231: - return OPCODE_XSR_VECBASE; - case 232: - return OPCODE_XSR_EXCCAUSE; - case 233: - return OPCODE_XSR_DEBUGCAUSE; - case 234: - return OPCODE_XSR_CCOUNT; - case 236: - return OPCODE_XSR_ICOUNT; - case 237: - return OPCODE_XSR_ICOUNTLEVEL; - case 238: - return OPCODE_XSR_EXCVADDR; - case 240: - return OPCODE_XSR_CCOMPARE0; - case 241: - return OPCODE_XSR_CCOMPARE1; - case 244: - return OPCODE_XSR_MISC0; - case 245: - return OPCODE_XSR_MISC1; - } - break; - case 8: - return OPCODE_SRC; - case 9: - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRL; - break; - case 10: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_SLL; - break; - case 11: - if (Field_s_Slot_inst_get (insn) == 0) - return OPCODE_SRA; - break; - case 12: - return OPCODE_MUL16U; - case 13: - return OPCODE_MUL16S; - case 15: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return OPCODE_LICT; - case 1: - return OPCODE_SICT; - case 2: - return OPCODE_LICW; - case 3: - return OPCODE_SICW; - case 8: - return OPCODE_LDCT; - case 9: - return OPCODE_SDCT; - case 14: - if (Field_t_Slot_inst_get (insn) == 0) - return OPCODE_RFDO; - if (Field_t_Slot_inst_get (insn) == 1) - return OPCODE_RFDD; - break; - case 15: - return OPCODE_LDPTE; - } - break; + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; } - break; - case 2: - switch (Field_op2_Slot_inst_get (insn)) + if (Field_op2_Slot_inst_get (insn) == 5) { - case 0: - return OPCODE_ANDB; - case 1: - return OPCODE_ANDBC; - case 2: - return OPCODE_ORB; - case 3: - return OPCODE_ORBC; - case 4: - return OPCODE_XORB; - case 8: - return OPCODE_MULL; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_HWWITLBA; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_HWWDTLBA; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; } - break; - case 3: - switch (Field_op2_Slot_inst_get (insn)) + if (Field_op2_Slot_inst_get (insn) == 6) { - case 0: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return OPCODE_RSR_LBEG; - case 1: - return OPCODE_RSR_LEND; - case 2: - return OPCODE_RSR_LCOUNT; - case 3: - return OPCODE_RSR_SAR; - case 4: - return OPCODE_RSR_BR; - case 5: - return OPCODE_RSR_LITBASE; - case 12: - return OPCODE_RSR_SCOMPARE1; - case 72: - return OPCODE_RSR_WINDOWBASE; - case 73: - return OPCODE_RSR_WINDOWSTART; - case 83: - return OPCODE_RSR_PTEVADDR; - case 90: - return OPCODE_RSR_RASID; - case 91: - return OPCODE_RSR_ITLBCFG; - case 92: - return OPCODE_RSR_DTLBCFG; - case 99: - return OPCODE_RSR_ATOMCTL; - case 104: - return OPCODE_RSR_DDR; - case 176: - return OPCODE_RSR_176; - case 177: - return OPCODE_RSR_EPC1; - case 178: - return OPCODE_RSR_EPC2; - case 192: - return OPCODE_RSR_DEPC; - case 194: - return OPCODE_RSR_EPS2; - case 208: - return OPCODE_RSR_208; - case 209: - return OPCODE_RSR_EXCSAVE1; - case 210: - return OPCODE_RSR_EXCSAVE2; - case 224: - return OPCODE_RSR_CPENABLE; - case 226: - return OPCODE_RSR_INTERRUPT; - case 228: - return OPCODE_RSR_INTENABLE; - case 230: - return OPCODE_RSR_PS; - case 231: - return OPCODE_RSR_VECBASE; - case 232: - return OPCODE_RSR_EXCCAUSE; - case 233: - return OPCODE_RSR_DEBUGCAUSE; - case 234: - return OPCODE_RSR_CCOUNT; - case 235: - return OPCODE_RSR_PRID; - case 236: - return OPCODE_RSR_ICOUNT; - case 237: - return OPCODE_RSR_ICOUNTLEVEL; - case 238: - return OPCODE_RSR_EXCVADDR; - case 240: - return OPCODE_RSR_CCOMPARE0; - case 241: - return OPCODE_RSR_CCOMPARE1; - case 244: - return OPCODE_RSR_MISC0; - case 245: - return OPCODE_RSR_MISC1; - } - break; - case 1: - switch (Field_sr_Slot_inst_get (insn)) - { - case 0: - return OPCODE_WSR_LBEG; - case 1: - return OPCODE_WSR_LEND; - case 2: - return OPCODE_WSR_LCOUNT; - case 3: - return OPCODE_WSR_SAR; - case 4: - return OPCODE_WSR_BR; - case 5: - return OPCODE_WSR_LITBASE; - case 12: - return OPCODE_WSR_SCOMPARE1; - case 72: - return OPCODE_WSR_WINDOWBASE; - case 73: - return OPCODE_WSR_WINDOWSTART; - case 83: - return OPCODE_WSR_PTEVADDR; - case 90: - return OPCODE_WSR_RASID; - case 91: - return OPCODE_WSR_ITLBCFG; - case 92: - return OPCODE_WSR_DTLBCFG; - case 99: - return OPCODE_WSR_ATOMCTL; - case 104: - return OPCODE_WSR_DDR; - case 176: - return OPCODE_WSR_176; - case 177: - return OPCODE_WSR_EPC1; - case 178: - return OPCODE_WSR_EPC2; - case 192: - return OPCODE_WSR_DEPC; - case 194: - return OPCODE_WSR_EPS2; - case 209: - return OPCODE_WSR_EXCSAVE1; - case 210: - return OPCODE_WSR_EXCSAVE2; - case 224: - return OPCODE_WSR_CPENABLE; - case 226: - return OPCODE_WSR_INTSET; - case 227: - return OPCODE_WSR_INTCLEAR; - case 228: - return OPCODE_WSR_INTENABLE; - case 230: - return OPCODE_WSR_PS; - case 231: - return OPCODE_WSR_VECBASE; - case 232: - return OPCODE_WSR_EXCCAUSE; - case 233: - return OPCODE_WSR_DEBUGCAUSE; - case 234: - return OPCODE_WSR_CCOUNT; - case 236: - return OPCODE_WSR_ICOUNT; - case 237: - return OPCODE_WSR_ICOUNTLEVEL; - case 238: - return OPCODE_WSR_EXCVADDR; - case 240: - return OPCODE_WSR_CCOMPARE0; - case 241: - return OPCODE_WSR_CCOMPARE1; - case 244: - return OPCODE_WSR_MISC0; - case 245: - return OPCODE_WSR_MISC1; - } - break; - case 2: - return OPCODE_SEXT; - case 3: - return OPCODE_CLAMPS; - case 4: - return OPCODE_MIN; - case 5: - return OPCODE_MAX; - case 6: - return OPCODE_MINU; - case 7: - return OPCODE_MAXU; - case 8: - return OPCODE_MOVEQZ; - case 9: - return OPCODE_MOVNEZ; - case 10: - return OPCODE_MOVLTZ; - case 11: - return OPCODE_MOVGEZ; - case 12: - return OPCODE_MOVF; - case 13: - return OPCODE_MOVT; - case 14: - switch (Field_st_Slot_inst_get (insn)) - { - case 231: - return OPCODE_RUR_THREADPTR; - case 240: - return OPCODE_RUR_AE_OVF_SAR; - case 241: - return OPCODE_RUR_AE_BITHEAD; - case 242: - return OPCODE_RUR_AE_TS_FTS_BU_BP; - case 243: - return OPCODE_RUR_AE_SD_NO; - } - break; - case 15: - switch (Field_sr_Slot_inst_get (insn)) - { - case 231: - return OPCODE_WUR_THREADPTR; - case 240: - return OPCODE_WUR_AE_OVF_SAR; - case 241: - return OPCODE_WUR_AE_BITHEAD; - case 242: - return OPCODE_WUR_AE_TS_FTS_BU_BP; - case 243: - return OPCODE_WUR_AE_SD_NO; - } - break; - } - break; - case 4: - case 5: - return OPCODE_EXTUI; - case 9: - switch (Field_op2_Slot_inst_get (insn)) - { - case 0: - return OPCODE_L32E; - case 4: - return OPCODE_S32E; + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; } - break; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; } - break; - case 1: - return OPCODE_L32R; - case 2: - switch (Field_r_Slot_inst_get (insn)) + if (Field_op1_Slot_inst_get (insn) == 1) { - case 0: - return OPCODE_L8UI; - case 1: - return OPCODE_L16UI; - case 2: - return OPCODE_L32I; - case 4: - return OPCODE_S8I; - case 5: - return OPCODE_S16I; - case 6: - return OPCODE_S32I; - case 7: - switch (Field_t_Slot_inst_get (insn)) + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) { - case 0: - return OPCODE_DPFR; - case 1: - return OPCODE_DPFW; - case 2: - return OPCODE_DPFRO; - case 3: - return OPCODE_DPFWO; - case 4: - return OPCODE_DHWB; - case 5: - return OPCODE_DHWBI; - case 6: - return OPCODE_DHI; - case 7: - return OPCODE_DII; - case 8: - switch (Field_op1_Slot_inst_get (insn)) - { - case 4: - return OPCODE_DIWB; - case 5: - return OPCODE_DIWBI; - } - break; - case 12: - return OPCODE_IPF; - case 14: - return OPCODE_IHI; - case 15: - return OPCODE_III; + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_XSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_XSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_XSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_XSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_LDPTE; } - break; - case 9: - return OPCODE_L16SI; - case 10: - return OPCODE_MOVI; - case 11: - return OPCODE_L32AI; - case 12: - return OPCODE_ADDI; - case 13: - return OPCODE_ADDMI; - case 14: - return OPCODE_S32C1I; - case 15: - return OPCODE_S32RI; - } - break; - case 4: - switch (Field_ae_r10_Slot_inst_get (insn)) - { - case 0: - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_I; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_X; - break; - case 1: - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_I; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_X; - break; - case 2: - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_IU; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ56_XU; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_CVTQ48A32S; - break; - case 3: - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_IU; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LQ32F_XU; - break; - } - switch (Field_ae_r3_Slot_inst_get (insn)) - { - case 0: - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_I; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_IU; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_X; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16F_XU; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_I; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_IU; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24F_X; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24F_XU; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_I; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_IU; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2F_X; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2F_XU; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_I; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_IU; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_X; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16X2F_XU; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_I; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_IU; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_X; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2F_XU; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_I; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_IU; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_X; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24S_L_XU; - if (Field_ae_s3_Slot_inst_get (insn) == 0 && - Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVP48; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVPA24X2; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_L; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LL; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HL; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_L; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_L; - break; - case 1: - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_I; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_IU; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_X; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24_XU; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_I; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_IU; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP16X2F_X; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP16X2F_XU; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_I; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_IU; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LP24X2_X; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_LP24X2_XU; - if (Field_op1_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_I; - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_IU; - if (Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_X; - if (Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24X2S_XU; - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_I; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_IU; - if (Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_X; - if (Field_op1_Slot_inst_get (insn) == 12 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP16F_L_XU; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_I; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_IU; - if (Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_X; - if (Field_op1_Slot_inst_get (insn) == 13 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_SP24F_L_XU; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCP24A32X2; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 11 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_CVTA32P24_H; - if (Field_op1_Slot_inst_get (insn) == 14 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_LH; - if (Field_op1_Slot_inst_get (insn) == 15 && - Field_op2_Slot_inst_get (insn) == 11) - return OPCODE_AE_CVTP24A16X2_HH; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 7 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVAP24S_H; - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 8 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_TRUNCA16P24S_H; - break; - } - switch (Field_ae_r32_Slot_inst_get (insn)) - { - case 0: - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_I; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_X; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_TRUNCA32Q48; - break; - case 1: - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_I; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_X; - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_NSAQ56S; - break; - case 2: - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_IU; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ56S_XU; - break; - case 3: - if (Field_op1_Slot_inst_get (insn) == 3 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_IU; - if (Field_op1_Slot_inst_get (insn) == 4 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SQ32F_XU; - break; } - switch (Field_ae_s_non_samt_Slot_inst_get (insn)) + if (Field_op1_Slot_inst_get (insn) == 2) { - case 0: - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLIQ56; - break; - case 1: - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLIQ56; - break; - case 2: - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRAIQ56; - break; - case 3: - if (Field_op1_Slot_inst_get (insn) == 5 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLISQ56S; - break; + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; } - switch (Field_op1_Slot_inst_get (insn)) + if (Field_op1_Slot_inst_get (insn) == 3) { - case 0: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SHA32; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL32T; - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLAQ56; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLDL16T; - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRLAQ56; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_LBK; - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SRAAQ56; - if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL32T; - break; - case 4: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SLLASQ56S; + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_RSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_RSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_RSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 5) + return OPCODE_WSR_LITBASE; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_WSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_WSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; if (Field_op2_Slot_inst_get (insn) == 10) - return OPCODE_AE_VLEL16T; - break; - case 5: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVTQ56; - break; - case 6: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_MOVFQ56; - break; + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 240) + return OPCODE_RUR_AE_OVF_SAR; + if (Field_st_Slot_inst_get (insn) == 241) + return OPCODE_RUR_AE_BITHEAD; + if (Field_st_Slot_inst_get (insn) == 242) + return OPCODE_RUR_AE_TS_FTS_BU_BP; + if (Field_st_Slot_inst_get (insn) == 243) + return OPCODE_RUR_AE_SD_NO; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WUR_AE_OVF_SAR; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WUR_AE_BITHEAD; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WUR_AE_TS_FTS_BU_BP; + if (Field_sr_Slot_inst_get (insn) == 243) + return OPCODE_WUR_AE_SD_NO; + } } - switch (Field_r_Slot_inst_get (insn)) + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 9) { - case 0: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_OVERFLOW; - if (Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SBI; - break; - case 1: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SAR; - if (Field_op1_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DB; - if (Field_op1_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_SB; - break; - case 2: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITPTR; - break; - case 3: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_BITSUSED; - break; - case 4: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_TABLESIZE; - break; - case 5: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_FIRST_TS; - break; - case 6: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_NEXTOFFSET; - break; - case 7: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_WUR_AE_SEARCHDONE; - break; - case 8: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 10 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_VLDSHT; - break; - case 12: - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLES16C; - break; - case 13: - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_SBF; - break; - case 14: - if (Field_op1_Slot_inst_get (insn) == 7 && - Field_t_Slot_inst_get (insn) == 1 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_VLDL16C; - break; + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; } - switch (Field_s_Slot_inst_get (insn)) + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) { - case 0: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSQ56; - if (Field_op1_Slot_inst_get (insn) == 6 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_LB; - break; - case 1: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRLSQ56; - break; - case 2: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SRASQ56; - break; - case 3: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_SLLSSQ56S; - break; - case 4: - if (Field_t_Slot_inst_get (insn) == 1 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_AE_MOVQ56; - break; - case 8: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_OVERFLOW; - break; - case 9: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SAR; - break; - case 10: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITPTR; - break; - case 11: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_BITSUSED; - break; - case 12: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_TABLESIZE; - break; - case 13: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_FIRST_TS; - break; - case 14: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_NEXTOFFSET; - break; - case 15: - if (Field_t_Slot_inst_get (insn) == 0 && - Field_op1_Slot_inst_get (insn) == 9 && - Field_op2_Slot_inst_get (insn) == 12) - return OPCODE_RUR_AE_SEARCHDONE; - break; + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; } - switch (Field_t_Slot_inst_get (insn)) + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_ae_r10_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_I; + if (Field_ae_r10_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_X; + if (Field_ae_r10_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_I; + if (Field_ae_r10_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_X; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_IU; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ56_XU; + if (Field_ae_r10_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_CVTQ48A32S; + if (Field_ae_r10_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_IU; + if (Field_ae_r10_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LQ32F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24S_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_ae_s3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVP48; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVPA24X2; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_CVTA32P24_L; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_LL; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_HL; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAP24S_L; + if (Field_ae_r3_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCA16P24S_L; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP16X2F_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP16X2F_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LP24X2_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_LP24X2_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24X2S_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 12 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP16F_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_I; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_IU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_X; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 13 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_SP24F_L_XU; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCP24A32X2; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 11 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_CVTA32P24_H; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 14 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_LH; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_AE_CVTP24A16X2_HH; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVAP24S_H; + if (Field_ae_r3_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 8 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_TRUNCA16P24S_H; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_I; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_X; + if (Field_ae_r32_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_TRUNCA32Q48; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_I; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_X; + if (Field_ae_r32_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_NSAQ56S; + if (Field_ae_r32_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_IU; + if (Field_ae_r32_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ56S_XU; + if (Field_ae_r32_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_IU; + if (Field_ae_r32_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SQ32F_XU; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRLIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRAIQ56; + if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && + Field_op1_Slot_inst_get (insn) == 5 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLISQ56S; + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SHA32; + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLDL32T; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SLLAQ56; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLDL16T; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRLAQ56; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_LBK; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SRAAQ56; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLEL32T; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SLLASQ56S; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_AE_VLEL16T; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_MOVTQ56; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_MOVFQ56; + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_OVERFLOW; + if (Field_r_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_SBI; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_SAR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_DB; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_SB; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_BITPTR; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_BITSUSED; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_TABLESIZE; + if (Field_r_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_FIRST_TS; + if (Field_r_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_NEXTOFFSET; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_WUR_AE_SEARCHDONE; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 10 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_VLDSHT; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLES16C; + if (Field_r_Slot_inst_get (insn) == 13 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_SBF; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_op1_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_VLDL16C; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLSQ56; + if (Field_s_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 6 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_LB; + if (Field_s_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRLSQ56; + if (Field_s_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SRASQ56; + if (Field_s_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_SLLSSQ56S; + if (Field_s_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 1 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_AE_MOVQ56; + if (Field_s_Slot_inst_get (insn) == 8 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_OVERFLOW; + if (Field_s_Slot_inst_get (insn) == 9 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SAR; + if (Field_s_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_BITPTR; + if (Field_s_Slot_inst_get (insn) == 11 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_BITSUSED; + if (Field_s_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_TABLESIZE; + if (Field_s_Slot_inst_get (insn) == 13 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_FIRST_TS; + if (Field_s_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_NEXTOFFSET; + if (Field_s_Slot_inst_get (insn) == 15 && + Field_t_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 9 && + Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_RUR_AE_SEARCHDONE; + if (Field_t_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBKI; + if (Field_t_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_AE_DBI; + if (Field_t_Slot_inst_get (insn) == 2 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_AE_LBI; + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) { - case 0: - if (Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBKI; - if (Field_r_Slot_inst_get (insn) == 2 && - Field_op2_Slot_inst_get (insn) == 15) - return OPCODE_AE_DBI; - break; - case 2: - if (Field_s_Slot_inst_get (insn) == 0 && - Field_op2_Slot_inst_get (insn) == 14) - return OPCODE_AE_LBI; - break; + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; } - break; - case 5: - switch (Field_n_Slot_inst_get (insn)) + if (Field_n_Slot_inst_get (insn) == 2) { - case 0: - return OPCODE_CALL0; - case 1: - return OPCODE_CALL4; - case 2: - return OPCODE_CALL8; - case 3: - return OPCODE_CALL12; + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; } - break; - case 6: - switch (Field_n_Slot_inst_get (insn)) + if (Field_n_Slot_inst_get (insn) == 3) { - case 0: - return OPCODE_J; - case 1: - switch (Field_m_Slot_inst_get (insn)) + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) { - case 0: - return OPCODE_BEQZ; - case 1: - return OPCODE_BNEZ; - case 2: - return OPCODE_BLTZ; - case 3: - return OPCODE_BGEZ; + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; } - break; - case 2: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return OPCODE_BEQI; - case 1: - return OPCODE_BNEI; - case 2: - return OPCODE_BLTI; - case 3: - return OPCODE_BGEI; - } - break; - case 3: - switch (Field_m_Slot_inst_get (insn)) - { - case 0: - return OPCODE_ENTRY; - case 1: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return OPCODE_BF; - case 1: - return OPCODE_BT; - case 8: - return OPCODE_LOOP; - case 9: - return OPCODE_LOOPNEZ; - case 10: - return OPCODE_LOOPGTZ; - } - break; - case 2: - return OPCODE_BLTUI; - case 3: - return OPCODE_BGEUI; - } - break; - } - break; - case 7: - switch (Field_r_Slot_inst_get (insn)) - { - case 0: - return OPCODE_BNONE; - case 1: - return OPCODE_BEQ; - case 2: - return OPCODE_BLT; - case 3: - return OPCODE_BLTU; - case 4: - return OPCODE_BALL; - case 5: - return OPCODE_BBC; - case 6: - case 7: - return OPCODE_BBCI; - case 8: - return OPCODE_BANY; - case 9: - return OPCODE_BNE; - case 10: - return OPCODE_BGE; - case 11: - return OPCODE_BGEU; - case 12: - return OPCODE_BNALL; - case 13: - return OPCODE_BBS; - case 14: - case 15: - return OPCODE_BBSI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; } - break; + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; } return XTENSA_UNDEFINED; } @@ -30824,50 +30653,37 @@ Slot_inst_decode (const xtensa_insnbuf insn) static int Slot_inst16b_decode (const xtensa_insnbuf insn) { - switch (Field_op0_Slot_inst16b_get (insn)) + if (Field_op0_Slot_inst16b_get (insn) == 12) { - case 12: - switch (Field_i_Slot_inst16b_get (insn)) + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) { - case 0: - return OPCODE_MOVI_N; - case 1: - switch (Field_z_Slot_inst16b_get (insn)) - { - case 0: - return OPCODE_BEQZ_N; - case 1: - return OPCODE_BNEZ_N; - } - break; + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; } - break; - case 13: - switch (Field_r_Slot_inst16b_get (insn)) + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) { - case 0: - return OPCODE_MOV_N; - case 15: - switch (Field_t_Slot_inst16b_get (insn)) - { - case 0: - return OPCODE_RET_N; - case 1: - return OPCODE_RETW_N; - case 2: - return OPCODE_BREAK_N; - case 3: - if (Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_NOP_N; - break; - case 6: - if (Field_s_Slot_inst16b_get (insn) == 0) - return OPCODE_ILL_N; - break; - } - break; + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; } - break; } return XTENSA_UNDEFINED; } @@ -30875,17 +30691,14 @@ Slot_inst16b_decode (const xtensa_insnbuf insn) static int Slot_inst16a_decode (const xtensa_insnbuf insn) { - switch (Field_op0_Slot_inst16a_get (insn)) - { - case 8: - return OPCODE_L32I_N; - case 9: - return OPCODE_S32I_N; - case 10: - return OPCODE_ADD_N; - case 11: - return OPCODE_ADDI_N; - } + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; return XTENSA_UNDEFINED; } @@ -30898,45 +30711,31 @@ Slot_ae_slot0_decode (const xtensa_insnbuf insn) if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && Field_op0_s4_Slot_ae_slot0_get (insn) == 1) return OPCODE_EXTUI; - switch (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn)) - { - case 6: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BGEZ; - break; - case 7: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BLTZ; - break; - case 8: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BEQZ; - break; - case 9: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_BNEZ; - break; - case 10: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVI; - break; - } - switch (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn)) - { - case 88: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRAI; - break; - case 96: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SLLI; - break; - case 123: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVTQ56; - break; - } + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BGEZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BLTZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BEQZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRAI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SLLI; + if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVTQ56; if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 && Field_op0_s4_Slot_ae_slot0_get (insn) == 1) return OPCODE_AE_CVTP24A16X2_HH; @@ -31160,17 +30959,12 @@ Slot_ae_slot0_decode (const xtensa_insnbuf insn) Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && Field_s_Slot_ae_slot0_get (insn) == 0) return OPCODE_ALL8; - switch (Field_ftsf293_Slot_ae_slot0_get (insn)) - { - case 0: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBCI; - break; - case 1: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBSI; - break; - } + if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBCI; + if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBSI; if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 && Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && Field_s_Slot_ae_slot0_get (insn) == 0) @@ -31188,57 +30982,38 @@ Slot_ae_slot0_decode (const xtensa_insnbuf insn) if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 && Field_op0_s4_Slot_ae_slot0_get (insn) == 1) return OPCODE_AE_SQ56S_IU; - switch (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn)) - { - case 964: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLIQ56; - break; - case 965: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRAIQ56; - break; - case 966: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SRLIQ56; - break; - case 968: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AE_SLLISQ56S; - break; - } - switch (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn)) - { - case 3868: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ABS; - break; - case 3869: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_NEG; - break; - case 3870: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRA; - break; - case 3871: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRL; - break; - } - switch (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn)) - { - case 7752: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf321_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_MOVP48; - break; - case 7753: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ftsf353_Slot_ae_slot0_get (insn) == 0) - return OPCODE_ANY4; - break; - } + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLIQ56; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRAIQ56; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SRLIQ56; + if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AE_SLLISQ56S; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf321_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_MOVP48; + if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ftsf353_Slot_ae_slot0_get (insn) == 0) + return OPCODE_ANY4; if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 && Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && Field_ftsf321_Slot_ae_slot0_get (insn) == 0) @@ -31328,239 +31103,181 @@ Slot_ae_slot0_decode (const xtensa_insnbuf insn) Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0) return OPCODE_AE_SQ32F_XU; - switch (Field_imm8_Slot_ae_slot0_get (insn)) - { - case 178: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADD; - break; - case 179: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX8; - break; - case 180: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX2; - break; - case 181: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_AND; - break; - case 182: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDB; - break; - case 183: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ANDBC; - break; - case 184: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ADDX4; - break; - case 185: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_CLAMPS; - break; - case 186: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAX; - break; - case 187: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MIN; - break; - case 188: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MAXU; - break; - case 189: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MINU; - break; - case 190: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVEQZ; - break; - case 191: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVF; - break; - case 194: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVGEZ; - break; - case 195: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORB; - break; - case 196: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVLTZ; - break; - case 197: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_ORBC; - break; - case 198: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SEXT; - break; - case 199: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRC; - break; - case 200: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVNEZ; - break; - case 201: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SRLI; - break; - case 202: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUB; - break; - case 203: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX4; - break; - case 204: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX2; - break; - case 205: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_SUBX8; - break; - case 206: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XOR; - break; - case 207: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_XORB; - break; - case 208: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_MOVT; - break; - case 224: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1) - return OPCODE_OR; - break; - case 244: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && - Field_ae_r32_Slot_ae_slot0_get (insn) == 0) - return OPCODE_AE_SQ32F_X; - break; - } + if (Field_imm8_Slot_ae_slot0_get (insn) == 178 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADD; + if (Field_imm8_Slot_ae_slot0_get (insn) == 179 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX8; + if (Field_imm8_Slot_ae_slot0_get (insn) == 180 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX2; + if (Field_imm8_Slot_ae_slot0_get (insn) == 181 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_imm8_Slot_ae_slot0_get (insn) == 182 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANDB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 184 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ADDX4; + if (Field_imm8_Slot_ae_slot0_get (insn) == 185 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_CLAMPS; + if (Field_imm8_Slot_ae_slot0_get (insn) == 186 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAX; + if (Field_imm8_Slot_ae_slot0_get (insn) == 187 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MIN; + if (Field_imm8_Slot_ae_slot0_get (insn) == 188 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MAXU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 189 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MINU; + if (Field_imm8_Slot_ae_slot0_get (insn) == 190 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVEQZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 191 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVF; + if (Field_imm8_Slot_ae_slot0_get (insn) == 194 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVGEZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 195 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ORB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 196 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVLTZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 197 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_ORBC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 198 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SEXT; + if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRC; + if (Field_imm8_Slot_ae_slot0_get (insn) == 200 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVNEZ; + if (Field_imm8_Slot_ae_slot0_get (insn) == 201 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SRLI; + if (Field_imm8_Slot_ae_slot0_get (insn) == 202 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 203 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX4; + if (Field_imm8_Slot_ae_slot0_get (insn) == 204 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX2; + if (Field_imm8_Slot_ae_slot0_get (insn) == 205 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_SUBX8; + if (Field_imm8_Slot_ae_slot0_get (insn) == 206 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_XOR; + if (Field_imm8_Slot_ae_slot0_get (insn) == 207 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_XORB; + if (Field_imm8_Slot_ae_slot0_get (insn) == 208 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_MOVT; + if (Field_imm8_Slot_ae_slot0_get (insn) == 224 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1) + return OPCODE_OR; + if (Field_imm8_Slot_ae_slot0_get (insn) == 244 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && + Field_ae_r32_Slot_ae_slot0_get (insn) == 0) + return OPCODE_AE_SQ32F_X; if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) return OPCODE_L32R; - switch (Field_r_Slot_ae_slot0_get (insn)) - { - case 0: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNE; - break; - case 1: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_BNONE; - break; - case 2: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16SI; - break; - case 3: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L8UI; - break; - case 4: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDI; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_L16UI; - break; - case 5: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BALL; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S16I; - break; - case 6: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BANY; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S32I; - break; - case 7: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBC; - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4) - return OPCODE_S8I; - break; - case 8: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_ADDMI; - break; - case 9: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BBS; - break; - case 10: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BEQ; - break; - case 11: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGEU; - break; - case 12: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BGE; - break; - case 13: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLT; - break; - case 14: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BLTU; - break; - case 15: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2) - return OPCODE_BNALL; - break; - } - switch (Field_t_Slot_ae_slot0_get (insn)) - { - case 0: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BEQI; - break; - case 1: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEI; - break; - case 2: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BGEUI; - break; - case 3: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BNEI; - break; - case 4: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3) - return OPCODE_BLTI; - break; - case 5: - if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && - Field_r_Slot_ae_slot0_get (insn) == 0) - return OPCODE_BF; - break; - } + if (Field_r_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_BNE; + if (Field_r_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_BNONE; + if (Field_r_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16SI; + if (Field_r_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L8UI; + if (Field_r_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDI; + if (Field_r_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_L16UI; + if (Field_r_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BALL; + if (Field_r_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S16I; + if (Field_r_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BANY; + if (Field_r_Slot_ae_slot0_get (insn) == 6 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S32I; + if (Field_r_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBC; + if (Field_r_Slot_ae_slot0_get (insn) == 7 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_ae_slot0_get (insn) == 8 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_ADDMI; + if (Field_r_Slot_ae_slot0_get (insn) == 9 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BBS; + if (Field_r_Slot_ae_slot0_get (insn) == 10 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BEQ; + if (Field_r_Slot_ae_slot0_get (insn) == 11 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BGEU; + if (Field_r_Slot_ae_slot0_get (insn) == 12 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BGE; + if (Field_r_Slot_ae_slot0_get (insn) == 13 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_ae_slot0_get (insn) == 14 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BLTU; + if (Field_r_Slot_ae_slot0_get (insn) == 15 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 2) + return OPCODE_BNALL; + if (Field_t_Slot_ae_slot0_get (insn) == 0 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BEQI; + if (Field_t_Slot_ae_slot0_get (insn) == 1 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BGEI; + if (Field_t_Slot_ae_slot0_get (insn) == 2 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BGEUI; + if (Field_t_Slot_ae_slot0_get (insn) == 3 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BNEI; + if (Field_t_Slot_ae_slot0_get (insn) == 4 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3) + return OPCODE_BLTI; + if (Field_t_Slot_ae_slot0_get (insn) == 5 && + Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && + Field_r_Slot_ae_slot0_get (insn) == 0) + return OPCODE_BF; return XTENSA_UNDEFINED; } @@ -31958,21 +31675,15 @@ Slot_ae_slot1_decode (const xtensa_insnbuf insn) if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 && Field_op0_s3_Slot_ae_slot1_get (insn) == 1) return OPCODE_AE_SUBP24; - switch (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn)) - { - case 8: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SLLIP24; - break; - case 9: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRAIP24; - break; - case 10: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1) - return OPCODE_AE_SRLIP24; - break; - } + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SLLIP24; + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRAIP24; + if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 1) + return OPCODE_AE_SRLIP24; if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 && Field_op0_s3_Slot_ae_slot1_get (insn) == 1) return OPCODE_AE_MULAFQ32SP16S_L; @@ -32148,137 +31859,150 @@ Slot_ae_slot1_decode (const xtensa_insnbuf insn) Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && Field_ae_r20_Slot_ae_slot1_get (insn) == 0) return OPCODE_AE_ABSP24; - switch (Field_t_Slot_ae_slot1_get (insn)) - { - case 0: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16S_LL; - break; - case 1: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASFQ32SP16U_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_HH; - break; - case 2: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16S_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LH; - break; - case 3: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LH; - break; - case 4: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSAQ32SP16U_LL; - break; - case 5: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_LL; - break; - case 6: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16U_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_HH; - break; - case 7: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16S_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LH; - break; - case 8: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAFQ32SP16U_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZASQ32SP16S_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16S_HH; - break; - case 9: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSFQ32SP16U_LL; - break; - case 10: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16S_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_HH; - break; - case 11: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LL; - break; - case 12: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZAAQ32SP16U_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16S_LH; - break; - case 13: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAFQ32SP16U_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_HH; - break; - case 14: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16S_LL; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LH; - break; - case 15: - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2) - return OPCODE_AE_MULZASFQ32SP16U_HH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3) - return OPCODE_AE_MULZSAQ32SP16S_LH; - if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4) - return OPCODE_AE_MULZSSQ32SP16U_LL; - break; - } + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 0 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 1 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 2 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 3 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 4 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSAQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 5 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 6 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 7 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZASQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 8 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 9 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 10 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 11 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZAAQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 12 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAFQ32SP16U_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 13 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16S_LL; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAQ32SP16S_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 14 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 2) + return OPCODE_AE_MULZASFQ32SP16U_HH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 3) + return OPCODE_AE_MULZSAQ32SP16S_LH; + if (Field_t_Slot_ae_slot1_get (insn) == 15 && + Field_op0_s3_Slot_ae_slot1_get (insn) == 4) + return OPCODE_AE_MULZSSQ32SP16U_LL; return XTENSA_UNDEFINED; } @@ -32418,6 +32142,8 @@ Slot_inst_get_field_fns[] = { Field_ae_r20_Slot_inst_get, Field_ae_r10_Slot_inst_get, Field_ae_s20_Slot_inst_get, + Field_ae_fld_ohba_Slot_inst_get, + Field_ae_fld_ohba2_Slot_inst_get, 0, Field_ftsf12_Slot_inst_get, Field_ftsf13_Slot_inst_get, @@ -32809,6 +32535,8 @@ Slot_inst_set_field_fns[] = { Field_ae_r20_Slot_inst_set, Field_ae_r10_Slot_inst_set, Field_ae_s20_Slot_inst_set, + Field_ae_fld_ohba_Slot_inst_set, + Field_ae_fld_ohba2_Slot_inst_set, 0, Field_ftsf12_Slot_inst_set, Field_ftsf13_Slot_inst_set, @@ -33525,6 +33253,8 @@ Slot_inst16a_get_field_fns[] = { 0, 0, 0, + 0, + 0, Implicit_Field_ar0_get, Implicit_Field_ar4_get, Implicit_Field_ar8_get, @@ -33916,6 +33646,8 @@ Slot_inst16a_set_field_fns[] = { 0, 0, 0, + 0, + 0, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, @@ -34307,6 +34039,8 @@ Slot_inst16b_get_field_fns[] = { 0, 0, 0, + 0, + 0, Implicit_Field_ar0_get, Implicit_Field_ar4_get, Implicit_Field_ar8_get, @@ -34698,6 +34432,8 @@ Slot_inst16b_set_field_fns[] = { 0, 0, 0, + 0, + 0, Implicit_Field_set, Implicit_Field_set, Implicit_Field_set, @@ -34764,6 +34500,8 @@ Slot_ae_slot1_get_field_fns[] = { Field_ae_r20_Slot_ae_slot1_get, Field_ae_r10_Slot_ae_slot1_get, Field_ae_s20_Slot_ae_slot1_get, + 0, + 0, Field_op0_s3_Slot_ae_slot1_get, Field_ftsf12_Slot_ae_slot1_get, Field_ftsf13_Slot_ae_slot1_get, @@ -35155,6 +34893,8 @@ Slot_ae_slot1_set_field_fns[] = { Field_ae_r20_Slot_ae_slot1_set, Field_ae_r10_Slot_ae_slot1_set, Field_ae_s20_Slot_ae_slot1_set, + 0, + 0, Field_op0_s3_Slot_ae_slot1_set, Field_ftsf12_Slot_ae_slot1_set, Field_ftsf13_Slot_ae_slot1_set, @@ -35745,6 +35485,8 @@ Slot_ae_slot0_get_field_fns[] = { 0, 0, 0, + 0, + 0, Field_op0_s4_Slot_ae_slot0_get, Field_ftsf212ae_slot0_Slot_ae_slot0_get, Field_ftsf213ae_slot0_Slot_ae_slot0_get, @@ -36136,6 +35878,8 @@ Slot_ae_slot0_set_field_fns[] = { 0, 0, 0, + 0, + 0, Field_op0_s4_Slot_ae_slot0_set, Field_ftsf212ae_slot0_Slot_ae_slot0_set, Field_ftsf213ae_slot0_Slot_ae_slot0_set, @@ -36356,7 +36100,247 @@ format_decoder (const xtensa_insnbuf insn) return -1; } -static int length_table[16] = { +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8, 3, 3, 3, @@ -36378,8 +36362,8 @@ static int length_table[16] = { static int length_decoder (const unsigned char *insn) { - int op0 = insn[0] & 0xf; - return length_table[op0]; + int l = insn[0]; + return length_table[l]; } @@ -36390,8 +36374,8 @@ xtensa_isa_internal xtensa_modules = { 8 /* insn_size */, 0, 4, formats, format_decoder, length_decoder, 5, slots, - 387 /* num_fields */, - 445, operands, + 389 /* num_fields */, + 454, operands, 588, iclasses, 656, opcodes, 0, 8, regfiles, |