diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/vfp_helper.c | 2 | ||||
| -rw-r--r-- | target/i386/tcg/fpu_helper.c | 2 | ||||
| -rw-r--r-- | target/m68k/fpu_helper.c | 2 | ||||
| -rw-r--r-- | target/mips/tcg/msa_helper.c | 2 | ||||
| -rw-r--r-- | target/rx/op_helper.c | 2 | ||||
| -rw-r--r-- | target/tricore/fpu_helper.c | 6 |
6 files changed, 8 insertions, 8 deletions
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 444702a460..3c8f3e6588 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -47,7 +47,7 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits) if (host_bits & float_flag_overflow) { target_bits |= FPSR_OFC; } - if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { + if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) { target_bits |= FPSR_UFC; } if (host_bits & float_flag_inexact) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 9c33ac7898..3d764bc138 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -3268,7 +3268,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env) (flags & float_flag_overflow ? FPUS_OE : 0) | (flags & float_flag_underflow ? FPUS_UE : 0) | (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE : + (flags & float_flag_output_denormal_flushed ? FPUS_UE | FPUS_PE : 0)); } diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index e3f4a18850..339b73ad7d 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -175,7 +175,7 @@ static int cpu_m68k_exceptbits_from_host(int host_bits) if (host_bits & float_flag_overflow) { target_bits |= 0x40; } - if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { + if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) { target_bits |= 0x20; } if (host_bits & float_flag_divbyzero) { diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index aeab6a1d8b..ec38d9fde5 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -6241,7 +6241,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) } /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */ - if ((ieee_exception_flags & float_flag_output_denormal) && + if ((ieee_exception_flags & float_flag_output_denormal_flushed) && (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { mips_exception_flags |= FP_INEXACT; if (action & CLEAR_FS_UNDERFLOW) { diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 59dd1ae612..b3ed822dd1 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -100,7 +100,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr) SET_FPSW(X); } if ((xcpt & (float_flag_input_denormal_flushed - | float_flag_output_denormal)) + | float_flag_output_denormal_flushed)) && !FIELD_EX32(env->fpsw, FPSW, DN)) { env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1); } diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index 5d38aea143..1b72dcc5f5 100644 --- a/target/tricore/fpu_helper.c +++ b/target/tricore/fpu_helper.c @@ -43,7 +43,7 @@ static inline uint8_t f_get_excp_flags(CPUTriCoreState *env) & (float_flag_invalid | float_flag_overflow | float_flag_underflow - | float_flag_output_denormal + | float_flag_output_denormal_flushed | float_flag_divbyzero | float_flag_inexact); } @@ -99,7 +99,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags) some_excp = 1; } - if (flags & float_flag_underflow || flags & float_flag_output_denormal) { + if (flags & float_flag_underflow || flags & float_flag_output_denormal_flushed) { env->FPU_FU = 1 << 31; some_excp = 1; } @@ -109,7 +109,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags) some_excp = 1; } - if (flags & float_flag_inexact || flags & float_flag_output_denormal) { + if (flags & float_flag_inexact || flags & float_flag_output_denormal_flushed) { env->PSW |= 1 << 26; some_excp = 1; } |