diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 7 | ||||
| -rw-r--r-- | target/arm/helper.c | 1 | ||||
| -rw-r--r-- | target/i386/kvm.c | 10 | ||||
| -rw-r--r-- | target/mips/msa_helper.c | 74 | ||||
| -rw-r--r-- | target/mips/translate.c | 2 |
5 files changed, 87 insertions, 7 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1959467fdc..9eb40ff755 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1369,6 +1369,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * There exist AArch64 cpus without AArch32 support. When KVM * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. + * As a general principle, we also do not make ID register + * consistency checks anywhere unless using TCG, because only + * for TCG would a consistency-check failure be a QEMU bug. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); @@ -1383,7 +1386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -1409,7 +1412,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); + assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 20f8728be1..b74c23a9bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7956,6 +7956,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) break; case EXCP_HYP_TRAP: addr = 0x14; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } diff --git a/target/i386/kvm.c b/target/i386/kvm.c index ada89d27cc..dbbb13772a 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -3563,12 +3563,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level) assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); - ret = kvm_put_nested_state(x86_cpu); - if (ret < 0) { - return ret; - } - if (level >= KVM_PUT_RESET_STATE) { + ret = kvm_put_nested_state(x86_cpu); + if (ret < 0) { + return ret; + } + ret = kvm_put_msr_feature_control(x86_cpu); if (ret < 0) { return ret; diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index a383c40ece..a5a86572b4 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -2113,6 +2113,24 @@ void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, switch (df) { case DF_BYTE: +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[8] = pws->b[9]; + pwd->b[10] = pws->b[13]; + pwd->b[12] = pws->b[1]; + pwd->b[14] = pws->b[5]; + pwd->b[0] = pwt->b[9]; + pwd->b[2] = pwt->b[13]; + pwd->b[4] = pwt->b[1]; + pwd->b[6] = pwt->b[5]; + pwd->b[9] = pws->b[11]; + pwd->b[13] = pws->b[3]; + pwd->b[1] = pwt->b[11]; + pwd->b[5] = pwt->b[3]; + pwd->b[11] = pws->b[15]; + pwd->b[3] = pwt->b[15]; + pwd->b[15] = pws->b[7]; + pwd->b[7] = pwt->b[7]; +#else pwd->b[15] = pws->b[14]; pwd->b[13] = pws->b[10]; pwd->b[11] = pws->b[6]; @@ -2129,8 +2147,19 @@ void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, pwd->b[4] = pwt->b[8]; pwd->b[8] = pws->b[0]; pwd->b[0] = pwt->b[0]; +#endif break; case DF_HALF: +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[4] = pws->h[5]; + pwd->h[6] = pws->h[1]; + pwd->h[0] = pwt->h[5]; + pwd->h[2] = pwt->h[1]; + pwd->h[5] = pws->h[7]; + pwd->h[1] = pwt->h[7]; + pwd->h[7] = pws->h[3]; + pwd->h[3] = pwt->h[3]; +#else pwd->h[7] = pws->h[6]; pwd->h[5] = pws->h[2]; pwd->h[3] = pwt->h[6]; @@ -2139,12 +2168,20 @@ void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, pwd->h[2] = pwt->h[4]; pwd->h[4] = pws->h[0]; pwd->h[0] = pwt->h[0]; +#endif break; case DF_WORD: +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[2] = pws->w[3]; + pwd->w[0] = pwt->w[3]; + pwd->w[3] = pws->w[1]; + pwd->w[1] = pwt->w[1]; +#else pwd->w[3] = pws->w[2]; pwd->w[1] = pwt->w[2]; pwd->w[2] = pws->w[0]; pwd->w[0] = pwt->w[0]; +#endif break; case DF_DOUBLE: pwd->d[1] = pws->d[0]; @@ -2164,6 +2201,24 @@ void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, switch (df) { case DF_BYTE: +#if defined(HOST_WORDS_BIGENDIAN) + pwd->b[7] = pwt->b[6]; + pwd->b[5] = pwt->b[2]; + pwd->b[3] = pwt->b[14]; + pwd->b[1] = pwt->b[10]; + pwd->b[15] = pws->b[6]; + pwd->b[13] = pws->b[2]; + pwd->b[11] = pws->b[14]; + pwd->b[9] = pws->b[10]; + pwd->b[6] = pwt->b[4]; + pwd->b[2] = pwt->b[12]; + pwd->b[14] = pws->b[4]; + pwd->b[10] = pws->b[12]; + pwd->b[4] = pwt->b[0]; + pwd->b[12] = pws->b[0]; + pwd->b[0] = pwt->b[8]; + pwd->b[8] = pws->b[8]; +#else pwd->b[0] = pwt->b[1]; pwd->b[2] = pwt->b[5]; pwd->b[4] = pwt->b[9]; @@ -2180,8 +2235,19 @@ void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, pwd->b[11] = pws->b[7]; pwd->b[7] = pwt->b[15]; pwd->b[15] = pws->b[15]; +#endif break; case DF_HALF: +#if defined(HOST_WORDS_BIGENDIAN) + pwd->h[3] = pwt->h[2]; + pwd->h[1] = pwt->h[6]; + pwd->h[7] = pws->h[2]; + pwd->h[5] = pws->h[6]; + pwd->h[2] = pwt->h[0]; + pwd->h[6] = pws->h[0]; + pwd->h[0] = pwt->h[4]; + pwd->h[4] = pws->h[4]; +#else pwd->h[0] = pwt->h[1]; pwd->h[2] = pwt->h[5]; pwd->h[4] = pws->h[1]; @@ -2190,12 +2256,20 @@ void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, pwd->h[5] = pws->h[3]; pwd->h[3] = pwt->h[7]; pwd->h[7] = pws->h[7]; +#endif break; case DF_WORD: +#if defined(HOST_WORDS_BIGENDIAN) + pwd->w[1] = pwt->w[0]; + pwd->w[3] = pws->w[0]; + pwd->w[0] = pwt->w[2]; + pwd->w[2] = pws->w[2]; +#else pwd->w[0] = pwt->w[1]; pwd->w[2] = pws->w[1]; pwd->w[1] = pwt->w[3]; pwd->w[3] = pws->w[3]; +#endif break; case DF_DOUBLE: pwd->d[0] = pwt->d[1]; diff --git a/target/mips/translate.c b/target/mips/translate.c index 3575eff0ae..ca628002ae 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20141,12 +20141,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) switch (extract32(ctx->opcode, 7, 4)) { case NM_SHXS: check_nms(ctx); + /* fall through */ case NM_LHXS: case NM_LHUXS: tcg_gen_shli_tl(t0, t0, 1); break; case NM_SWXS: check_nms(ctx); + /* fall through */ case NM_LWXS: case NM_LWC1XS: case NM_SWC1XS: |