diff options
Diffstat (limited to 'target')
148 files changed, 2331 insertions, 2995 deletions
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 17cd14e590..68c46f7998 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -15,6 +15,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 44 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) -#define NB_MMU_MODES 3 - #endif diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 7db14f4431..0f8fa150f8 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 25f6cb8894..c83c92dd4c 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index b7bde18986..b3b35f7aa1 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -45,6 +45,4 @@ bool guarded; #endif -#define NB_MMU_MODES 12 - #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..0fb07cc7b6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "cpregs.h" #include "qemu/module.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" @@ -1027,6 +1028,72 @@ static void aarch64_a64fx_initfn(Object *obj) /* TODO: Add A64FX specific HPC extension registers */ } +static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { + { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* + * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU + * (and in particular its system registers). + */ + { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, + { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, + { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, +}; + +static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); +} + static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1094,6 +1161,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj) /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 = 0x410c3000; + + define_neoverse_n1_cp_reginfo(cpu); } static void aarch64_host_initfn(Object *obj) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 3f799f5d05..3bd86cee97 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "internals.h" #include "cpregs.h" @@ -519,12 +520,19 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } +#if 0 + /* + * GDB versions 9 through 12 have a bug which means they will + * crash if they see this XML from QEMU; disable it for the 8.0 + * release, pending a better solution. + */ if (isar_feature_aa64_pauth(&cpu->isar)) { gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, aarch64_gdb_set_pauth_reg, 4, "aarch64-pauth.xml", 0); } #endif +#endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 3bee892fb7..ec1e07f139 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -20,7 +20,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/arm/internals.h b/target/arm/internals.h index b1ef05963f..673519a24a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -193,16 +193,22 @@ void arm_restore_state_to_opc(CPUState *cs, void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ -enum arm_fprounding { +typedef enum ARMFPRounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, FPROUNDING_NEGINF, FPROUNDING_ZERO, FPROUNDING_TIEAWAY, FPROUNDING_ODD -}; +} ARMFPRounding; + +extern const FloatRoundMode arm_rmode_to_sf_map[6]; -int arm_rmode_to_sf(int rmode); +static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode) +{ + assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map)); + return arm_rmode_to_sf_map[rmode]; +} static inline void aarch64_save_sp(CPUARMState *env, int el) { diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 0972a4bdd0..c3edf163be 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/log.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 081fc3f5f7..9758f225d6 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2c2ea45b47..dff391bfe2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -6146,13 +6146,12 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) case 0xb: /* FRINTZ */ case 0xc: /* FRINTA */ { - TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); - fpst = fpstatus_ptr(FPST_FPCR_F16); + TCGv_i32 tcg_rmode; - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + fpst = fpstatus_ptr(FPST_FPCR_F16); + tcg_rmode = gen_set_rmode(opcode & 7, fpst); gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); break; } case 0xe: /* FRINTX */ @@ -6202,7 +6201,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) case 0xa: /* FRINTM */ case 0xb: /* FRINTZ */ case 0xc: /* FRINTA */ - rmode = arm_rmode_to_sf(opcode & 7); + rmode = opcode & 7; gen_fpst = gen_helper_rints; break; case 0xe: /* FRINTX */ @@ -6212,14 +6211,14 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) gen_fpst = gen_helper_rints; break; case 0x10: /* FRINT32Z */ - rmode = float_round_to_zero; + rmode = FPROUNDING_ZERO; gen_fpst = gen_helper_frint32_s; break; case 0x11: /* FRINT32X */ gen_fpst = gen_helper_frint32_s; break; case 0x12: /* FRINT64Z */ - rmode = float_round_to_zero; + rmode = FPROUNDING_ZERO; gen_fpst = gen_helper_frint64_s; break; case 0x13: /* FRINT64X */ @@ -6231,10 +6230,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) fpst = fpstatus_ptr(FPST_FPCR); if (rmode >= 0) { - TCGv_i32 tcg_rmode = tcg_const_i32(rmode); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst); gen_fpst(tcg_res, tcg_op, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); } else { gen_fpst(tcg_res, tcg_op, fpst); } @@ -6275,7 +6273,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) case 0xa: /* FRINTM */ case 0xb: /* FRINTZ */ case 0xc: /* FRINTA */ - rmode = arm_rmode_to_sf(opcode & 7); + rmode = opcode & 7; gen_fpst = gen_helper_rintd; break; case 0xe: /* FRINTX */ @@ -6285,14 +6283,14 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) gen_fpst = gen_helper_rintd; break; case 0x10: /* FRINT32Z */ - rmode = float_round_to_zero; + rmode = FPROUNDING_ZERO; gen_fpst = gen_helper_frint32_d; break; case 0x11: /* FRINT32X */ gen_fpst = gen_helper_frint32_d; break; case 0x12: /* FRINT64Z */ - rmode = float_round_to_zero; + rmode = FPROUNDING_ZERO; gen_fpst = gen_helper_frint64_d; break; case 0x13: /* FRINT64X */ @@ -6304,10 +6302,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) fpst = fpstatus_ptr(FPST_FPCR); if (rmode >= 0) { - TCGv_i32 tcg_rmode = tcg_const_i32(rmode); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst); gen_fpst(tcg_res, tcg_op, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); } else { gen_fpst(tcg_res, tcg_op, fpst); } @@ -6944,9 +6941,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, rmode = FPROUNDING_TIEAWAY; } - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); switch (type) { case 1: /* float64 */ @@ -7023,7 +7018,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, g_assert_not_reached(); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + gen_restore_rmode(tcg_rmode, tcg_fpstatus); } } @@ -7447,10 +7442,10 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) bool part = extract32(insn, 14, 1); bool is_q = extract32(insn, 30, 1); int esize = 8 << size; - int i, ofs; + int i; int datasize = is_q ? 128 : 64; int elements = datasize / esize; - TCGv_i64 tcg_res, tcg_resl, tcg_resh; + TCGv_i64 tcg_res[2], tcg_ele; if (opcode == 0 || (size == 3 && !is_q)) { unallocated_encoding(s); @@ -7461,37 +7456,39 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) return; } - tcg_resl = tcg_const_i64(0); - tcg_resh = is_q ? tcg_const_i64(0) : NULL; - tcg_res = tcg_temp_new_i64(); + tcg_res[0] = tcg_temp_new_i64(); + tcg_res[1] = is_q ? tcg_temp_new_i64() : NULL; + tcg_ele = tcg_temp_new_i64(); for (i = 0; i < elements; i++) { + int o, w; + switch (opcode) { case 1: /* UZP1/2 */ { int midpoint = elements / 2; if (i < midpoint) { - read_vec_element(s, tcg_res, rn, 2 * i + part, size); + read_vec_element(s, tcg_ele, rn, 2 * i + part, size); } else { - read_vec_element(s, tcg_res, rm, + read_vec_element(s, tcg_ele, rm, 2 * (i - midpoint) + part, size); } break; } case 2: /* TRN1/2 */ if (i & 1) { - read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); + read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size); } else { - read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); + read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size); } break; case 3: /* ZIP1/2 */ { int base = part * elements / 2; if (i & 1) { - read_vec_element(s, tcg_res, rm, base + (i >> 1), size); + read_vec_element(s, tcg_ele, rm, base + (i >> 1), size); } else { - read_vec_element(s, tcg_res, rn, base + (i >> 1), size); + read_vec_element(s, tcg_ele, rn, base + (i >> 1), size); } break; } @@ -7499,19 +7496,18 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) g_assert_not_reached(); } - ofs = i * esize; - if (ofs < 64) { - tcg_gen_shli_i64(tcg_res, tcg_res, ofs); - tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); + w = (i * esize) / 64; + o = (i * esize) % 64; + if (o == 0) { + tcg_gen_mov_i64(tcg_res[w], tcg_ele); } else { - tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); - tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); + tcg_gen_shli_i64(tcg_ele, tcg_ele, o); + tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele); } } - write_vec_element(s, tcg_resl, rd, 0, MO_64); - if (is_q) { - write_vec_element(s, tcg_resh, rd, 1, MO_64); + for (i = 0; i <= is_q; ++i) { + write_vec_element(s, tcg_res[i], rd, i, MO_64); } clear_vec_high(s, is_q, rd); } @@ -8463,7 +8459,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, tcg_rn = tcg_temp_new_i64(); tcg_rd = tcg_temp_new_i64(); tcg_rd_narrowed = tcg_temp_new_i32(); - tcg_final = tcg_const_i64(0); + tcg_final = tcg_temp_new_i64(); if (round) { tcg_round = tcg_constant_i64(1ULL << (shift - 1)); @@ -8477,7 +8473,11 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, false, is_u_shift, size+1, shift); narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); - tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); + if (i == 0) { + tcg_gen_mov_i64(tcg_final, tcg_rd); + } else { + tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); + } } if (!is_q) { @@ -8771,9 +8771,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, assert(!(is_scalar && is_q)); - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus); fracbits = (16 << size) - immhb; tcg_shift = tcg_constant_i32(fracbits); @@ -8831,7 +8830,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, } } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + gen_restore_rmode(tcg_rmode, tcg_fpstatus); } /* AdvSIMD scalar shift by immediate @@ -10219,12 +10218,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) } if (is_fcvt) { - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); tcg_fpstatus = fpstatus_ptr(FPST_FPCR); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); } else { - tcg_rmode = NULL; tcg_fpstatus = NULL; + tcg_rmode = NULL; } if (size == 3) { @@ -10276,7 +10274,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) } if (is_fcvt) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + gen_restore_rmode(tcg_rmode, tcg_fpstatus); } } @@ -12005,22 +12003,26 @@ static void handle_rev(DisasContext *s, int opcode, bool u, int esize = 8 << size; int elements = dsize / esize; TCGv_i64 tcg_rn = tcg_temp_new_i64(); - TCGv_i64 tcg_rd = tcg_const_i64(0); - TCGv_i64 tcg_rd_hi = tcg_const_i64(0); + TCGv_i64 tcg_rd[2]; + + for (i = 0; i < 2; i++) { + tcg_rd[i] = tcg_temp_new_i64(); + tcg_gen_movi_i64(tcg_rd[i], 0); + } for (i = 0; i < elements; i++) { int e_rev = (i & 0xf) ^ revmask; - int off = e_rev * esize; + int w = (e_rev * esize) / 64; + int o = (e_rev * esize) % 64; + read_vec_element(s, tcg_rn, rn, i, size); - if (off >= 64) { - tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, - tcg_rn, off - 64, esize); - } else { - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); - } + tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize); + } + + for (i = 0; i < 2; i++) { + write_vec_element(s, tcg_rd[i], rd, i, MO_64); } - write_vec_element(s, tcg_rd, rd, 0, MO_64); - write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); + clear_vec_high(s, true, rd); } } @@ -12133,7 +12135,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); bool need_fpstatus = false; - bool need_rmode = false; int rmode = -1; TCGv_i32 tcg_rmode; TCGv_ptr tcg_fpstatus; @@ -12283,7 +12284,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ need_fpstatus = true; - need_rmode = true; rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); if (size == 3 && !is_q) { unallocated_encoding(s); @@ -12293,7 +12293,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x5c: /* FCVTAU */ case 0x1c: /* FCVTAS */ need_fpstatus = true; - need_rmode = true; rmode = FPROUNDING_TIEAWAY; if (size == 3 && !is_q) { unallocated_encoding(s); @@ -12352,7 +12351,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ case 0x39: /* FRINTZ */ - need_rmode = true; rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); /* fall through */ case 0x59: /* FRINTX */ @@ -12364,7 +12362,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } break; case 0x58: /* FRINTA */ - need_rmode = true; rmode = FPROUNDING_TIEAWAY; need_fpstatus = true; if (size == 3 && !is_q) { @@ -12380,7 +12377,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) break; case 0x1e: /* FRINT32Z */ case 0x1f: /* FRINT64Z */ - need_rmode = true; rmode = FPROUNDING_ZERO; /* fall through */ case 0x5e: /* FRINT32X */ @@ -12406,14 +12402,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) return; } - if (need_fpstatus || need_rmode) { + if (need_fpstatus || rmode >= 0) { tcg_fpstatus = fpstatus_ptr(FPST_FPCR); } else { tcg_fpstatus = NULL; } - if (need_rmode) { - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + if (rmode >= 0) { + tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); } else { tcg_rmode = NULL; } @@ -12595,8 +12590,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } clear_vec_high(s, is_q, rd); - if (need_rmode) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + if (tcg_rmode) { + gen_restore_rmode(tcg_rmode, tcg_fpstatus); } } @@ -12625,9 +12620,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) int pass; TCGv_i32 tcg_rmode = NULL; TCGv_ptr tcg_fpstatus = NULL; - bool need_rmode = false; bool need_fpst = true; - int rmode; + int rmode = -1; if (!dc_isar_feature(aa64_fp16, s)) { unallocated_encoding(s); @@ -12676,27 +12670,22 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3f: /* FRECPX */ break; case 0x18: /* FRINTN */ - need_rmode = true; only_in_vector = true; rmode = FPROUNDING_TIEEVEN; break; case 0x19: /* FRINTM */ - need_rmode = true; only_in_vector = true; rmode = FPROUNDING_NEGINF; break; case 0x38: /* FRINTP */ - need_rmode = true; only_in_vector = true; rmode = FPROUNDING_POSINF; break; case 0x39: /* FRINTZ */ - need_rmode = true; only_in_vector = true; rmode = FPROUNDING_ZERO; break; case 0x58: /* FRINTA */ - need_rmode = true; only_in_vector = true; rmode = FPROUNDING_TIEAWAY; break; @@ -12706,43 +12695,33 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) /* current rounding mode */ break; case 0x1a: /* FCVTNS */ - need_rmode = true; rmode = FPROUNDING_TIEEVEN; break; case 0x1b: /* FCVTMS */ - need_rmode = true; rmode = FPROUNDING_NEGINF; break; case 0x1c: /* FCVTAS */ - need_rmode = true; rmode = FPROUNDING_TIEAWAY; break; case 0x3a: /* FCVTPS */ - need_rmode = true; rmode = FPROUNDING_POSINF; break; case 0x3b: /* FCVTZS */ - need_rmode = true; rmode = FPROUNDING_ZERO; break; case 0x5a: /* FCVTNU */ - need_rmode = true; rmode = FPROUNDING_TIEEVEN; break; case 0x5b: /* FCVTMU */ - need_rmode = true; rmode = FPROUNDING_NEGINF; break; case 0x5c: /* FCVTAU */ - need_rmode = true; rmode = FPROUNDING_TIEAWAY; break; case 0x7a: /* FCVTPU */ - need_rmode = true; rmode = FPROUNDING_POSINF; break; case 0x7b: /* FCVTZU */ - need_rmode = true; rmode = FPROUNDING_ZERO; break; case 0x2f: /* FABS */ @@ -12775,13 +12754,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) return; } - if (need_rmode || need_fpst) { + if (rmode >= 0 || need_fpst) { tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16); } - if (need_rmode) { - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + if (rmode >= 0) { + tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus); } if (is_scalar) { @@ -12881,7 +12859,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) } if (tcg_rmode) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + gen_restore_rmode(tcg_rmode, tcg_fpstatus); } } diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index 798b4fddfe..31fb2110f1 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -588,7 +588,7 @@ DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs) DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu) static bool do_vcvt_rmode(DisasContext *s, arg_1op *a, - enum arm_fprounding rmode, bool u) + ARMFPRounding rmode, bool u) { /* * Handle VCVT fp to int with specified rounding mode. @@ -1150,7 +1150,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenLongDualAccOpFn *fn) { TCGv_ptr qn, qm; - TCGv_i64 rda; + TCGv_i64 rda_i, rda_o; TCGv_i32 rdalo, rdahi; if (!dc_isar_feature(aa32_mve, s) || @@ -1177,21 +1177,22 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, * of an A=0 (no-accumulate) insn which does not execute the first * beat must start with the current rda value, not 0. */ + rda_o = tcg_temp_new_i64(); if (a->a || mve_skip_first_beat(s)) { - rda = tcg_temp_new_i64(); + rda_i = rda_o; rdalo = load_reg(s, a->rdalo); rdahi = load_reg(s, a->rdahi); - tcg_gen_concat_i32_i64(rda, rdalo, rdahi); + tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi); } else { - rda = tcg_const_i64(0); + rda_i = tcg_constant_i64(0); } - fn(rda, cpu_env, qn, qm, rda); + fn(rda_o, cpu_env, qn, qm, rda_i); rdalo = tcg_temp_new_i32(); rdahi = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(rdalo, rda); - tcg_gen_extrh_i64_i32(rdahi, rda); + tcg_gen_extrl_i64_i32(rdalo, rda_o); + tcg_gen_extrh_i64_i32(rdahi, rda_o); store_reg(s, a->rdalo, rdalo); store_reg(s, a->rdahi, rdahi); mve_update_eci(s); @@ -1258,7 +1259,7 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn) { TCGv_ptr qn, qm; - TCGv_i32 rda; + TCGv_i32 rda_i, rda_o; if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qn) || @@ -1278,13 +1279,14 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn) * beat must start with the current rda value, not 0. */ if (a->a || mve_skip_first_beat(s)) { - rda = load_reg(s, a->rda); + rda_o = rda_i = load_reg(s, a->rda); } else { - rda = tcg_const_i32(0); + rda_i = tcg_constant_i32(0); + rda_o = tcg_temp_new_i32(); } - fn(rda, cpu_env, qn, qm, rda); - store_reg(s, a->rda, rda); + fn(rda_o, cpu_env, qn, qm, rda_i); + store_reg(s, a->rda, rda_o); mve_update_eci(s); return true; @@ -1396,7 +1398,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) { NULL, NULL } }; TCGv_ptr qm; - TCGv_i32 rda; + TCGv_i32 rda_i, rda_o; if (!dc_isar_feature(aa32_mve, s) || a->size == 3) { @@ -1413,15 +1415,16 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) */ if (a->a || mve_skip_first_beat(s)) { /* Accumulate input from Rda */ - rda = load_reg(s, a->rda); + rda_o = rda_i = load_reg(s, a->rda); } else { /* Accumulate starting at zero */ - rda = tcg_const_i32(0); + rda_i = tcg_constant_i32(0); + rda_o = tcg_temp_new_i32(); } qm = mve_qreg_ptr(a->qm); - fns[a->size][a->u](rda, cpu_env, qm, rda); - store_reg(s, a->rda, rda); + fns[a->size][a->u](rda_o, cpu_env, qm, rda_i); + store_reg(s, a->rda, rda_o); mve_update_eci(s); return true; @@ -1436,7 +1439,7 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) * No need to check Qm's bank: it is only 3 bits in decode. */ TCGv_ptr qm; - TCGv_i64 rda; + TCGv_i64 rda_i, rda_o; TCGv_i32 rdalo, rdahi; if (!dc_isar_feature(aa32_mve, s)) { @@ -1458,28 +1461,29 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) * of an A=0 (no-accumulate) insn which does not execute the first * beat must start with the current value of RdaHi:RdaLo, not zero. */ + rda_o = tcg_temp_new_i64(); if (a->a || mve_skip_first_beat(s)) { /* Accumulate input from RdaHi:RdaLo */ - rda = tcg_temp_new_i64(); + rda_i = rda_o; rdalo = load_reg(s, a->rdalo); rdahi = load_reg(s, a->rdahi); - tcg_gen_concat_i32_i64(rda, rdalo, rdahi); + tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi); } else { /* Accumulate starting at zero */ - rda = tcg_const_i64(0); + rda_i = tcg_constant_i64(0); } qm = mve_qreg_ptr(a->qm); if (a->u) { - gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); + gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i); } else { - gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); + gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i); } rdalo = tcg_temp_new_i32(); rdahi = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(rdalo, rda); - tcg_gen_extrh_i64_i32(rdahi, rda); + tcg_gen_extrl_i64_i32(rdalo, rda_o); + tcg_gen_extrh_i64_i32(rdahi, rda_o); store_reg(s, a->rdalo, rdalo); store_reg(s, a->rdahi, rdahi); mve_update_eci(s); diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 5bf80b22d7..92ab290106 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4082,7 +4082,7 @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, - int mode, gen_helper_gvec_3_ptr *fn) + ARMFPRounding mode, gen_helper_gvec_3_ptr *fn) { unsigned vsz; TCGv_i32 tmode; @@ -4096,30 +4096,28 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, } vsz = vec_full_reg_size(s); - tmode = tcg_const_i32(mode); status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR); - - gen_helper_set_rmode(tmode, tmode, status); + tmode = gen_set_rmode(mode, status); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), pred_full_reg_offset(s, a->pg), status, vsz, vsz, 0, fn); - gen_helper_set_rmode(tmode, tmode, status); + gen_restore_rmode(tmode, status); return true; } TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a, - float_round_nearest_even, frint_fns[a->esz]) + FPROUNDING_TIEEVEN, frint_fns[a->esz]) TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a, - float_round_up, frint_fns[a->esz]) + FPROUNDING_POSINF, frint_fns[a->esz]) TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a, - float_round_down, frint_fns[a->esz]) + FPROUNDING_NEGINF, frint_fns[a->esz]) TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a, - float_round_to_zero, frint_fns[a->esz]) + FPROUNDING_ZERO, frint_fns[a->esz]) TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a, - float_round_ties_away, frint_fns[a->esz]) + FPROUNDING_TIEAWAY, frint_fns[a->esz]) static gen_helper_gvec_3_ptr * const frecpx_fns[] = { NULL, gen_helper_sve_frecpx_h, @@ -4208,8 +4206,9 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, } } else { TCGLabel *loop = gen_new_label(); - TCGv_ptr tp, i = tcg_const_ptr(0); + TCGv_ptr tp, i = tcg_temp_new_ptr(); + tcg_gen_movi_ptr(i, 0); gen_set_label(loop); t0 = tcg_temp_new_i64(); @@ -4286,8 +4285,9 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, } } else { TCGLabel *loop = gen_new_label(); - TCGv_ptr tp, i = tcg_const_ptr(0); + TCGv_ptr tp, i = tcg_temp_new_ptr(); + tcg_gen_movi_ptr(i, 0); gen_set_label(loop); t0 = tcg_temp_new_i64(); @@ -7145,9 +7145,9 @@ TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR) TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a, - float_round_to_odd, gen_helper_sve_fcvt_ds) + FPROUNDING_ODD, gen_helper_sve_fcvt_ds) TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a, - float_round_to_odd, gen_helper_sve2_fcvtnt_ds) + FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds) static gen_helper_gvec_3_ptr * const flogb_fns[] = { NULL, gen_helper_flogb_h, diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 757a2bf7d9..dd782aacf4 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) fpst = fpstatus_ptr(FPST_FPCR); } - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_rmode = gen_set_rmode(rounding, fpst); if (sz == 3) { TCGv_i64 tcg_op; @@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) vfp_store_reg32(tcg_res, rd); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); return true; } @@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } tcg_shift = tcg_constant_i32(0); - - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_rmode = gen_set_rmode(rounding, fpst); if (sz == 3) { TCGv_i64 tcg_double, tcg_res; @@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) vfp_store_reg32(tcg_res, rd); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); return true; } @@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); fpst = fpstatus_ptr(FPST_FPCR_F16); - tcg_rmode = tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rinth(tmp, tmp, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); vfp_store_reg32(tmp, a->vd); return true; } @@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) tmp = tcg_temp_new_i32(); vfp_load_reg32(tmp, a->vm); fpst = fpstatus_ptr(FPST_FPCR); - tcg_rmode = tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rints(tmp, tmp, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); vfp_store_reg32(tmp, a->vd); return true; } @@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) tmp = tcg_temp_new_i64(); vfp_load_reg64(tmp, a->vm); fpst = fpstatus_ptr(FPST_FPCR); - tcg_rmode = tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst); gen_helper_rintd(tmp, tmp, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_restore_rmode(tcg_rmode, fpst); vfp_store_reg64(tmp, a->vd); return true; } diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b70b628000..2cb9368b1b 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a) static bool trans_BFCI(DisasContext *s, arg_BFCI *a) { - TCGv_i32 tmp; int msb = a->msb, lsb = a->lsb; + TCGv_i32 t_in, t_rd; int width; if (!ENABLE_ARCH_6T2) { @@ -7277,16 +7277,14 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a) width = msb + 1 - lsb; if (a->rn == 15) { /* BFC */ - tmp = tcg_const_i32(0); + t_in = tcg_constant_i32(0); } else { /* BFI */ - tmp = load_reg(s, a->rn); - } - if (width != 32) { - TCGv_i32 tmp2 = load_reg(s, a->rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + t_in = load_reg(s, a->rn); } - store_reg(s, a->rd, tmp); + t_rd = load_reg(s, a->rd); + tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width); + store_reg(s, a->rd, t_rd); return true; } diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 20f3ca7aca..f02d4685b4 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -617,6 +617,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) } /* + * Set and reset rounding mode around another operation. + */ +static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst) +{ + TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode)); + TCGv_i32 old = tcg_temp_new_i32(); + + gen_helper_set_rmode(old, new, fpst); + return old; +} + +static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst) +{ + gen_helper_set_rmode(old, old, fpst); +} + +/* * Helpers for implementing sets of trans_* functions. * Defer the implementation of NAME to FUNC, with optional extra arguments. */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 24e3d820a5..36906db8e0 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1104,33 +1104,14 @@ float64 HELPER(rintd)(float64 x, void *fp_status) } /* Convert ARM rounding mode to softfloat */ -int arm_rmode_to_sf(int rmode) -{ - switch (rmode) { - case FPROUNDING_TIEAWAY: - rmode = float_round_ties_away; - break; - case FPROUNDING_ODD: - /* FIXME: add support for TIEAWAY and ODD */ - qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", - rmode); - /* fall through for now */ - case FPROUNDING_TIEEVEN: - default: - rmode = float_round_nearest_even; - break; - case FPROUNDING_POSINF: - rmode = float_round_up; - break; - case FPROUNDING_NEGINF: - rmode = float_round_down; - break; - case FPROUNDING_ZERO: - rmode = float_round_to_zero; - break; - } - return rmode; -} +const FloatRoundMode arm_rmode_to_sf_map[] = { + [FPROUNDING_TIEEVEN] = float_round_nearest_even, + [FPROUNDING_POSINF] = float_round_up, + [FPROUNDING_NEGINF] = float_round_down, + [FPROUNDING_ZERO] = float_round_to_zero, + [FPROUNDING_TIEAWAY] = float_round_ties_away, + [FPROUNDING_ODD] = float_round_to_odd, +}; /* * Implement float64 to int32_t conversion without saturation; diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 7ef4e7c679..9a92bc74fc 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -31,6 +31,5 @@ #define TARGET_PAGE_BITS 8 #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 -#define NB_MMU_MODES 2 #endif diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index 1c1b908c92..150344d8b9 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/avr/translate.c b/target/avr/translate.c index b9506a8d86..a6aeae6dfa 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -400,7 +400,7 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a) static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a) { TCGv Rd = cpu_r[a->rd]; - TCGv Rr = tcg_const_i32(a->imm); + TCGv Rr = tcg_constant_i32(a->imm); TCGv R = tcg_temp_new_i32(); tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */ @@ -425,7 +425,7 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a) TCGv Rd = cpu_r[a->rd]; TCGv Rr = cpu_r[a->rr]; TCGv R = tcg_temp_new_i32(); - TCGv zero = tcg_const_i32(0); + TCGv zero = tcg_constant_i32(0); tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ tcg_gen_sub_tl(R, R, cpu_Cf); @@ -453,9 +453,9 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a) static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a) { TCGv Rd = cpu_r[a->rd]; - TCGv Rr = tcg_const_i32(a->imm); + TCGv Rr = tcg_constant_i32(a->imm); TCGv R = tcg_temp_new_i32(); - TCGv zero = tcg_const_i32(0); + TCGv zero = tcg_constant_i32(0); tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ tcg_gen_sub_tl(R, R, cpu_Cf); @@ -637,7 +637,7 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a) static bool trans_NEG(DisasContext *ctx, arg_NEG *a) { TCGv Rd = cpu_r[a->rd]; - TCGv t0 = tcg_const_i32(0); + TCGv t0 = tcg_constant_i32(0); TCGv R = tcg_temp_new_i32(); tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */ @@ -930,19 +930,19 @@ static void gen_jmp_z(DisasContext *ctx) static void gen_push_ret(DisasContext *ctx, int ret) { if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { - TCGv t0 = tcg_const_i32((ret & 0x0000ff)); + TCGv t0 = tcg_constant_i32(ret & 0x0000ff); tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { - TCGv t0 = tcg_const_i32((ret & 0x00ffff)); + TCGv t0 = tcg_constant_i32(ret & 0x00ffff); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { - TCGv lo = tcg_const_i32((ret & 0x0000ff)); - TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8); + TCGv lo = tcg_constant_i32(ret & 0x0000ff); + TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8); tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); @@ -1211,7 +1211,7 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a) TCGv Rd = cpu_r[a->rd]; TCGv Rr = cpu_r[a->rr]; TCGv R = tcg_temp_new_i32(); - TCGv zero = tcg_const_i32(0); + TCGv zero = tcg_constant_i32(0); tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ tcg_gen_sub_tl(R, R, cpu_Cf); @@ -1238,7 +1238,7 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a) { TCGv Rd = cpu_r[a->rd]; int Imm = a->imm; - TCGv Rr = tcg_const_i32(Imm); + TCGv Rr = tcg_constant_i32(Imm); TCGv R = tcg_temp_new_i32(); tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ @@ -1288,12 +1288,13 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) */ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { - TCGv temp = tcg_const_i32(a->reg); + TCGv data = tcg_temp_new_i32(); + TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(temp, cpu_env, temp); - tcg_gen_andi_tl(temp, temp, 1 << a->bit); + gen_helper_inb(data, cpu_env, port); + tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond = TCG_COND_EQ; - ctx->skip_var0 = temp; + ctx->skip_var0 = data; return true; } @@ -1305,12 +1306,13 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) */ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { - TCGv temp = tcg_const_i32(a->reg); + TCGv data = tcg_temp_new_i32(); + TCGv port = tcg_constant_i32(a->reg); - gen_helper_inb(temp, cpu_env, temp); - tcg_gen_andi_tl(temp, temp, 1 << a->bit); + gen_helper_inb(data, cpu_env, port); + tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond = TCG_COND_NE; - ctx->skip_var0 = temp; + ctx->skip_var0 = data; return true; } @@ -2122,7 +2124,7 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd = cpu_r[a->rd]; - TCGv port = tcg_const_i32(a->imm); + TCGv port = tcg_constant_i32(a->imm); gen_helper_inb(Rd, cpu_env, port); return true; @@ -2135,7 +2137,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd = cpu_r[a->rd]; - TCGv port = tcg_const_i32(a->imm); + TCGv port = tcg_constant_i32(a->imm); gen_helper_outb(cpu_env, port, Rd); return true; @@ -2403,7 +2405,7 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_const_i32(a->reg); + TCGv port = tcg_constant_i32(a->reg); gen_helper_inb(data, cpu_env, port); tcg_gen_ori_tl(data, data, 1 << a->bit); @@ -2418,7 +2420,7 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data = tcg_temp_new_i32(); - TCGv port = tcg_const_i32(a->reg); + TCGv port = tcg_constant_i32(a->reg); gen_helper_inb(data, cpu_env, port); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h index 12ec22d8df..b31b742c0d 100644 --- a/target/cris/cpu-param.h +++ b/target/cris/cpu-param.h @@ -12,6 +12,5 @@ #define TARGET_PAGE_BITS 13 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define NB_MMU_MODES 2 #endif diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index 2418d575b1..25c0ca33a5 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/cris/translate.c b/target/cris/translate.c index 5172c9b9b2..b2beb9964d 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -175,10 +175,7 @@ static const int preg_sizes[] = { #define t_gen_mov_env_TN(member, tn) \ tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) #define t_gen_movi_env_TN(member, c) \ - do { \ - TCGv tc = tcg_const_tl(c); \ - t_gen_mov_env_TN(member, tc); \ - } while (0) + t_gen_mov_env_TN(member, tcg_constant_tl(c)) static inline void t_gen_mov_TN_preg(TCGv tn, int r) { @@ -268,8 +265,7 @@ static void cris_lock_irq(DisasContext *dc) static inline void t_gen_raise_exception(uint32_t index) { - TCGv_i32 tmp = tcg_const_i32(index); - gen_helper_raise_exception(cpu_env, tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); } static void t_gen_lsl(TCGv d, TCGv a, TCGv b) @@ -277,7 +273,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b) TCGv t0, t_31; t0 = tcg_temp_new(); - t_31 = tcg_const_tl(31); + t_31 = tcg_constant_tl(31); tcg_gen_shl_tl(d, a, b); tcg_gen_sub_tl(t0, t_31, b); @@ -1250,7 +1246,7 @@ static int dec_addq(CPUCRISState *env, DisasContext *dc) cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(dc->op1); + c = tcg_constant_tl(dc->op1); cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); return 2; @@ -1274,7 +1270,7 @@ static int dec_subq(CPUCRISState *env, DisasContext *dc) LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(dc->op1); + c = tcg_constant_tl(dc->op1); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); return 2; @@ -1289,7 +1285,7 @@ static int dec_cmpq(CPUCRISState *env, DisasContext *dc) LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); return 2; @@ -1304,7 +1300,7 @@ static int dec_andq(CPUCRISState *env, DisasContext *dc) LOG_DIS("andq %d, $r%d\n", imm, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); return 2; @@ -1318,7 +1314,7 @@ static int dec_orq(CPUCRISState *env, DisasContext *dc) LOG_DIS("orq %d, $r%d\n", imm, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); return 2; @@ -1330,7 +1326,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc) LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); - c = tcg_const_tl(dc->op1); + c = tcg_constant_tl(dc->op1); cris_evaluate_flags(dc); gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], c, cpu_PR[PR_CCS]); @@ -1945,8 +1941,8 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc) { TCGv c2, c1; LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); - c1 = tcg_const_tl(dc->op1); - c2 = tcg_const_tl(dc->op2); + c1 = tcg_constant_tl(dc->op1); + c2 = tcg_constant_tl(dc->op2); cris_cc_mask(dc, 0); gen_helper_movl_sreg_reg(cpu_env, c2, c1); return 2; @@ -1955,8 +1951,8 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc) { TCGv c2, c1; LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); - c1 = tcg_const_tl(dc->op1); - c2 = tcg_const_tl(dc->op2); + c1 = tcg_constant_tl(dc->op1); + c2 = tcg_constant_tl(dc->op2); cris_cc_mask(dc, 0); gen_helper_movl_reg_sreg(cpu_env, c1, c2); return 2; @@ -2237,7 +2233,7 @@ static int dec_test_m(CPUCRISState *env, DisasContext *dc) cris_cc_mask(dc, CC_MASK_NZ); tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); - c = tcg_const_tl(0); + c = tcg_constant_tl(0); cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[1], c, memsize_zz(dc)); do_postinc(dc, memsize); @@ -2582,7 +2578,7 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc) if (dc->op2 > 15) { abort(); } - c = tcg_const_tl(dc->pc + 4); + c = tcg_constant_tl(dc->pc + 4); t_gen_mov_preg_TN(dc, dc->op2, c); cris_prepare_jmp(dc, JMP_INDIRECT); @@ -2598,7 +2594,7 @@ static int dec_jas_im(CPUCRISState *env, DisasContext *dc) LOG_DIS("jas 0x%x\n", imm); cris_cc_mask(dc, 0); - c = tcg_const_tl(dc->pc + 8); + c = tcg_constant_tl(dc->pc + 8); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); @@ -2616,7 +2612,7 @@ static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) LOG_DIS("jasc 0x%x\n", imm); cris_cc_mask(dc, 0); - c = tcg_const_tl(dc->pc + 8 + 4); + c = tcg_constant_tl(dc->pc + 8 + 4); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); @@ -2632,7 +2628,7 @@ static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) cris_cc_mask(dc, 0); /* Store the return address in Pd. */ tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); - c = tcg_const_tl(dc->pc + 4 + 4); + c = tcg_constant_tl(dc->pc + 4 + 4); t_gen_mov_preg_TN(dc, dc->op2, c); cris_prepare_jmp(dc, JMP_INDIRECT); return 2; @@ -2664,7 +2660,7 @@ static int dec_bas_im(CPUCRISState *env, DisasContext *dc) LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); cris_cc_mask(dc, 0); - c = tcg_const_tl(dc->pc + 8); + c = tcg_constant_tl(dc->pc + 8); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); @@ -2681,7 +2677,7 @@ static int dec_basc_im(CPUCRISState *env, DisasContext *dc) LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); cris_cc_mask(dc, 0); - c = tcg_const_tl(dc->pc + 12); + c = tcg_constant_tl(dc->pc + 12); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); @@ -2695,7 +2691,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) cris_cc_mask(dc, 0); if (dc->op2 == 15) { - tcg_gen_st_i32(tcg_const_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, -offsetof(CRISCPU, env) + offsetof(CPUState, halted)); tcg_gen_movi_tl(env_pc, dc->pc + 2); t_gen_raise_exception(EXCP_HLT); diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc index b03b2ef746..32338bb69b 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -251,7 +251,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("moveq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(simm); + c = tcg_constant_tl(simm); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -259,7 +259,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(simm); + c = tcg_constant_tl(simm); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -267,7 +267,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("addq %d, $r%d\n", imm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -275,7 +275,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("andq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(simm); + c = tcg_constant_tl(simm); cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -285,7 +285,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) cris_cc_mask(dc, CC_MASK_NZVC); op = imm & (1 << 5); imm &= 0x1f; - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); if (op) { cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); @@ -305,7 +305,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) } imm &= 0x1f; cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -313,7 +313,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("subq %d, $r%d\n", imm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(imm); + c = tcg_constant_tl(imm); cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -321,7 +321,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("andq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); - c = tcg_const_tl(simm); + c = tcg_constant_tl(simm); cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); break; @@ -1014,7 +1014,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) cris_alu_m_alloc_temps(t); insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]); tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); - c = tcg_const_tl(0); + c = tcg_constant_tl(0); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], t[0], c, size); break; @@ -1111,7 +1111,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) if (dc->mode == CRISV10_MODE_AUTOINC) insn_len += size; - c = tcg_const_tl(dc->pc + insn_len); + c = tcg_constant_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); dc->jmp_pc = imm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -1121,7 +1121,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) LOG_DIS("break %d\n", dc->src); cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc + 2); - c = tcg_const_tl(dc->src + 2); + c = tcg_constant_tl(dc->src + 2); t_gen_mov_env_TN(trap_vector, c); t_gen_raise_exception(EXCP_BREAK); dc->base.is_jmp = DISAS_NORETURN; @@ -1130,7 +1130,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size, dc->opcode, dc->src, dc->dst); t[0] = tcg_temp_new(); - c = tcg_const_tl(dc->pc + insn_len); + c = tcg_constant_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); crisv10_prepare_memaddr(dc, t[0], size); gen_load(dc, env_btarget, t[0], 4, 0); @@ -1153,7 +1153,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n", dc->pc, dc->opcode, dc->dst, dc->src); tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); - c = tcg_const_tl(dc->pc + insn_len); + c = tcg_constant_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ diff --git a/target/hexagon/README b/target/hexagon/README index 251960b862..ebafc78b1c 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -52,6 +52,7 @@ header files in <BUILD_DIR>/target/hexagon gen_tcg_func_table.py -> tcg_func_table_generated.c.inc gen_helper_funcs.py -> helper_funcs_generated.c.inc gen_idef_parser_funcs.py -> idef_parser_input.h + gen_analyze_funcs.py -> analyze_funcs_generated.c.inc Qemu helper functions have 3 parts DEF_HELPER declaration indicates the signature of the helper @@ -87,7 +88,6 @@ tcg_funcs_generated.c.inc TCGv RtV = hex_gpr[insn->regno[2]]; gen_helper_A2_add(RdV, cpu_env, RsV, RtV); gen_log_reg_write(RdN, RdV); - ctx_log_reg_write(ctx, RdN); } helper_funcs_generated.c.inc @@ -136,12 +136,9 @@ For HVX vectors, the generator behaves slightly differently. The wide vectors won't fit in a TCGv or TCGv_i64, so we pass TCGv_ptr variables to pass the address to helper functions. Here's an example for an HVX vector-add-word istruction. - static void generate_V6_vaddw( - CPUHexagonState *env, - DisasContext *ctx, - Insn *insn, - Packet *pkt) + static void generate_V6_vaddw(DisasContext *ctx) { + Insn *insn __attribute__((unused)) = ctx->insn; const int VdN = insn->regno[0]; const intptr_t VdV_off = ctx_future_vreg_off(ctx, VdN, 1, true); @@ -157,10 +154,7 @@ istruction. TCGv_ptr VvV = tcg_temp_new_ptr(); tcg_gen_addi_ptr(VuV, cpu_env, VuV_off); tcg_gen_addi_ptr(VvV, cpu_env, VvV_off); - TCGv slot = tcg_constant_tl(insn->slot); - gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot); - gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); - ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); + gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV); } Notice that we also generate a variable named <operand>_off for each operand of @@ -173,12 +167,9 @@ functions from tcg-op-gvec.h. Here's the override for this instruction. Finally, we notice that the override doesn't use the TCGv_ptr variables, so we don't generate them when an override is present. Here is what we generate when the override is present. - static void generate_V6_vaddw( - CPUHexagonState *env, - DisasContext *ctx, - Insn *insn, - Packet *pkt) + static void generate_V6_vaddw(DisasContext *ctx) { + Insn *insn __attribute__((unused)) = ctx->insn; const int VdN = insn->regno[0]; const intptr_t VdV_off = ctx_future_vreg_off(ctx, VdN, 1, true); @@ -189,10 +180,14 @@ when the override is present. const intptr_t VvV_off = vreg_src_off(ctx, VvN); fGEN_TCG_V6_vaddw({ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] = VuV.w[i] + VvV.w[i] ; } }); - gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); - ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); } +We also generate an analyze_<tag> function for each instruction. Currently, +these functions record the writes to registers by calling ctx_log_*. During +gen_start_packet, we invoke the analyze_<tag> function for each instruction in +the packet, and we mark the implicit writes. After the analysis is performed, +we initialize hex_new_value for each of the predicated assignments. + In addition to instruction semantics, we use a generator to create the decode tree. This generation is also a two step process. The first step is to run target/hexagon/gen_dectree_import.c to produce @@ -277,10 +272,8 @@ For Hexagon Vector eXtensions (HVX), the following fields are used VRegs Vector registers future_VRegs Registers to be stored during packet commit tmp_VRegs Temporary registers *not* stored during commit - VRegs_updated Mask of predicated vector writes QRegs Q (vector predicate) registers future_QRegs Registers to be stored during packet commit - QRegs_updated Mask of predicated vector writes *** Debugging *** diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc index 5d2a102c18..9874d1658f 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -44,6 +44,7 @@ DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "") DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "") DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "") DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "") +DEF_ATTRIB(SCALAR_LOAD, "Load is scalar", "", "") DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "") DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "") DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "") diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index e8ed5468d9..71b4a9b83e 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -24,6 +24,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define NB_MMU_MODES 1 - #endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 34c0ae0a67..81b663ecfb 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -111,11 +111,8 @@ typedef struct CPUArchState { MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); - VRegMask VRegs_updated; - MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); - QRegMask QRegs_updated; /* Temporaries used within instructions */ MMVectorPair VuuV QEMU_ALIGNED(16); diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index d152d01bfe..46083da620 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -16,7 +16,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "cpu.h" #include "internal.h" diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py new file mode 100755 index 0000000000..ebd3e7afb9 --- /dev/null +++ b/target/hexagon/gen_analyze_funcs.py @@ -0,0 +1,252 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see <http://www.gnu.org/licenses/>. +## + +import sys +import re +import string +import hex_common + +## +## Helpers for gen_analyze_func +## +def is_predicated(tag): + return 'A_CONDEXEC' in hex_common.attribdict[tag] + +def analyze_opn_old(f, tag, regtype, regid, regno): + regN = "%s%sN" % (regtype, regid) + predicated = "true" if is_predicated(tag) else "false" + if (regtype == "R"): + if (regid in {"ss", "tt"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"dd", "ee", "xx", "yy"}): + f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) + f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \ + (regN, predicated)) + elif (regid in {"s", "t", "u", "v"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d", "e", "x", "y"}): + f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) + f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \ + (regN, predicated)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "P"): + if (regid in {"s", "t", "u", "v"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d", "e", "x"}): + f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) + f.write(" ctx_log_pred_write(ctx, %s);\n" % (regN)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "C"): + if (regid == "ss"): + f.write("// const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \ + (regN, regno)) + elif (regid == "dd"): + f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \ + (regN, regno)) + f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \ + (regN, predicated)) + elif (regid == "s"): + f.write("// const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \ + (regN, regno)) + elif (regid == "d"): + f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \ + (regN, regno)) + f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \ + (regN, predicated)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "M"): + if (regid == "u"): + f.write("// const int %s = insn->regno[%d];\n"% \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "V"): + newv = "EXT_DFL" + if (hex_common.is_new_result(tag)): + newv = "EXT_NEW" + elif (hex_common.is_tmp_result(tag)): + newv = "EXT_TMP" + if (regid in {"dd", "xx"}): + f.write(" const int %s = insn->regno[%d];\n" %\ + (regN, regno)) + f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \ + (regN, newv, predicated)) + elif (regid in {"uu", "vv"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s", "u", "v", "w"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d", "x", "y"}): + f.write(" const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \ + (regN, newv, predicated)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "Q"): + if (regid in {"d", "e", "x"}): + f.write(" const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN)) + elif (regid in {"s", "t", "u", "v"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "G"): + if (regid in {"dd"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"ss"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "S"): + if (regid in {"dd"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"ss"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + else: + print("Bad register parse: ", regtype, regid) + +def analyze_opn_new(f, tag, regtype, regid, regno): + regN = "%s%sN" % (regtype, regid) + if (regtype == "N"): + if (regid in {"s", "t"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "P"): + if (regid in {"t", "u", "v"}): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype == "O"): + if (regid == "s"): + f.write("// const int %s = insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + else: + print("Bad register parse: ", regtype, regid) + +def analyze_opn(f, tag, regtype, regid, toss, numregs, i): + if (hex_common.is_pair(regid)): + analyze_opn_old(f, tag, regtype, regid, i) + elif (hex_common.is_single(regid)): + if hex_common.is_old_val(regtype, regid, tag): + analyze_opn_old(f,tag, regtype, regid, i) + elif hex_common.is_new_val(regtype, regid, tag): + analyze_opn_new(f, tag, regtype, regid, i) + else: + print("Bad register parse: ", regtype, regid, toss, numregs) + else: + print("Bad register parse: ", regtype, regid, toss, numregs) + +## +## Generate the code to analyze the instruction +## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;} +## We produce: +## static void analyze_A2_add(DisasContext *ctx) +## { +## Insn *insn G_GNUC_UNUSED = ctx->insn; +## const int RdN = insn->regno[0]; +## ctx_log_reg_write(ctx, RdN, false); +## // const int RsN = insn->regno[1]; +## // const int RtN = insn->regno[2]; +## } +## +def gen_analyze_func(f, tag, regs, imms): + f.write("static void analyze_%s(DisasContext *ctx)\n" %tag) + f.write('{\n') + + f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n") + + i=0 + ## Analyze all the registers + for regtype, regid, toss, numregs in regs: + analyze_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + + has_generated_helper = (not hex_common.skip_qemu_helper(tag) and + not hex_common.is_idef_parser_enabled(tag)) + if (has_generated_helper and + 'A_SCALAR_LOAD' in hex_common.attribdict[tag]): + f.write(" ctx->need_pkt_has_store_s1 = true;\n") + + f.write("}\n\n") + +def main(): + hex_common.read_semantics_file(sys.argv[1]) + hex_common.read_attribs_file(sys.argv[2]) + hex_common.read_overrides_file(sys.argv[3]) + hex_common.read_overrides_file(sys.argv[4]) + ## Whether or not idef-parser is enabled is + ## determined by the number of arguments to + ## this script: + ## + ## 5 args. -> not enabled, + ## 6 args. -> idef-parser enabled. + ## + ## The 6:th arg. then holds a list of the successfully + ## parsed instructions. + is_idef_parser_enabled = len(sys.argv) > 6 + if is_idef_parser_enabled: + hex_common.read_idef_parser_enabled_file(sys.argv[5]) + hex_common.calculate_attribs() + tagregs = hex_common.get_tagregs() + tagimms = hex_common.get_tagimms() + + with open(sys.argv[-1], 'w') as f: + f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") + f.write("#define HEXAGON_TCG_FUNCS_H\n\n") + + for tag in hex_common.tags: + gen_analyze_func(f, tag, tagregs[tag], tagimms[tag]) + + f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n") + +if __name__ == "__main__": + main() diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper_funcs.py index 19e9883f4c..7a224b66e6 100755 --- a/target/hexagon/gen_helper_funcs.py +++ b/target/hexagon/gen_helper_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ## -## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -226,6 +226,14 @@ def gen_helper_function(f, tag, tagregs, tagimms): print("Bad register parse: ",regtype,regid,toss,numregs) i += 1 + ## For conditional instructions, we pass in the destination register + if 'A_CONDEXEC' in hex_common.attribdict[tag]: + for regtype, regid, toss, numregs in regs: + if (hex_common.is_writeonly(regid) and + not hex_common.is_hvx_reg(regtype)): + gen_helper_arg_opn(f, regtype, regid, i, tag) + i += 1 + ## Arguments to the helper function are the source regs and immediates for regtype,regid,toss,numregs in regs: if (hex_common.is_read(regid)): @@ -262,10 +270,11 @@ def gen_helper_function(f, tag, tagregs, tagimms): if hex_common.need_ea(tag): gen_decl_ea(f) ## Declare the return variable i=0 - for regtype,regid,toss,numregs in regs: - if (hex_common.is_writeonly(regid)): - gen_helper_dest_decl_opn(f,regtype,regid,i) - i += 1 + if 'A_CONDEXEC' not in hex_common.attribdict[tag]: + for regtype,regid,toss,numregs in regs: + if (hex_common.is_writeonly(regid)): + gen_helper_dest_decl_opn(f,regtype,regid,i) + i += 1 for regtype,regid,toss,numregs in regs: if (hex_common.is_read(regid)): diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helper_protos.py index 674bf370fa..ddddc9e4f0 100755 --- a/target/hexagon/gen_helper_protos.py +++ b/target/hexagon/gen_helper_protos.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ## -## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -87,6 +87,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): if hex_common.need_slot(tag): def_helper_size += 1 if hex_common.need_PC(tag): def_helper_size += 1 if hex_common.helper_needs_next_PC(tag): def_helper_size += 1 + if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1 f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag)) ## The return type is void f.write(', void' ) @@ -96,6 +97,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): if hex_common.need_part1(tag): def_helper_size += 1 if hex_common.need_slot(tag): def_helper_size += 1 if hex_common.need_PC(tag): def_helper_size += 1 + if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1 if hex_common.helper_needs_next_PC(tag): def_helper_size += 1 f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag)) @@ -121,6 +123,14 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i) i += 1 + ## For conditional instructions, we pass in the destination register + if 'A_CONDEXEC' in hex_common.attribdict[tag]: + for regtype, regid, toss, numregs in regs: + if (hex_common.is_writeonly(regid) and + not hex_common.is_hvx_reg(regtype)): + gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i) + i += 1 + ## Generate the qemu type for each input operand (regs and immediates) for regtype,regid,toss,numregs in regs: if (hex_common.is_read(regid)): diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index b2e7880b5c..bcf0cf466a 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -332,8 +332,6 @@ tcg_gen_movi_tl(EA, 0); \ PRED; \ CHECK_NOSHUF_PRED(GET_EA, SIZE, LSB); \ - PRED_LOAD_CANCEL(LSB, EA); \ - tcg_gen_movi_tl(RdV, 0); \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ fLOAD(1, SIZE, SIGN, EA, RdV); \ gen_set_label(label); \ @@ -391,8 +389,6 @@ tcg_gen_movi_tl(EA, 0); \ PRED; \ CHECK_NOSHUF_PRED(GET_EA, 8, LSB); \ - PRED_LOAD_CANCEL(LSB, EA); \ - tcg_gen_movi_i64(RddV, 0); \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ fLOAD(1, 8, u, EA, RddV); \ gen_set_label(label); \ @@ -419,16 +415,16 @@ #define fGEN_TCG_STORE(SHORTCODE) \ do { \ - TCGv HALF = tcg_temp_new(); \ - TCGv BYTE = tcg_temp_new(); \ + TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \ + TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \ SHORTCODE; \ } while (0) #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ do { \ TCGv ireg = tcg_temp_new(); \ - TCGv HALF = tcg_temp_new(); \ - TCGv BYTE = tcg_temp_new(); \ + TCGv HALF G_GNUC_UNUSED = tcg_temp_new(); \ + TCGv BYTE G_GNUC_UNUSED = tcg_temp_new(); \ tcg_gen_mov_tl(EA, RxV); \ gen_read_ireg(ireg, MuV, SHIFT); \ gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ @@ -492,6 +488,59 @@ fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) /* + * dealloc_return + * Assembler mapped to + * r31:30 = dealloc_return(r30):raw + */ +#define fGEN_TCG_L4_return(SHORTCODE) \ + gen_return(ctx, RddV, RsV) + +/* + * sub-instruction version (no RddV, so handle it manually) + */ +#define fGEN_TCG_SL2_return(SHORTCODE) \ + do { \ + TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP); \ + gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \ + gen_log_reg_write_pair(HEX_REG_FP, RddV); \ + } while (0) + +/* + * Conditional returns follow this naming convention + * _t predicate true + * _f predicate false + * _tnew_pt predicate.new true predict taken + * _fnew_pt predicate.new false predict taken + * _tnew_pnt predicate.new true predict not taken + * _fnew_pnt predicate.new false predict not taken + * Predictions are not modelled in QEMU + * + * Example: + * if (p1) r31:30 = dealloc_return(r30):raw + */ +#define fGEN_TCG_L4_return_t(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ); +#define fGEN_TCG_L4_return_f(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE) +#define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) +#define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) +#define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) +#define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) + +#define fGEN_TCG_SL2_return_t(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0]) +#define fGEN_TCG_SL2_return_f(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0]) +#define fGEN_TCG_SL2_return_tnew(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_new_pred_value[0]) +#define fGEN_TCG_SL2_return_fnew(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_new_pred_value[0]) + +/* * Mathematical operations with more than one definition require * special handling */ @@ -589,14 +638,24 @@ #define fGEN_TCG_J2_call(SHORTCODE) \ gen_call(ctx, riV) +#define fGEN_TCG_J2_callr(SHORTCODE) \ + gen_callr(ctx, RsV) #define fGEN_TCG_J2_callt(SHORTCODE) \ gen_cond_call(ctx, PuV, TCG_COND_EQ, riV) #define fGEN_TCG_J2_callf(SHORTCODE) \ gen_cond_call(ctx, PuV, TCG_COND_NE, riV) +#define fGEN_TCG_J2_callrt(SHORTCODE) \ + gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV) +#define fGEN_TCG_J2_callrf(SHORTCODE) \ + gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV) #define fGEN_TCG_J2_endloop0(SHORTCODE) \ gen_endloop0(ctx) +#define fGEN_TCG_J2_endloop1(SHORTCODE) \ + gen_endloop1(ctx) +#define fGEN_TCG_J2_endloop01(SHORTCODE) \ + gen_endloop01(ctx) /* * Compound compare and jump instructions @@ -986,6 +1045,19 @@ #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \ gen_asl_r_r_sat(RdV, RsV, RtV) +#define fGEN_TCG_SL2_jumpr31(SHORTCODE) \ + gen_jumpr(ctx, hex_gpr[HEX_REG_LR]) + +#define fGEN_TCG_SL2_jumpr31_t(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_pred[0]) +#define fGEN_TCG_SL2_jumpr31_f(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_NE, hex_pred[0]) + +#define fGEN_TCG_SL2_jumpr31_tnew(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_new_pred_value[0]) +#define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0]) + /* Floating point */ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ gen_helper_conv_sf2df(RddV, cpu_env, RsV) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index 02cb52c21e..fa93e185ce 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ## -## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -30,37 +30,33 @@ def gen_decl_ea_tcg(f, tag): def genptr_decl_pair_writable(f, tag, regtype, regid, regno): regN="%s%sN" % (regtype,regid) - f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \ - (regtype, regid)) - if (regtype == "C"): + if (regtype == "R"): + f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) + elif (regtype == "C"): f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \ (regN, regno)) else: - f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - f.write(" if (!is_preloaded(ctx, %s)) {\n" % regN) - f.write(" tcg_gen_mov_tl(hex_new_value[%s], hex_gpr[%s]);\n" % \ - (regN, regN)) - f.write(" }\n") - f.write(" if (!is_preloaded(ctx, %s + 1)) {\n" % regN) - f.write(" tcg_gen_mov_tl(hex_new_value[%s + 1], hex_gpr[%s + 1]);\n" % \ - (regN, regN)) - f.write(" }\n") + print("Bad register parse: ", regtype, regid) + f.write(" TCGv_i64 %s%sV = get_result_gpr_pair(ctx, %s);\n" % \ + (regtype, regid, regN)) def genptr_decl_writable(f, tag, regtype, regid, regno): regN="%s%sN" % (regtype,regid) - f.write(" TCGv %s%sV = tcg_temp_new();\n" % \ - (regtype, regid)) - if (regtype == "C"): + if (regtype == "R"): + f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) + f.write(" TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \ + (regtype, regid, regN)) + elif (regtype == "C"): f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \ (regN, regno)) - else: + f.write(" TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \ + (regtype, regid, regN)) + elif (regtype == "P"): f.write(" const int %s = insn->regno[%d];\n" % (regN, regno)) - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - f.write(" if (!is_preloaded(ctx, %s)) {\n" % regN) - f.write(" tcg_gen_mov_tl(hex_new_value[%s], hex_gpr[%s]);\n" % \ - (regN, regN)) - f.write(" }\n") + f.write(" TCGv %s%sV = tcg_temp_new();\n" % \ + (regtype, regid)) + else: + print("Bad register parse: ", regtype, regid) def genptr_decl(f, tag, regtype, regid, regno): regN="%s%sN" % (regtype,regid) @@ -166,17 +162,6 @@ def genptr_decl(f, tag, regtype, regid, regno): f.write(" ctx_future_vreg_off(ctx, %s%sN," % \ (regtype, regid)) f.write(" 1, true);\n"); - if 'A_CONDEXEC' in hex_common.attribdict[tag]: - f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % (regN)) - f.write(" intptr_t src_off =") - f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \ - (regtype, regid)) - f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \ - (regtype, regid)) - f.write(" src_off,\n") - f.write(" sizeof(MMVector),\n") - f.write(" sizeof(MMVector));\n") - f.write(" }\n") if (not hex_common.skip_qemu_helper(tag)): f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \ @@ -191,8 +176,7 @@ def genptr_decl(f, tag, regtype, regid, regno): (regtype, regid, regno)) f.write(" const intptr_t %s%sV_off =\n" % \ (regtype, regid)) - f.write(" offsetof(CPUHexagonState,\n") - f.write(" future_QRegs[%s%sN]);\n" % \ + f.write(" get_result_qreg(ctx, %s%sN);\n" % \ (regtype, regid)) if (not hex_common.skip_qemu_helper(tag)): f.write(" TCGv_ptr %s%sV = tcg_temp_new_ptr();\n" % \ @@ -274,8 +258,12 @@ def genptr_src_read(f, tag, regtype, regid): f.write(" hex_gpr[%s%sN + 1]);\n" % \ (regtype, regid)) elif (regid in {"x", "y"}): - f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \ - (regtype,regid,regtype,regid)) + ## For read/write registers, we need to get the original value into + ## the result TCGv. For conditional instructions, this is done in + ## gen_start_packet. For unconditional instructions, we do it here. + if ('A_CONDEXEC' not in hex_common.attribdict[tag]): + f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \ + (regtype, regid, regtype, regid)) elif (regid not in {"s", "t", "u", "v"}): print("Bad register parse: ", regtype, regid) elif (regtype == "P"): @@ -385,37 +373,22 @@ def gen_helper_call_imm(f,immlett): f.write(", tcgv_%s" % hex_common.imm_name(immlett)) def genptr_dst_write_pair(f, tag, regtype, regid): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - f.write(" gen_log_predicated_reg_write_pair(%s%sN, %s%sV, insn->slot);\n" % \ - (regtype, regid, regtype, regid)) - else: - f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \ - (regtype, regid, regtype, regid)) - f.write(" ctx_log_reg_write_pair(ctx, %s%sN);\n" % \ - (regtype, regid)) + f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \ + (regtype, regid, regtype, regid)) def genptr_dst_write(f, tag, regtype, regid): if (regtype == "R"): if (regid in {"dd", "xx", "yy"}): genptr_dst_write_pair(f, tag, regtype, regid) elif (regid in {"d", "e", "x", "y"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - f.write(" gen_log_predicated_reg_write(%s%sN, %s%sV,\n" % \ - (regtype, regid, regtype, regid)) - f.write(" insn->slot);\n") - else: - f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \ - (regtype, regid, regtype, regid)) - f.write(" ctx_log_reg_write(ctx, %s%sN);\n" % \ - (regtype, regid)) + f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \ + (regtype, regid, regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype == "P"): if (regid in {"d", "e", "x"}): f.write(" gen_log_pred_write(ctx, %s%sN, %s%sV);\n" % \ (regtype, regid, regtype, regid)) - f.write(" ctx_log_pred_write(ctx, %s%sN);\n" % \ - (regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype == "C"): @@ -432,43 +405,18 @@ def genptr_dst_write(f, tag, regtype, regid): def genptr_dst_write_ext(f, tag, regtype, regid, newv="EXT_DFL"): if (regtype == "V"): - if (regid in {"dd", "xx", "yy"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - is_predicated = "true" - else: - is_predicated = "false" + if (regid in {"xx"}): f.write(" gen_log_vreg_write_pair(ctx, %s%sV_off, %s%sN, " % \ (regtype, regid, regtype, regid)) - f.write("%s, insn->slot, %s);\n" % \ - (newv, is_predicated)) - f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s,\n" % \ - (regtype, regid, newv)) - f.write(" %s);\n" % (is_predicated)) - elif (regid in {"d", "x", "y"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - is_predicated = "true" - else: - is_predicated = "false" - f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s, " % \ + f.write("%s);\n" % \ + (newv)) + elif (regid in {"y"}): + f.write(" gen_log_vreg_write(ctx, %s%sV_off, %s%sN, %s);\n" % \ (regtype, regid, regtype, regid, newv)) - f.write("insn->slot, %s);\n" % \ - (is_predicated)) - f.write(" ctx_log_vreg_write(ctx, %s%sN, %s, %s);\n" % \ - (regtype, regid, newv, is_predicated)) - else: + elif (regid not in {"dd", "d", "x"}): print("Bad register parse: ", regtype, regid) elif (regtype == "Q"): - if (regid in {"d", "e", "x"}): - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - is_predicated = "true" - else: - is_predicated = "false" - f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \ - (regtype, regid, regtype, regid, newv)) - f.write("insn->slot, %s);\n" % (is_predicated)) - f.write(" ctx_log_qreg_write(ctx, %s%sN, %s);\n" % \ - (regtype, regid, is_predicated)) - else: + if (regid not in {"d", "e", "x"}): print("Bad register parse: ", regtype, regid) else: print("Bad register parse: ", regtype, regid) @@ -500,15 +448,15 @@ def genptr_dst_write_opn(f,regtype, regid, tag): ## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;} ## We produce: ## static void generate_A2_add(DisasContext *ctx) -## { -## TCGv RdV = tcg_temp_new(); -## const int RdN = insn->regno[0]; -## TCGv RsV = hex_gpr[insn->regno[1]]; -## TCGv RtV = hex_gpr[insn->regno[2]]; -## <GEN> -## gen_log_reg_write(RdN, RdV); -## ctx_log_reg_write(ctx, RdN); -## } +## { +## Insn *insn __attribute__((unused)) = ctx->insn; +## const int RdN = insn->regno[0]; +## TCGv RdV = get_result_gpr(ctx, RdN); +## TCGv RsV = hex_gpr[insn->regno[1]]; +## TCGv RtV = hex_gpr[insn->regno[2]]; +## <GEN> +## gen_log_reg_write(RdN, RdV); +## } ## ## where <GEN> depends on hex_common.skip_qemu_helper(tag) ## if hex_common.skip_qemu_helper(tag) is True @@ -592,6 +540,14 @@ def gen_tcg_func(f, tag, regs, imms): if (i > 0): f.write(", ") f.write("cpu_env") i=1 + ## For conditional instructions, we pass in the destination register + if 'A_CONDEXEC' in hex_common.attribdict[tag]: + for regtype, regid, toss, numregs in regs: + if (hex_common.is_writeonly(regid) and + not hex_common.is_hvx_reg(regtype)): + gen_helper_call_opn(f, tag, regtype, regid, toss, \ + numregs, i) + i += 1 for regtype,regid,toss,numregs in regs: if (hex_common.is_written(regid)): if (not hex_common.is_hvx_reg(regtype)): diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 94f272e286..d4aefe8e3f 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -133,16 +133,11 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv lsb = tcg_temp_new(); \ TCGLabel *false_label = gen_new_label(); \ - TCGLabel *end_label = gen_new_label(); \ tcg_gen_andi_tl(lsb, PsV, 1); \ tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_br(end_label); \ gen_set_label(false_label); \ - tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \ - 1 << insn->slot); \ - gen_set_label(end_label); \ } while (0) @@ -547,17 +542,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv LSB = tcg_temp_new(); \ TCGLabel *false_label = gen_new_label(); \ - TCGLabel *end_label = gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ gen_vreg_load(ctx, DSTOFF, EA, true); \ INC; \ - tcg_gen_br(end_label); \ gen_set_label(false_label); \ - tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \ - 1 << insn->slot); \ - gen_set_label(end_label); \ } while (0) #define fGEN_TCG_PRED_VEC_LOAD_pred_pi \ @@ -717,17 +707,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv LSB = tcg_temp_new(); \ TCGLabel *false_label = gen_new_label(); \ - TCGLabel *end_label = gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \ INC; \ - tcg_gen_br(end_label); \ gen_set_label(false_label); \ - tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \ - 1 << insn->slot); \ - gen_set_label(end_label); \ } while (0) #define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 86bd093ce8..bb274d4a71 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -68,26 +68,17 @@ static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val, } } -static inline void gen_log_predicated_reg_write(int rnum, TCGv val, - uint32_t slot) +static TCGv get_result_gpr(DisasContext *ctx, int rnum) { - TCGv zero = tcg_constant_tl(0); - TCGv slot_mask = tcg_temp_new(); + return hex_new_value[rnum]; +} - tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); - tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, - val, hex_new_value[rnum]); - if (HEX_DEBUG) { - /* - * Do this so HELPER(debug_commit_end) will know - * - * Note that slot_mask indicates the value is not written - * (i.e., slot was cancelled), so we create a true/false value before - * or'ing with hex_reg_written[rnum]. - */ - tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); - tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); - } +static TCGv_i64 get_result_gpr_pair(DisasContext *ctx, int rnum) +{ + TCGv_i64 result = tcg_temp_new_i64(); + tcg_gen_concat_i32_i64(result, hex_new_value[rnum], + hex_new_value[rnum + 1]); + return result; } void gen_log_reg_write(int rnum, TCGv val) @@ -102,39 +93,6 @@ void gen_log_reg_write(int rnum, TCGv val) } } -static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, - uint32_t slot) -{ - TCGv val32 = tcg_temp_new(); - TCGv zero = tcg_constant_tl(0); - TCGv slot_mask = tcg_temp_new(); - - tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); - /* Low word */ - tcg_gen_extrl_i64_i32(val32, val); - tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], - slot_mask, zero, - val32, hex_new_value[rnum]); - /* High word */ - tcg_gen_extrh_i64_i32(val32, val); - tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1], - slot_mask, zero, - val32, hex_new_value[rnum + 1]); - if (HEX_DEBUG) { - /* - * Do this so HELPER(debug_commit_end) will know - * - * Note that slot_mask indicates the value is not written - * (i.e., slot was cancelled), so we create a true/false value before - * or'ing with hex_reg_written[rnum]. - */ - tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); - tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); - tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1], - slot_mask); - } -} - static void gen_log_reg_write_pair(int rnum, TCGv_i64 val) { const target_ulong reg_mask_low = reg_immut_masks[rnum]; @@ -180,6 +138,7 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) hex_new_pred_value[pnum], base_val); } tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); + set_bit(pnum, ctx->pregs_written); } static inline void gen_read_p3_0(TCGv control_reg) @@ -256,7 +215,6 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg) for (int i = 0; i < NUM_PREGS; i++) { tcg_gen_extract_tl(hex_p8, control_reg, i * 8, 8); gen_log_pred_write(ctx, i, hex_p8); - ctx_log_pred_write(ctx, i); } } @@ -274,7 +232,6 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num, gen_write_p3_0(ctx, val); } else { gen_log_reg_write(reg_num, val); - ctx_log_reg_write(ctx, reg_num); if (reg_num == HEX_REG_QEMU_PKT_CNT) { ctx->num_packets = 0; } @@ -291,15 +248,14 @@ static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num, TCGv_i64 val) { if (reg_num == HEX_REG_P3_0_ALIASED) { + TCGv result = get_result_gpr(ctx, reg_num + 1); TCGv val32 = tcg_temp_new(); tcg_gen_extrl_i64_i32(val32, val); gen_write_p3_0(ctx, val32); tcg_gen_extrh_i64_i32(val32, val); - gen_log_reg_write(reg_num + 1, val32); - ctx_log_reg_write(ctx, reg_num + 1); + tcg_gen_mov_tl(result, val32); } else { gen_log_reg_write_pair(reg_num, val); - ctx_log_reg_write_pair(ctx, reg_num); if (reg_num == HEX_REG_QEMU_PKT_CNT) { ctx->num_packets = 0; ctx->num_insns = 0; @@ -571,6 +527,13 @@ static void gen_cond_jumpr(DisasContext *ctx, TCGv dst_pc, gen_write_new_pc_addr(ctx, dst_pc, cond, pred); } +static void gen_cond_jumpr31(DisasContext *ctx, TCGCond cond, TCGv pred) +{ + TCGv LSB = tcg_temp_new(); + tcg_gen_andi_tl(LSB, pred, 1); + gen_cond_jumpr(ctx, hex_gpr[HEX_REG_LR], cond, LSB); +} + static void gen_cond_jump(DisasContext *ctx, TCGCond cond, TCGv pred, int pc_off) { @@ -669,27 +632,99 @@ static void gen_jumpr(DisasContext *ctx, TCGv new_pc) static void gen_call(DisasContext *ctx, int pc_off) { - TCGv next_PC = - tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes); - gen_log_reg_write(HEX_REG_LR, next_PC); + TCGv lr = get_result_gpr(ctx, HEX_REG_LR); + tcg_gen_movi_tl(lr, ctx->next_PC); gen_write_new_pc_pcrel(ctx, pc_off, TCG_COND_ALWAYS, NULL); } +static void gen_callr(DisasContext *ctx, TCGv new_pc) +{ + TCGv lr = get_result_gpr(ctx, HEX_REG_LR); + tcg_gen_movi_tl(lr, ctx->next_PC); + gen_write_new_pc_addr(ctx, new_pc, TCG_COND_ALWAYS, NULL); +} + static void gen_cond_call(DisasContext *ctx, TCGv pred, TCGCond cond, int pc_off) { - TCGv next_PC; + TCGv lr = get_result_gpr(ctx, HEX_REG_LR); TCGv lsb = tcg_temp_new(); TCGLabel *skip = gen_new_label(); tcg_gen_andi_tl(lsb, pred, 1); gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb); tcg_gen_brcondi_tl(cond, lsb, 0, skip); - next_PC = - tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes); - gen_log_reg_write(HEX_REG_LR, next_PC); + tcg_gen_movi_tl(lr, ctx->next_PC); gen_set_label(skip); } +static void gen_cond_callr(DisasContext *ctx, + TCGCond cond, TCGv pred, TCGv new_pc) +{ + TCGv lsb = tcg_temp_new(); + TCGLabel *skip = gen_new_label(); + tcg_gen_andi_tl(lsb, pred, 1); + tcg_gen_brcondi_tl(cond, lsb, 0, skip); + gen_callr(ctx, new_pc); + gen_set_label(skip); +} + +/* frame ^= (int64_t)FRAMEKEY << 32 */ +static void gen_frame_unscramble(TCGv_i64 frame) +{ + TCGv_i64 framekey = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(framekey, hex_gpr[HEX_REG_FRAMEKEY]); + tcg_gen_shli_i64(framekey, framekey, 32); + tcg_gen_xor_i64(frame, frame, framekey); +} + +static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA) +{ + Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */ + CHECK_NOSHUF(EA, 8); + tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx); +} + +static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src) +{ + /* + * frame = *src + * dst = frame_unscramble(frame) + * SP = src + 8 + * PC = dst.w[1] + */ + TCGv_i64 frame = tcg_temp_new_i64(); + TCGv r31 = tcg_temp_new(); + TCGv r29 = get_result_gpr(ctx, HEX_REG_SP); + + gen_load_frame(ctx, frame, src); + gen_frame_unscramble(frame); + tcg_gen_mov_i64(dst, frame); + tcg_gen_addi_tl(r29, src, 8); + tcg_gen_extrh_i64_i32(r31, dst); + gen_jumpr(ctx, r31); +} + +/* if (pred) dst = dealloc_return(src):raw */ +static void gen_cond_return(DisasContext *ctx, TCGv_i64 dst, TCGv src, + TCGv pred, TCGCond cond) +{ + TCGv LSB = tcg_temp_new(); + TCGLabel *skip = gen_new_label(); + tcg_gen_andi_tl(LSB, pred, 1); + + tcg_gen_brcondi_tl(cond, LSB, 0, skip); + gen_return(ctx, dst, src); + gen_set_label(skip); +} + +/* sub-instruction version (no RddV, so handle it manually) */ +static void gen_cond_return_subinsn(DisasContext *ctx, TCGCond cond, TCGv pred) +{ + TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP); + gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond); + gen_log_reg_write_pair(HEX_REG_FP, RddV); +} + static void gen_endloop0(DisasContext *ctx) { TCGv lpcfg = tcg_temp_new(); @@ -737,14 +772,95 @@ static void gen_endloop0(DisasContext *ctx) TCGLabel *label3 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3); { + TCGv lc0 = get_result_gpr(ctx, HEX_REG_LC0); gen_jumpr(ctx, hex_gpr[HEX_REG_SA0]); - tcg_gen_subi_tl(hex_new_value[HEX_REG_LC0], - hex_gpr[HEX_REG_LC0], 1); + tcg_gen_subi_tl(lc0, hex_gpr[HEX_REG_LC0], 1); } gen_set_label(label3); } } +static void gen_endloop1(DisasContext *ctx) +{ + /* + * if (hex_gpr[HEX_REG_LC1] > 1) { + * PC = hex_gpr[HEX_REG_SA1]; + * hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1; + * } + */ + TCGLabel *label = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, label); + { + TCGv lc1 = get_result_gpr(ctx, HEX_REG_LC1); + gen_jumpr(ctx, hex_gpr[HEX_REG_SA1]); + tcg_gen_subi_tl(lc1, hex_gpr[HEX_REG_LC1], 1); + } + gen_set_label(label); +} + +static void gen_endloop01(DisasContext *ctx) +{ + TCGv lpcfg = tcg_temp_new(); + TCGLabel *label1 = gen_new_label(); + TCGLabel *label2 = gen_new_label(); + TCGLabel *label3 = gen_new_label(); + TCGLabel *done = gen_new_label(); + + GET_USR_FIELD(USR_LPCFG, lpcfg); + + /* + * if (lpcfg == 1) { + * hex_new_pred_value[3] = 0xff; + * hex_pred_written |= 1 << 3; + * } + */ + tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1); + { + tcg_gen_movi_tl(hex_new_pred_value[3], 0xff); + tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3); + } + gen_set_label(label1); + + /* + * if (lpcfg) { + * SET_USR_FIELD(USR_LPCFG, lpcfg - 1); + * } + */ + tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2); + { + tcg_gen_subi_tl(lpcfg, lpcfg, 1); + SET_USR_FIELD(USR_LPCFG, lpcfg); + } + gen_set_label(label2); + + /* + * if (hex_gpr[HEX_REG_LC0] > 1) { + * PC = hex_gpr[HEX_REG_SA0]; + * hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1; + * } else { + * if (hex_gpr[HEX_REG_LC1] > 1) { + * hex_next_pc = hex_gpr[HEX_REG_SA1]; + * hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1; + * } + * } + */ + tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3); + { + TCGv lc0 = get_result_gpr(ctx, HEX_REG_LC0); + gen_jumpr(ctx, hex_gpr[HEX_REG_SA0]); + tcg_gen_subi_tl(lc0, hex_gpr[HEX_REG_LC0], 1); + tcg_gen_br(done); + } + gen_set_label(label3); + tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, done); + { + TCGv lc1 = get_result_gpr(ctx, HEX_REG_LC1); + gen_jumpr(ctx, hex_gpr[HEX_REG_SA1]); + tcg_gen_subi_tl(lc1, hex_gpr[HEX_REG_LC1], 1); + } + gen_set_label(done); +} + static void gen_cmp_jumpnv(DisasContext *ctx, TCGCond cond, TCGv val, TCGv src, int pc_off) { @@ -869,68 +985,32 @@ static intptr_t vreg_src_off(DisasContext *ctx, int num) } static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num, - VRegWriteType type, int slot_num, - bool is_predicated) + VRegWriteType type) { - TCGLabel *label_end = NULL; intptr_t dstoff; - if (is_predicated) { - TCGv cancelled = tcg_temp_new(); - label_end = gen_new_label(); - - /* Don't do anything if the slot was cancelled */ - tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); - tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - } - if (type != EXT_TMP) { dstoff = ctx_future_vreg_off(ctx, num, 1, true); tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVector)); - tcg_gen_ori_tl(hex_VRegs_updated, hex_VRegs_updated, 1 << num); } else { dstoff = ctx_tmp_vreg_off(ctx, num, 1, false); tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVector)); } - - if (is_predicated) { - gen_set_label(label_end); - } } static void gen_log_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int num, - VRegWriteType type, int slot_num, - bool is_predicated) + VRegWriteType type) { - gen_log_vreg_write(ctx, srcoff, num ^ 0, type, slot_num, is_predicated); + gen_log_vreg_write(ctx, srcoff, num ^ 0, type); srcoff += sizeof(MMVector); - gen_log_vreg_write(ctx, srcoff, num ^ 1, type, slot_num, is_predicated); + gen_log_vreg_write(ctx, srcoff, num ^ 1, type); } -static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew, - int slot_num, bool is_predicated) +static intptr_t get_result_qreg(DisasContext *ctx, int qnum) { - TCGLabel *label_end = NULL; - intptr_t dstoff; - - if (is_predicated) { - TCGv cancelled = tcg_temp_new(); - label_end = gen_new_label(); - - /* Don't do anything if the slot was cancelled */ - tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); - tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - } - - dstoff = offsetof(CPUHexagonState, future_QRegs[num]); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMQReg), sizeof(MMQReg)); - - if (is_predicated) { - tcg_gen_ori_tl(hex_QRegs_updated, hex_QRegs_updated, 1 << num); - gen_set_label(label_end); - } + return offsetof(CPUHexagonState, future_QRegs[qnum]); } static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src, diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index a29f61bb4f..0200a66cb6 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ## -## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -89,6 +89,7 @@ def calculate_attribs(): add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG') add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR') add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR') + add_qemu_macro_attrib('fLOAD', 'A_SCALAR_LOAD') add_qemu_macro_attrib('fSTORE', 'A_SCALAR_STORE') # Recurse down macros, find attributes from sub-macros @@ -236,6 +237,13 @@ def helper_needs_next_PC(tag): def need_pkt_has_multi_cof(tag): return 'A_COF' in attribdict[tag] +def need_condexec_reg(tag, regs): + if 'A_CONDEXEC' in attribdict[tag]: + for regtype, regid, toss, numregs in regs: + if is_writeonly(regid) and not is_hvx_reg(regtype): + return True + return False + def skip_qemu_helper(tag): return tag in overrides.keys() diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef-parser/idef-parser.h index 17d2ebfaf6..d23e71f13b 100644 --- a/target/hexagon/idef-parser/idef-parser.h +++ b/target/hexagon/idef-parser/idef-parser.h @@ -82,7 +82,6 @@ enum ImmUnionTag { VALUE, QEMU_TMP, IMM_PC, - IMM_NPC, IMM_CONSTEXT, }; diff --git a/target/hexagon/idef-parser/idef-parser.lex b/target/hexagon/idef-parser/idef-parser.lex index ff87a02c3a..5eb8ac5a80 100644 --- a/target/hexagon/idef-parser/idef-parser.lex +++ b/target/hexagon/idef-parser/idef-parser.lex @@ -5,7 +5,7 @@ %{ /* - * Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved. + * Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -140,8 +140,6 @@ STRING_LIT \"(\\.|[^"\\])*\" yylval->rvalue.is_dotnew = true; yylval->rvalue.signedness = SIGNED; return PRED; } -"IV1DEAD()" | -"fPAUSE(uiV);" { return ';'; } "+=" { return INC; } "-=" { return DEC; } "++" { return PLUSPLUS; } @@ -159,9 +157,8 @@ STRING_LIT \"(\\.|[^"\\])*\" "else" { return ELSE; } "for" { return FOR; } "fREAD_IREG" { return ICIRC; } -"fPART1" { return PART1; } "if" { return IF; } -"fFRAME_SCRAMBLE" { return FSCR; } +"fFRAME_SCRAMBLE" | "fFRAME_UNSCRAMBLE" { return FSCR; } "fFRAMECHECK" { return FCHK; } "Constant_extended" { return CONSTEXT; } @@ -312,14 +309,10 @@ STRING_LIT \"(\\.|[^"\\])*\" "(unsigned int)" { yylval->cast.bit_width = 32; yylval->cast.signedness = UNSIGNED; return CAST; } -"fREAD_PC()" | -"PC" { return PC; } -"fREAD_NPC()" | -"NPC" { return NPC; } -"fGET_LPCFG" | +"fREAD_PC()" { return PC; } "USR.LPCFG" { return LPCFG; } "LOAD_CANCEL(EA)" { return LOAD_CANCEL; } -"STORE_CANCEL(EA)" | +"STORE_CANCEL(EA)" { return STORE_CANCEL; } "CANCEL" { return CANCEL; } "N"{LOWER_ID}"N" { yylval->rvalue.type = REGISTER_ARG; yylval->rvalue.reg.type = DOTNEW; @@ -360,14 +353,6 @@ STRING_LIT \"(\\.|[^"\\])*\" yylval->rvalue.bit_width = 32; yylval->rvalue.signedness = UNSIGNED; return REG; } -"fREAD_LC"[01] { yylval->rvalue.type = REGISTER; - yylval->rvalue.reg.type = CONTROL; - yylval->rvalue.reg.id = HEX_REG_LC0 - + (yytext[8] - '0') * 2; - yylval->rvalue.reg.bit_width = 32; - yylval->rvalue.bit_width = 32; - yylval->rvalue.signedness = UNSIGNED; - return REG; } "LC"[01] { yylval->rvalue.type = REGISTER; yylval->rvalue.reg.type = CONTROL; yylval->rvalue.reg.id = HEX_REG_LC0 @@ -376,14 +361,6 @@ STRING_LIT \"(\\.|[^"\\])*\" yylval->rvalue.bit_width = 32; yylval->rvalue.signedness = UNSIGNED; return REG; } -"fREAD_SA"[01] { yylval->rvalue.type = REGISTER; - yylval->rvalue.reg.type = CONTROL; - yylval->rvalue.reg.id = HEX_REG_SA0 - + (yytext[8] - '0') * 2; - yylval->rvalue.reg.bit_width = 32; - yylval->rvalue.bit_width = 32; - yylval->rvalue.signedness = UNSIGNED; - return REG; } "SA"[01] { yylval->rvalue.type = REGISTER; yylval->rvalue.reg.type = CONTROL; yylval->rvalue.reg.id = HEX_REG_SA0 diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y index c784726d41..7d05773b67 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -1,6 +1,6 @@ %{ /* - * Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved. + * Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -52,8 +52,8 @@ %token IN INAME VAR %token ABS CROUND ROUND CIRCADD COUNTONES INC DEC ANDA ORA XORA PLUSPLUS ASL %token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK SXT -%token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC NPC LPCFG -%token LOAD_CANCEL CANCEL IDENTITY PART1 ROTL INSBITS SETBITS EXTRANGE +%token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC LPCFG +%token LOAD_CANCEL STORE_CANCEL CANCEL IDENTITY ROTL INSBITS SETBITS EXTRANGE %token CAST4_8U FAIL CARRY_FROM_ADD ADDSAT64 LSBNEW %token TYPE_SIZE_T TYPE_INT TYPE_SIGNED TYPE_UNSIGNED TYPE_LONG @@ -336,15 +336,6 @@ assign_statement : lvalue '=' rvalue OUT(c, &@1, &$1, " = ", &$3, ";\n"); $$ = $1; } - | PC '=' rvalue - { - @1.last_column = @3.last_column; - yyassert(c, &@1, !is_inside_ternary(c), - "Assignment side-effect not modeled!"); - $3 = gen_rvalue_truncate(c, &@1, &$3); - $3 = rvalue_materialize(c, &@1, &$3); - OUT(c, &@1, "gen_write_new_pc(", &$3, ");\n"); - } | LOAD '(' IMM ',' IMM ',' SIGN ',' var ',' lvalue ')' { @1.last_column = @12.last_column; @@ -412,7 +403,6 @@ control_statement : frame_check | cancel_statement | if_statement | for_statement - | fpart1_statement ; frame_check : FCHK '(' rvalue ',' rvalue ')' ';' @@ -422,10 +412,11 @@ cancel_statement : LOAD_CANCEL { gen_load_cancel(c, &@1); } - | CANCEL + | STORE_CANCEL { gen_cancel(c, &@1); } + | CANCEL ; if_statement : if_stmt @@ -462,17 +453,6 @@ for_statement : FOR '(' IMM '=' IMM ';' IMM '<' IMM ';' IMM PLUSPLUS ')' } ; -fpart1_statement : PART1 - { - OUT(c, &@1, "if (insn->part1) {\n"); - } - '(' statements ')' - { - @1.last_column = @3.last_column; - OUT(c, &@1, "return; }\n"); - } - ; - if_stmt : IF '(' rvalue ')' { @1.last_column = @3.last_column; @@ -512,20 +492,6 @@ rvalue : FAIL rvalue.signedness = UNSIGNED; $$ = rvalue; } - | NPC - { - /* - * NPC is only read from CALLs, so we can hardcode it - * at translation time - */ - HexValue rvalue; - memset(&rvalue, 0, sizeof(HexValue)); - rvalue.type = IMMEDIATE; - rvalue.imm.type = IMM_NPC; - rvalue.bit_width = 32; - rvalue.signedness = UNSIGNED; - $$ = rvalue; - } | CONSTEXT { HexValue rvalue; @@ -781,11 +747,6 @@ rvalue : FAIL /* Ones count */ $$ = gen_ctpop_op(c, &@1, &$3); } - | LPCFG - { - $$ = gen_tmp(c, &@1, 32, UNSIGNED); - OUT(c, &@1, "GET_USR_FIELD(USR_LPCFG, ", &$$, ");\n"); - } | EXTRACT '(' rvalue ',' rvalue ')' { @1.last_column = @6.last_column; diff --git a/target/hexagon/idef-parser/macros.inc b/target/hexagon/idef-parser/macros.inc index 6b697da87a..7478d4db17 100644 --- a/target/hexagon/idef-parser/macros.inc +++ b/target/hexagon/idef-parser/macros.inc @@ -97,16 +97,8 @@ #define fWRITE_LR(A) (LR = A) #define fWRITE_FP(A) (FP = A) #define fWRITE_SP(A) (SP = A) -/* - * Note: There is a rule in the parser that matches `PC = ...` and emits - * a call to `gen_write_new_pc`. We need to call `gen_write_new_pc` to - * get the correct semantics when there are multiple stores in a packet. - */ -#define fBRANCH(LOC, TYPE) (PC = LOC) -#define fJUMPR(REGNO, TARGET, TYPE) (PC = TARGET) #define fWRITE_LOOP_REGS0(START, COUNT) SA0 = START; (LC0 = COUNT) #define fWRITE_LOOP_REGS1(START, COUNT) SA1 = START; (LC1 = COUNT) -#define fWRITE_LC0(VAL) (LC0 = VAL) #define fWRITE_LC1(VAL) (LC1 = VAL) #define fSET_LPCFG(VAL) (USR.LPCFG = VAL) #define fWRITE_P0(VAL) P0 = VAL; @@ -121,7 +113,6 @@ #define fEA_GPI(IMM) (EA = fREAD_GP() + IMM) #define fPM_I(REG, IMM) (REG = REG + IMM) #define fPM_M(REG, MVAL) (REG = REG + MVAL) -#define fWRITE_NPC(VAL) (PC = VAL) /* Unary operators */ #define fROUND(A) (A + 0x8000) diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c index e1a55412c8..18cde6a1be 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved. + * Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -185,9 +185,6 @@ void imm_print(Context *c, YYLTYPE *locp, HexImm *imm) case IMM_PC: EMIT(c, "ctx->base.pc_next"); break; - case IMM_NPC: - EMIT(c, "ctx->npc"); - break; case IMM_CONSTEXT: EMIT(c, "insn->extension_valid"); break; @@ -1323,10 +1320,6 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexValue *reg, HexValue *value) locp, "gen_log_reg_write(", ®->reg.id, ", ", &value_m, ");\n"); - OUT(c, - locp, - "ctx_log_reg_write(ctx, ", ®->reg.id, - ");\n"); } void gen_assign(Context *c, @@ -1675,9 +1668,7 @@ void gen_inst_init_args(Context *c, YYLTYPE *locp) for (unsigned i = 0; i < c->inst.init_list->len; i++) { HexValue *val = &g_array_index(c->inst.init_list, HexValue, i); if (val->type == REGISTER_ARG) { - char reg_id[5]; - reg_compose(c, locp, &val->reg, reg_id); - EMIT_HEAD(c, "tcg_gen_movi_i%u(%s, 0);\n", val->bit_width, reg_id); + /* Nothing to do here */ } else if (val->type == PREDICATE) { char suffix = val->is_dotnew ? 'N' : 'V'; EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width, @@ -1722,13 +1713,10 @@ void gen_pred_assign(Context *c, YYLTYPE *locp, HexValue *left_pred, *left_pred = gen_tmp(c, locp, 32, UNSIGNED); } /* Extract first 8 bits, and store new predicate value */ - OUT(c, locp, "tcg_gen_mov_i32(", left_pred, ", ", &r, ");\n"); - OUT(c, locp, "tcg_gen_andi_i32(", left_pred, ", ", left_pred, - ", 0xff);\n"); + OUT(c, locp, "tcg_gen_andi_i32(", left_pred, ", ", &r, ", 0xff);\n"); if (is_direct) { OUT(c, locp, "gen_log_pred_write(ctx, ", pred_id, ", ", left_pred, ");\n"); - OUT(c, locp, "ctx_log_pred_write(ctx, ", pred_id, ");\n"); } } @@ -1739,7 +1727,6 @@ void gen_cancel(Context *c, YYLTYPE *locp) void gen_load_cancel(Context *c, YYLTYPE *locp) { - gen_cancel(c, locp); OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n"); OUT(c, locp, "ctx->s1_store_processed = false;\n"); OUT(c, locp, "process_store(ctx, 1);\n"); diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 17facadaad..482a9c787f 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -205,26 +205,11 @@ static inline void gen_cancel(uint32_t slot) #define CANCEL gen_cancel(slot); #else -#define CANCEL cancel_slot(env, slot) +#define CANCEL do { } while (0) #endif #define LOAD_CANCEL(EA) do { CANCEL; } while (0) -#ifdef QEMU_GENERATE -static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num) - { - TCGv slot_mask = tcg_temp_new(); - TCGv tmp = tcg_temp_new(); - TCGv zero = tcg_constant_tl(0); - tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num); - tcg_gen_andi_tl(tmp, pred, 1); - tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, - slot_mask, hex_slot_cancelled); -} -#define PRED_LOAD_CANCEL(PRED, EA) \ - gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot) -#endif - #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) @@ -415,16 +400,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) #define fHINTJR(TARGET) { /* Not modelled in qemu */} -#define fCALL(A) \ - do { \ - fWRITE_LR(fREAD_NPC()); \ - fBRANCH(A, COF_TYPE_CALL); \ - } while (0) -#define fCALLR(A) \ - do { \ - fWRITE_LR(fREAD_NPC()); \ - fBRANCH(A, COF_TYPE_CALLR); \ - } while (0) #define fWRITE_LOOP_REGS0(START, COUNT) \ do { \ WRITE_RREG(HEX_REG_LC0, COUNT); \ diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index c9d31d095c..da8e608d00 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -1,5 +1,5 @@ ## -## Copyright(c) 2020-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2020-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -183,7 +183,7 @@ if idef_parser_enabled and 'hexagon-linux-user' in target_dirs ) bison = generator( - find_program('bison'), + find_program('bison', version: '>=3.0'), output: ['@BASENAME@.tab.c', '@BASENAME@.tab.h'], arguments: ['@INPUT@', '--defines=@OUTPUT1@', '--output=@OUTPUT0@'] ) @@ -276,4 +276,13 @@ tcg_funcs_generated = custom_target( ) hexagon_ss.add(tcg_funcs_generated) +analyze_funcs_generated = custom_target( + 'analyze_funcs_generated.c.inc', + output: 'analyze_funcs_generated.c.inc', + depends: helper_dep, + depend_files: [hex_common_py, attribs_def, gen_tcg_h, gen_tcg_hvx_h], + command: [python, files('gen_analyze_funcs.py'), helper_in, '@OUTPUT@'], +) +hexagon_ss.add(analyze_funcs_generated) + target_arch += {'hexagon': hexagon_ss} diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 35449ef524..c9a156030e 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,6 +30,7 @@ #include "mmvec/mmvec.h" #include "mmvec/macros.h" #include "op_helper.h" +#include "translate.h" #define SF_BIAS 127 #define SF_MANTBITS 23 @@ -105,30 +106,6 @@ void log_store64(CPUHexagonState *env, target_ulong addr, env->mem_log_stores[slot].data64 = val; } -void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof, - target_ulong addr) -{ - HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); - - if (pkt_has_multi_cof) { - /* - * If more than one branch is taken in a packet, only the first one - * is actually done. - */ - if (env->branch_taken) { - HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " - "ignoring the second one\n"); - } else { - fCHECK_PCALIGN(addr); - env->gpr[HEX_REG_PC] = addr; - env->branch_taken = 1; - } - } else { - fCHECK_PCALIGN(addr); - env->gpr[HEX_REG_PC] = addr; - } -} - /* Handy place to set a breakpoint */ void HELPER(debug_start_packet)(CPUHexagonState *env) { @@ -439,9 +416,10 @@ int32_t HELPER(vacsh_pred)(CPUHexagonState *env, return PeV; } -static void probe_store(CPUHexagonState *env, int slot, int mmu_idx) +static void probe_store(CPUHexagonState *env, int slot, int mmu_idx, + bool is_predicated) { - if (!(env->slot_cancelled & (1 << slot))) { + if (!is_predicated || !(env->slot_cancelled & (1 << slot))) { size1u_t width = env->mem_log_stores[slot].width; target_ulong va = env->mem_log_stores[slot].va; uintptr_t ra = GETPC(); @@ -461,9 +439,12 @@ void HELPER(probe_noshuf_load)(CPUHexagonState *env, target_ulong va, } /* Called during packet commit when there are two scalar stores */ -void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int mmu_idx) +void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args) { - probe_store(env, 0, mmu_idx); + int mmu_idx = FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX); + bool is_predicated = + FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED); + probe_store(env, 0, mmu_idx, is_predicated); } void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx) @@ -510,15 +491,18 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx) void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask, int mmu_idx) { - bool has_st0 = (mask >> 0) & 1; - bool has_st1 = (mask >> 1) & 1; - bool has_hvx_stores = (mask >> 2) & 1; + bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0); + bool has_st1 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1); + bool has_hvx_stores = + FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES); + bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED); + bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED); if (has_st0) { - probe_store(env, 0, mmu_idx); + probe_store(env, 0, mmu_idx, s0_is_pred); } if (has_st1) { - probe_store(env, 1, mmu_idx); + probe_store(env, 1, mmu_idx, s1_is_pred); } if (has_hvx_stores) { HELPER(probe_hvx_stores)(env, mmu_idx); @@ -1193,7 +1177,7 @@ float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, { float32 neg_RsV; arch_fpop_start(env); - neg_RsV = float32_sub(float32_zero, RsV, &env->fp_status); + neg_RsV = float32_set_sign(RsV, float32_is_neg(RsV) ? 0 : 1); RxV = internal_fmafx(neg_RsV, RtV, RxV, 0, &env->fp_status); arch_fpop_end(env); return RxV; @@ -1468,12 +1452,6 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_t uiV) } } -void cancel_slot(CPUHexagonState *env, uint32_t slot) -{ - HEX_DEBUG_LOG("Slot %d cancelled\n", slot); - env->slot_cancelled |= (1 << slot); -} - /* These macros can be referenced in the generated helper functions */ #define warn(...) /* Nothing */ #define fatal(...) g_assert_not_reached(); diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h index 02347edee8..34b3a53975 100644 --- a/target/hexagon/op_helper.h +++ b/target/hexagon/op_helper.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +19,6 @@ #define HEXAGON_OP_HELPER_H /* Misc functions */ -void cancel_slot(CPUHexagonState *env, uint32_t slot); void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof, target_ulong addr); uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 93fd1b55e3..665476ab48 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +29,15 @@ #include "translate.h" #include "printinsn.h" +#include "analyze_funcs_generated.c.inc" + +typedef void (*AnalyzeInsn)(DisasContext *ctx); +static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = { +#define OPCODE(X) [X] = analyze_##X +#include "opcodes_def_generated.h.inc" +#undef OPCODE +}; + TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; TCGv hex_this_PC; @@ -47,8 +56,6 @@ TCGv hex_dczero_addr; TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; -TCGv hex_VRegs_updated; -TCGv hex_QRegs_updated; TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; @@ -239,7 +246,15 @@ static bool check_for_attrib(Packet *pkt, int attrib) static bool need_slot_cancelled(Packet *pkt) { - return check_for_attrib(pkt, A_CONDEXEC); + /* We only need slot_cancelled for conditional store instructions */ + for (int i = 0; i < pkt->num_insns; i++) { + uint16_t opcode = pkt->insn[i].opcode; + if (GET_ATTRIB(opcode, A_CONDEXEC) && + GET_ATTRIB(opcode, A_SCALAR_STORE)) { + return true; + } + } + return false; } static bool need_pred_written(Packet *pkt) @@ -265,6 +280,77 @@ static bool need_next_PC(DisasContext *ctx) return false; } +/* + * The opcode_analyze functions mark most of the writes in a packet + * However, there are some implicit writes marked as attributes + * of the applicable instructions. + */ +static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum) +{ + uint16_t opcode = ctx->insn->opcode; + if (GET_ATTRIB(opcode, attrib)) { + /* + * USR is used to set overflow and FP exceptions, + * so treat it as conditional + */ + bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) || + rnum == HEX_REG_USR; + + /* LC0/LC1 is conditionally written by endloop instructions */ + if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) && + (opcode == J2_endloop0 || + opcode == J2_endloop1 || + opcode == J2_endloop01)) { + is_predicated = true; + } + + ctx_log_reg_write(ctx, rnum, is_predicated); + } +} + +static void mark_implicit_reg_writes(DisasContext *ctx) +{ + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); + mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); +} + +static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum) +{ + if (GET_ATTRIB(ctx->insn->opcode, attrib)) { + ctx_log_pred_write(ctx, pnum); + } +} + +static void mark_implicit_pred_writes(DisasContext *ctx) +{ + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); +} + +static void analyze_packet(DisasContext *ctx) +{ + Packet *pkt = ctx->pkt; + ctx->need_pkt_has_store_s1 = false; + for (int i = 0; i < pkt->num_insns; i++) { + Insn *insn = &pkt->insn[i]; + ctx->insn = insn; + if (opcode_analyze[insn->opcode]) { + opcode_analyze[insn->opcode](ctx); + } + mark_implicit_reg_writes(ctx); + mark_implicit_pred_writes(ctx); + } +} + static void gen_start_packet(DisasContext *ctx) { Packet *pkt = ctx->pkt; @@ -275,6 +361,7 @@ static void gen_start_packet(DisasContext *ctx) ctx->next_PC = next_PC; ctx->reg_log_idx = 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); + bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx = 0; bitmap_zero(ctx->pregs_written, NUM_PREGS); ctx->future_vregs_idx = 0; @@ -283,14 +370,27 @@ static void gen_start_packet(DisasContext *ctx) bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); bitmap_zero(ctx->vregs_updated, NUM_VREGS); bitmap_zero(ctx->vregs_select, NUM_VREGS); + bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); + bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); ctx->qreg_log_idx = 0; for (i = 0; i < STORES_MAX; i++) { ctx->store_width[i] = 0; } - tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); ctx->s1_store_processed = false; ctx->pre_commit = true; + analyze_packet(ctx); + + if (ctx->need_pkt_has_store_s1) { + tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); + } + + /* + * pregs_written is used both in the analyze phase as well as the code + * gen phase, so clear it again. + */ + bitmap_zero(ctx->pregs_written, NUM_PREGS); + if (HEX_DEBUG) { /* Handy place to set a breakpoint before the packet executes */ gen_helper_debug_start_packet(cpu_env); @@ -313,9 +413,42 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(hex_pred_written, 0); } - if (pkt->pkt_has_hvx) { - tcg_gen_movi_tl(hex_VRegs_updated, 0); - tcg_gen_movi_tl(hex_QRegs_updated, 0); + /* Preload the predicated registers into hex_new_value[i] */ + if (!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { + int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); + while (i < TOTAL_PER_THREAD_REGS) { + tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]); + i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS, + i + 1); + } + } + + /* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */ + if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { + int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); + while (i < NUM_VREGS) { + const intptr_t VdV_off = + ctx_future_vreg_off(ctx, i, 1, true); + intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); + tcg_gen_gvec_mov(MO_64, VdV_off, + src_off, + sizeof(MMVector), + sizeof(MMVector)); + i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1); + } + } + if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { + int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); + while (i < NUM_VREGS) { + const intptr_t VdV_off = + ctx_tmp_vreg_off(ctx, i, 1, true); + intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); + tcg_gen_gvec_mov(MO_64, VdV_off, + src_off, + sizeof(MMVector), + sizeof(MMVector)); + i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1); + } } } @@ -336,66 +469,6 @@ bool is_gather_store_insn(DisasContext *ctx) return false; } -/* - * The LOG_*_WRITE macros mark most of the writes in a packet - * However, there are some implicit writes marked as attributes - * of the applicable instructions. - */ -static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum) -{ - uint16_t opcode = ctx->insn->opcode; - if (GET_ATTRIB(opcode, attrib)) { - /* - * USR is used to set overflow and FP exceptions, - * so treat it as conditional - */ - bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) || - rnum == HEX_REG_USR; - - /* LC0/LC1 is conditionally written by endloop instructions */ - if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) && - (opcode == J2_endloop0 || - opcode == J2_endloop1 || - opcode == J2_endloop01)) { - is_predicated = true; - } - - if (is_predicated && !is_preloaded(ctx, rnum)) { - tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); - } - - ctx_log_reg_write(ctx, rnum); - } -} - -static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum) -{ - if (GET_ATTRIB(ctx->insn->opcode, attrib)) { - ctx_log_pred_write(ctx, pnum); - } -} - -static void mark_implicit_reg_writes(DisasContext *ctx) -{ - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); - mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); -} - -static void mark_implicit_pred_writes(DisasContext *ctx) -{ - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); -} - static void mark_store_width(DisasContext *ctx) { uint16_t opcode = ctx->insn->opcode; @@ -423,9 +496,7 @@ static void mark_store_width(DisasContext *ctx) static void gen_insn(DisasContext *ctx) { if (ctx->insn->generate) { - mark_implicit_reg_writes(ctx); ctx->insn->generate(ctx); - mark_implicit_pred_writes(ctx); mark_store_width(ctx); } else { gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); @@ -646,65 +717,31 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i = 0; i < ctx->vreg_log_idx; i++) { * int rnum = ctx->vreg_log[i]; - * if (ctx->vreg_is_predicated[i]) { - * if (env->VRegs_updated & (1 << rnum)) { - * env->VRegs[rnum] = env->future_VRegs[rnum]; - * } - * } else { - * env->VRegs[rnum] = env->future_VRegs[rnum]; - * } + * env->VRegs[rnum] = env->future_VRegs[rnum]; * } */ for (i = 0; i < ctx->vreg_log_idx; i++) { int rnum = ctx->vreg_log[i]; - bool is_predicated = ctx->vreg_is_predicated[i]; intptr_t dstoff = offsetof(CPUHexagonState, VRegs[rnum]); intptr_t srcoff = ctx_future_vreg_off(ctx, rnum, 1, false); size_t size = sizeof(MMVector); - if (is_predicated) { - TCGv cmp = tcg_temp_new(); - TCGLabel *label_skip = gen_new_label(); - - tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum); - tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - gen_set_label(label_skip); - } else { - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - } + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); } /* * for (i = 0; i < ctx->qreg_log_idx; i++) { * int rnum = ctx->qreg_log[i]; - * if (ctx->qreg_is_predicated[i]) { - * if (env->QRegs_updated) & (1 << rnum)) { - * env->QRegs[rnum] = env->future_QRegs[rnum]; - * } - * } else { - * env->QRegs[rnum] = env->future_QRegs[rnum]; - * } + * env->QRegs[rnum] = env->future_QRegs[rnum]; * } */ for (i = 0; i < ctx->qreg_log_idx; i++) { int rnum = ctx->qreg_log[i]; - bool is_predicated = ctx->qreg_is_predicated[i]; intptr_t dstoff = offsetof(CPUHexagonState, QRegs[rnum]); intptr_t srcoff = offsetof(CPUHexagonState, future_QRegs[rnum]); size_t size = sizeof(MMQReg); - if (is_predicated) { - TCGv cmp = tcg_temp_new(); - TCGLabel *label_skip = gen_new_label(); - - tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum); - tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - gen_set_label(label_skip); - } else { - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); - } + tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); } if (pkt_has_hvx_store(ctx->pkt)) { @@ -775,13 +812,27 @@ static void gen_commit_packet(DisasContext *ctx) TCGv mask_tcgv; if (has_store_s0) { - mask |= (1 << 0); + mask = + FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 1); } if (has_store_s1) { - mask |= (1 << 1); + mask = + FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1); } if (has_hvx_store) { - mask |= (1 << 2); + mask = + FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, + HAS_HVX_STORES, 1); + } + if (has_store_s0 && slot_is_predicated(pkt, 0)) { + mask = + FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, + S0_IS_PRED, 1); + } + if (has_store_s1 && slot_is_predicated(pkt, 1)) { + mask = + FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, + S1_IS_PRED, 1); } mask_tcgv = tcg_constant_tl(mask); gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx); @@ -791,8 +842,15 @@ static void gen_commit_packet(DisasContext *ctx) * process_store_log will execute the slot 1 store first, * so we only have to probe the store in slot 0 */ - TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); - gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); + int args = 0; + args = + FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx); + if (slot_is_predicated(pkt, 0)) { + args = + FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1); + } + TCGv args_tcgv = tcg_constant_tl(args); + gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv); } process_store_log(ctx); @@ -1029,10 +1087,6 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, llsc_val), "llsc_val"); hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); - hex_VRegs_updated = tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, VRegs_updated), "VRegs_updated"); - hex_QRegs_updated = tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, QRegs_updated), "QRegs_updated"); for (i = 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); hex_store_addr[i] = tcg_global_mem_new(cpu_env, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d971f4f095..db832b0f88 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +38,7 @@ typedef struct DisasContext { int reg_log[REG_WRITES_MAX]; int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); + DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); int preg_log[PRED_WRITES_MAX]; int preg_log_idx; DECLARE_BITMAP(pregs_written, NUM_PREGS); @@ -48,52 +49,54 @@ typedef struct DisasContext { int tmp_vregs_idx; int tmp_vregs_num[VECTOR_TEMPS_MAX]; int vreg_log[NUM_VREGS]; - bool vreg_is_predicated[NUM_VREGS]; int vreg_log_idx; DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); DECLARE_BITMAP(vregs_updated, NUM_VREGS); DECLARE_BITMAP(vregs_select, NUM_VREGS); + DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); + DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); int qreg_log[NUM_QREGS]; - bool qreg_is_predicated[NUM_QREGS]; int qreg_log_idx; bool pre_commit; TCGCond branch_cond; target_ulong branch_dest; bool is_tight_loop; + bool need_pkt_has_store_s1; } DisasContext; -static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) -{ - if (test_bit(rnum, ctx->regs_written)) { - HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum); - } - ctx->reg_log[ctx->reg_log_idx] = rnum; - ctx->reg_log_idx++; - set_bit(rnum, ctx->regs_written); -} - -static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum) -{ - ctx_log_reg_write(ctx, rnum); - ctx_log_reg_write(ctx, rnum + 1); -} - static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) { - ctx->preg_log[ctx->preg_log_idx] = pnum; - ctx->preg_log_idx++; - set_bit(pnum, ctx->pregs_written); + if (!test_bit(pnum, ctx->pregs_written)) { + ctx->preg_log[ctx->preg_log_idx] = pnum; + ctx->preg_log_idx++; + set_bit(pnum, ctx->pregs_written); + } } -static inline bool is_preloaded(DisasContext *ctx, int num) +static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, + bool is_predicated) { - return test_bit(num, ctx->regs_written); + if (rnum == HEX_REG_P3_0_ALIASED) { + for (int i = 0; i < NUM_PREGS; i++) { + ctx_log_pred_write(ctx, i); + } + } else { + if (!test_bit(rnum, ctx->regs_written)) { + ctx->reg_log[ctx->reg_log_idx] = rnum; + ctx->reg_log_idx++; + set_bit(rnum, ctx->regs_written); + } + if (is_predicated) { + set_bit(rnum, ctx->predicated_regs); + } + } } -static inline bool is_vreg_preloaded(DisasContext *ctx, int num) +static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum, + bool is_predicated) { - return test_bit(num, ctx->vregs_updated) || - test_bit(num, ctx->vregs_updated_tmp); + ctx_log_reg_write(ctx, rnum, is_predicated); + ctx_log_reg_write(ctx, rnum + 1, is_predicated); } intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, @@ -106,17 +109,25 @@ static inline void ctx_log_vreg_write(DisasContext *ctx, bool is_predicated) { if (type != EXT_TMP) { - ctx->vreg_log[ctx->vreg_log_idx] = rnum; - ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated; - ctx->vreg_log_idx++; + if (!test_bit(rnum, ctx->vregs_updated)) { + ctx->vreg_log[ctx->vreg_log_idx] = rnum; + ctx->vreg_log_idx++; + set_bit(rnum, ctx->vregs_updated); + } set_bit(rnum, ctx->vregs_updated); + if (is_predicated) { + set_bit(rnum, ctx->predicated_future_vregs); + } } if (type == EXT_NEW) { set_bit(rnum, ctx->vregs_select); } if (type == EXT_TMP) { set_bit(rnum, ctx->vregs_updated_tmp); + if (is_predicated) { + set_bit(rnum, ctx->predicated_tmp_vregs); + } } } @@ -129,10 +140,9 @@ static inline void ctx_log_vreg_write_pair(DisasContext *ctx, } static inline void ctx_log_qreg_write(DisasContext *ctx, - int rnum, bool is_predicated) + int rnum) { ctx->qreg_log[ctx->qreg_log_idx] = rnum; - ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated; ctx->qreg_log_idx++; } @@ -153,12 +163,20 @@ extern TCGv hex_dczero_addr; extern TCGv hex_llsc_addr; extern TCGv hex_llsc_val; extern TCGv_i64 hex_llsc_val_i64; -extern TCGv hex_VRegs_updated; -extern TCGv hex_QRegs_updated; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; bool is_gather_store_insn(DisasContext *ctx); void process_store(DisasContext *ctx, int slot_num); + +FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2) +FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1) + +FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 0, 1) +FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1) +FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1) +FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1) +FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1) + #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index a48a2701ae..c2791ae5f2 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -29,6 +29,5 @@ # define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif #define TARGET_PAGE_BITS 12 -#define NB_MMU_MODES 5 #endif diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 729c37b2ca..48a514384f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cb4fd1fd62..6a3154ebc6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -135,8 +135,6 @@ #define tcg_gen_extract_reg tcg_gen_extract_i64 #define tcg_gen_sextract_reg tcg_gen_sextract_i64 #define tcg_gen_extract2_reg tcg_gen_extract2_i64 -#define tcg_const_reg tcg_const_i64 -#define tcg_const_local_reg tcg_const_local_i64 #define tcg_constant_reg tcg_constant_i64 #define tcg_gen_movcond_reg tcg_gen_movcond_i64 #define tcg_gen_add2_reg tcg_gen_add2_i64 @@ -228,8 +226,6 @@ #define tcg_gen_extract_reg tcg_gen_extract_i32 #define tcg_gen_sextract_reg tcg_gen_sextract_i32 #define tcg_gen_extract2_reg tcg_gen_extract2_i32 -#define tcg_const_reg tcg_const_i32 -#define tcg_const_local_reg tcg_const_local_i32 #define tcg_constant_reg tcg_constant_i32 #define tcg_gen_movcond_reg tcg_gen_movcond_i32 #define tcg_gen_add2_reg tcg_gen_add2_i32 @@ -574,7 +570,9 @@ static TCGv_i32 load_frw_i32(unsigned rt) static TCGv_i32 load_frw0_i32(unsigned rt) { if (rt == 0) { - return tcg_const_i32(0); + TCGv_i32 ret = tcg_temp_new_i32(); + tcg_gen_movi_i32(ret, 0); + return ret; } else { return load_frw_i32(rt); } @@ -582,15 +580,15 @@ static TCGv_i32 load_frw0_i32(unsigned rt) static TCGv_i64 load_frw0_i64(unsigned rt) { + TCGv_i64 ret = tcg_temp_new_i64(); if (rt == 0) { - return tcg_const_i64(0); + tcg_gen_movi_i64(ret, 0); } else { - TCGv_i64 ret = tcg_temp_new_i64(); tcg_gen_ld32u_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt & 31]) + (rt & 32 ? LO_OFS : HI_OFS)); - return ret; } + return ret; } static void save_frw_i32(unsigned rt, TCGv_i32 val) @@ -613,7 +611,9 @@ static TCGv_i64 load_frd(unsigned rt) static TCGv_i64 load_frd0(unsigned rt) { if (rt == 0) { - return tcg_const_i64(0); + TCGv_i64 ret = tcg_temp_new_i64(); + tcg_gen_movi_i64(ret, 0); + return ret; } else { return load_frd(rt); } @@ -3330,7 +3330,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, /* Convert big-endian bit numbering in SAR to left-shift. */ tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); - mask = tcg_const_reg(msb + (msb - 1)); + mask = tcg_temp_new(); + tcg_gen_movi_reg(mask, msb + (msb - 1)); tcg_gen_and_reg(tmp, val, mask); if (rs) { tcg_gen_shl_reg(mask, mask, shift); @@ -3547,12 +3548,16 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a) { + uint64_t ret; + + if (TARGET_REGISTER_BITS == 64) { + ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */ + } else { + ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ + } + nullify_over(ctx); -#if TARGET_REGISTER_BITS == 64 - save_frd(0, tcg_const_i64(0x13080000000000ULL)); /* PA8700 (PCX-W2) */ -#else - save_frd(0, tcg_const_i64(0x0f080000000000ULL)); /* PA7300LC (PCX-L2) */ -#endif + save_frd(0, tcg_constant_i64(ret)); return nullify_end(ctx); } diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index abad52af20..911b4cd51b 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -23,6 +23,5 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #define TARGET_PAGE_BITS 12 -#define NB_MMU_MODES 5 #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cab1e2a957..6576287e5b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -29,6 +29,7 @@ #include "kvm/kvm_i386.h" #include "sev.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qapi/qapi-visit-machine.h" #include "qapi/qmp/qerror.h" #include "standard-headers/asm-x86/kvm_para.h" diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 786971284a..ebb000df6a 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "include/gdbstub/helpers.h" #ifdef TARGET_X86_64 static const int gpr_map[16] = { diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c index 10f8aba86e..92ecb7254b 100644 --- a/target/i386/host-cpu.c +++ b/target/i386/host-cpu.c @@ -11,6 +11,7 @@ #include "cpu.h" #include "host-cpu.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "sysemu/sysemu.h" /* Note: Only safe for use on x86(-64) hosts */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 1aef54f87e..de531842f6 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4991,6 +4991,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) kvm_rate_limit_on_bus_lock(); } +#ifdef CONFIG_XEN_EMU /* * If the callback is asserted as a GSI (or PCI INTx) then check if * vcpu_info->evtchn_upcall_pending has been cleared, and deassert @@ -5001,6 +5002,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) if (x86_cpu->env.xen_callback_asserted) { kvm_xen_maybe_deassert_callback(cpu); } +#endif /* We need to protect the apic state against concurrent accesses from * different threads in case the userspace irqchip is used. */ diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index bad3131d08..d7c7eb8d9c 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "qemu/error-report.h" #include "hw/xen/xen.h" #include "sysemu/kvm_int.h" #include "sysemu/kvm_xen.h" @@ -1406,6 +1407,11 @@ int kvm_xen_soft_reset(void) return err; } + err = xen_gnttab_reset(); + if (err) { + return err; + } + err = xen_xenstore_reset(); if (err) { return err; diff --git a/target/i386/sev.c b/target/i386/sev.c index 0ec970496e..859e06f6ad 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -23,6 +23,7 @@ #include "qemu/base64.h" #include "qemu/module.h" #include "qemu/uuid.h" +#include "qemu/error-report.h" #include "crypto/hash.h" #include "sysemu/kvm.h" #include "sev.h" diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index fa422ebd0b..9dfad2f7bc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -884,7 +884,7 @@ static void gen_compute_eflags(DisasContext *s) live = cc_op_live[s->cc_op] & ~USES_CC_SRCT; dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2); if (dead) { - zero = tcg_const_tl(0); + zero = tcg_constant_tl(0); if (dead & USES_CC_DST) { dst = zero; } @@ -1412,7 +1412,7 @@ static void gen_helper_fp_arith_ST0_FT0(int op) /* NOTE the exception in "r" op ordering */ static void gen_helper_fp_arith_STN_ST0(int op, int opreg) { - TCGv_i32 tmp = tcg_const_i32(opreg); + TCGv_i32 tmp = tcg_constant_i32(opreg); switch (op) { case 0: gen_helper_fadd_STN_ST0(cpu_env, tmp); @@ -1439,7 +1439,7 @@ static void gen_exception(DisasContext *s, int trapno) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno)); s->base.is_jmp = DISAS_NORETURN; } @@ -1633,7 +1633,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result, /* Store the results into the CC variables. If we know that the variable must be dead, store unconditionally. Otherwise we'll need to not disrupt the current contents. */ - z_tl = tcg_const_tl(0); + z_tl = tcg_constant_tl(0); if (cc_op_live[s->cc_op] & USES_CC_DST) { tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl, result, cpu_cc_dst); @@ -1657,7 +1657,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result, } /* Conditionally store the CC_OP value. */ - z32 = tcg_const_i32(0); + z32 = tcg_constant_i32(0); s32 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(s32, count); tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop); @@ -1813,7 +1813,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right) is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live. Otherwise reuse CC_OP_ADCOX which have the C and O flags split out exactly as we computed above. */ - t0 = tcg_const_i32(0); + t0 = tcg_constant_i32(0); t1 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t1, s->T1); tcg_gen_movi_i32(s->tmp2_i32, CC_OP_ADCOX); @@ -2497,7 +2497,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b, cc.reg = t0; } if (!cc.use_reg2) { - cc.reg2 = tcg_const_tl(cc.imm); + cc.reg2 = tcg_constant_tl(cc.imm); } tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2, @@ -2525,7 +2525,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) { if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32); + gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i32); /* abort translation because the addseg value may change or because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware @@ -4344,7 +4344,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_v_reg(s, ot, s->T1, reg); if (shift) { - TCGv imm = tcg_const_tl(x86_ldub_code(env, s)); + TCGv imm = tcg_constant_tl(x86_ldub_code(env, s)); gen_shiftd_rm_T1(s, ot, opreg, op, imm); } else { gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); @@ -4503,7 +4503,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; case 0x0c: /* fldenv mem */ gen_helper_fldenv(cpu_env, s->A0, - tcg_const_i32(dflag - 1)); + tcg_constant_i32(dflag - 1)); update_fip = update_fdp = false; break; case 0x0d: /* fldcw mem */ @@ -4514,7 +4514,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; case 0x0e: /* fnstenv mem */ gen_helper_fstenv(cpu_env, s->A0, - tcg_const_i32(dflag - 1)); + tcg_constant_i32(dflag - 1)); update_fip = update_fdp = false; break; case 0x0f: /* fnstcw mem */ @@ -4532,12 +4532,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; case 0x2c: /* frstor mem */ gen_helper_frstor(cpu_env, s->A0, - tcg_const_i32(dflag - 1)); + tcg_constant_i32(dflag - 1)); update_fip = update_fdp = false; break; case 0x2e: /* fnsave mem */ gen_helper_fsave(cpu_env, s->A0, - tcg_const_i32(dflag - 1)); + tcg_constant_i32(dflag - 1)); update_fip = update_fdp = false; break; case 0x2f: /* fnstsw mem */ @@ -4587,12 +4587,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x08: /* fld sti */ gen_helper_fpush(cpu_env); gen_helper_fmov_ST0_STN(cpu_env, - tcg_const_i32((opreg + 1) & 7)); + tcg_constant_i32((opreg + 1) & 7)); break; case 0x09: /* fxchg sti */ case 0x29: /* fxchg4 sti, undocumented op */ case 0x39: /* fxchg7 sti, undocumented op */ - gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opreg)); break; case 0x0a: /* grp d9/2 */ switch (rm) { @@ -4732,27 +4732,27 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } } else { gen_helper_fmov_FT0_STN(cpu_env, - tcg_const_i32(opreg)); + tcg_constant_i32(opreg)); gen_helper_fp_arith_ST0_FT0(op1); } } break; case 0x02: /* fcom */ case 0x22: /* fcom2, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fcom_ST0_FT0(cpu_env); break; case 0x03: /* fcomp */ case 0x23: /* fcomp3, undocumented op */ case 0x32: /* fcomp5, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fcom_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); break; case 0x15: /* da/5 */ switch (rm) { case 1: /* fucompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1)); gen_helper_fucom_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env); @@ -4786,7 +4786,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fucomi_ST0_FT0(cpu_env); set_cc_op(s, CC_OP_EFLAGS); break; @@ -4795,36 +4795,36 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fcomi_ST0_FT0(cpu_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x28: /* ffree sti */ - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg)); break; case 0x2a: /* fst sti */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg)); break; case 0x2b: /* fstp sti */ case 0x0b: /* fstp1 sti, undocumented op */ case 0x3a: /* fstp8 sti, undocumented op */ case 0x3b: /* fstp9 sti, undocumented op */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg)); gen_helper_fpop(cpu_env); break; case 0x2c: /* fucom st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fucom_ST0_FT0(cpu_env); break; case 0x2d: /* fucomp st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fucom_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); break; case 0x33: /* de/3 */ switch (rm) { case 1: /* fcompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1)); gen_helper_fcom_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env); @@ -4834,7 +4834,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } break; case 0x38: /* ffreep sti, undocumented op */ - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fpop(cpu_env); break; case 0x3c: /* df/4 */ @@ -4853,7 +4853,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fucomi_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); set_cc_op(s, CC_OP_EFLAGS); @@ -4863,7 +4863,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg)); gen_helper_fcomi_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); set_cc_op(s, CC_OP_EFLAGS); @@ -4886,7 +4886,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); l1 = gen_new_label(); gen_jcc1_noeob(s, op1, l1); - gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fmov_ST0_STN(cpu_env, + tcg_constant_i32(opreg)); gen_set_label(l1); } break; @@ -5092,8 +5093,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (PE(s) && !VM86(s)) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), - tcg_const_i32(val)); + gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1), + tcg_constant_i32(val)); } else { gen_stack_A0(s); /* pop offset */ @@ -5120,7 +5121,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!check_vm86_iopl(s)) { break; } - gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); + gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1)); } else { gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1), eip_next_i32(s)); @@ -5509,7 +5510,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (val == 0) { gen_exception(s, EXCP00_DIVZ); } else { - gen_helper_aam(cpu_env, tcg_const_i32(val)); + gen_helper_aam(cpu_env, tcg_constant_i32(val)); set_cc_op(s, CC_OP_LOGICB); } break; @@ -5517,7 +5518,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s)) goto illegal_op; val = x86_ldub_code(env, s); - gen_helper_aad(cpu_env, tcg_const_i32(val)); + gen_helper_aad(cpu_env, tcg_constant_i32(val)); set_cc_op(s, CC_OP_LOGICB); break; /************************/ @@ -5698,7 +5699,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s)) { gen_exception_gpf(s); } else { - gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); + gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1)); s->base.is_jmp = DISAS_EOB_ONLY; } break; @@ -5717,7 +5718,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s)) { gen_exception_gpf(s); } else { - gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); + gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1)); /* condition codes are modified only in long mode */ if (LMA(s)) { set_cc_op(s, CC_OP_EFLAGS); @@ -5923,7 +5924,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), + gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1), cur_insn_len_i32(s)); tcg_gen_exit_tb(NULL, 0); s->base.is_jmp = DISAS_NORETURN; @@ -5947,7 +5948,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1)); + gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1)); break; case 0xdb: /* VMSAVE */ @@ -5959,7 +5960,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1)); + gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1)); break; case 0xdc: /* STGI */ diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 3d0c0b375f..52af81683c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -12,7 +12,7 @@ #include "cpu.h" #include "exec/address-spaces.h" #include "exec/ioport.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/accel.h" #include "sysemu/whpx.h" #include "sysemu/cpus.h" diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index c15df35ad6..8710e37567 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -11,6 +11,7 @@ * See the COPYING file in the top-level directory. */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "cpu.h" #include "hw/i386/apic_internal.h" #include "hw/i386/apic-msidef.h" diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 414d8fff46..1265dc7cb5 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,5 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 48 #define TARGET_PAGE_BITS 14 -#define NB_MMU_MODES 5 #endif diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index a4d1e28e36..fa3e034d15 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -10,6 +10,7 @@ #include "cpu.h" #include "internals.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" uint64_t read_fcc(CPULoongArchState *env) { diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 44a8d193f0..39dcbcece8 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,6 +17,5 @@ #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define NB_MMU_MODES 2 #endif diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index eb2d030e14..1e5f033a12 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 4621cf2402..3b3a6ea8bd 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" +#include "gdbstub/helpers.h" #include "fpu/softfloat.h" #include "qemu/qemu-print.h" diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 87b1314925..88ad9ba814 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -20,7 +20,8 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" +#include "gdbstub/helpers.h" #include "semihosting/syscalls.h" #include "semihosting/softmmu-uaccess.h" #include "hw/boards.h" diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3055d2d246..422f4652f1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -264,10 +264,7 @@ static void gen_jmp(DisasContext *s, TCGv dest) static void gen_raise_exception(int nr) { - TCGv_i32 tmp; - - tmp = tcg_const_i32(nr); - gen_helper_raise_exception(cpu_env, tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr)); } static void gen_raise_exception_format2(DisasContext *s, int nr, @@ -471,7 +468,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) if ((ext & 0x80) == 0) { /* base not suppressed */ if (IS_NULL_QREG(base)) { - base = tcg_const_i32(offset + bd); + base = tcg_constant_i32(offset + bd); bd = 0; } if (!IS_NULL_QREG(add)) { @@ -487,7 +484,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) add = tmp; } } else { - add = tcg_const_i32(bd); + add = tcg_constant_i32(bd); } if ((ext & 3) != 0) { /* memory indirect */ @@ -623,8 +620,7 @@ static void gen_flush_flags(DisasContext *s) break; default: - t0 = tcg_const_i32(s->cc_op); - gen_helper_flush_flags(cpu_env, t0); + gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op)); s->cc_op_synced = 1; break; } @@ -785,14 +781,14 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s, switch (reg0) { case 0: /* Absolute short. */ offset = (int16_t)read_im16(env, s); - return tcg_const_i32(offset); + return tcg_constant_i32(offset); case 1: /* Absolute long. */ offset = read_im32(env, s); - return tcg_const_i32(offset); + return tcg_constant_i32(offset); case 2: /* pc displacement */ offset = s->pc; offset += (int16_t)read_im16(env, s); - return tcg_const_i32(offset); + return tcg_constant_i32(offset); case 3: /* pc index+displacement. */ return gen_lea_indexed(env, s, NULL_QREG); case 4: /* Immediate. */ @@ -920,7 +916,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, default: g_assert_not_reached(); } - return tcg_const_i32(offset); + return tcg_constant_i32(offset); default: return NULL_QREG; } @@ -1167,23 +1163,23 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode, } switch (opsize) { case OS_BYTE: - tmp = tcg_const_i32((int8_t)read_im8(env, s)); + tmp = tcg_constant_i32((int8_t)read_im8(env, s)); gen_helper_exts32(cpu_env, fp, tmp); break; case OS_WORD: - tmp = tcg_const_i32((int16_t)read_im16(env, s)); + tmp = tcg_constant_i32((int16_t)read_im16(env, s)); gen_helper_exts32(cpu_env, fp, tmp); break; case OS_LONG: - tmp = tcg_const_i32(read_im32(env, s)); + tmp = tcg_constant_i32(read_im32(env, s)); gen_helper_exts32(cpu_env, fp, tmp); break; case OS_SINGLE: - tmp = tcg_const_i32(read_im32(env, s)); + tmp = tcg_constant_i32(read_im32(env, s)); gen_helper_extf32(cpu_env, fp, tmp); break; case OS_DOUBLE: - t64 = tcg_const_i64(read_im64(env, s)); + t64 = tcg_constant_i64(read_im64(env, s)); gen_helper_extf64(cpu_env, fp, t64); break; case OS_EXTENDED: @@ -1191,9 +1187,9 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode, gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); break; } - tmp = tcg_const_i32(read_im32(env, s) >> 16); + tmp = tcg_constant_i32(read_im32(env, s) >> 16); tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper)); - t64 = tcg_const_i64(read_im64(env, s)); + t64 = tcg_constant_i64(read_im64(env, s)); tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower)); break; case OS_PACKED: @@ -1253,7 +1249,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) goto done; case 10: /* PL */ case 11: /* MI */ - c->v2 = tcg_const_i32(0); + c->v2 = tcg_constant_i32(0); c->v1 = tmp = tcg_temp_new(); tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); gen_ext(tmp, tmp, op - CC_OP_CMPB, 1); @@ -1269,7 +1265,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) } } - c->v2 = tcg_const_i32(0); + c->v2 = tcg_constant_i32(0); switch (cond) { case 0: /* T */ @@ -1631,8 +1627,8 @@ static void bcd_add(TCGv dest, TCGv src) * = result with some possible exceeding 0x6 */ - t0 = tcg_const_i32(0x066); - tcg_gen_add_i32(t0, t0, src); + t0 = tcg_temp_new(); + tcg_gen_addi_i32(t0, src, 0x066); t1 = tcg_temp_new(); tcg_gen_add_i32(t1, t0, dest); @@ -1818,7 +1814,8 @@ DISAS_INSN(nbcd) SRC_EA(env, src, OS_BYTE, 0, &addr); - dest = tcg_const_i32(0); + dest = tcg_temp_new(); + tcg_gen_movi_i32(dest, 0); bcd_sub(dest, src); DEST_EA(env, insn, OS_BYTE, dest, &addr); @@ -1896,8 +1893,8 @@ DISAS_INSN(bitop_reg) else tcg_gen_andi_i32(src2, DREG(insn, 9), 31); - tmp = tcg_const_i32(1); - tcg_gen_shl_i32(tmp, tmp, src2); + tmp = tcg_temp_new(); + tcg_gen_shl_i32(tmp, tcg_constant_i32(1), src2); tcg_gen_and_i32(QREG_CC_Z, src1, tmp); @@ -1999,7 +1996,7 @@ DISAS_INSN(movem) addr = tcg_temp_new(); tcg_gen_mov_i32(addr, tmp); - incr = tcg_const_i32(opsize_bytes(opsize)); + incr = tcg_constant_i32(opsize_bytes(opsize)); if (is_load) { /* memory to register */ @@ -2235,13 +2232,13 @@ DISAS_INSN(arith_im) opsize = insn_opsize(insn); switch (opsize) { case OS_BYTE: - im = tcg_const_i32((int8_t)read_im8(env, s)); + im = tcg_constant_i32((int8_t)read_im8(env, s)); break; case OS_WORD: - im = tcg_const_i32((int16_t)read_im16(env, s)); + im = tcg_constant_i32((int16_t)read_im16(env, s)); break; case OS_LONG: - im = tcg_const_i32(read_im32(env, s)); + im = tcg_constant_i32(read_im32(env, s)); break; default: g_assert_not_reached(); @@ -2393,7 +2390,6 @@ DISAS_INSN(cas2w) { uint16_t ext1, ext2; TCGv addr1, addr2; - TCGv regs; /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ @@ -2425,13 +2421,13 @@ DISAS_INSN(cas2w) * Dc2 = (R2) */ - regs = tcg_const_i32(REG(ext2, 6) | - (REG(ext1, 6) << 3) | - (REG(ext2, 0) << 6) | - (REG(ext1, 0) << 9)); if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { + TCGv regs = tcg_constant_i32(REG(ext2, 6) | + (REG(ext1, 6) << 3) | + (REG(ext2, 0) << 6) | + (REG(ext1, 0) << 9)); gen_helper_cas2w(cpu_env, regs, addr1, addr2); } @@ -2475,10 +2471,10 @@ DISAS_INSN(cas2l) * Dc2 = (R2) */ - regs = tcg_const_i32(REG(ext2, 6) | - (REG(ext1, 6) << 3) | - (REG(ext2, 0) << 6) | - (REG(ext1, 0) << 9)); + regs = tcg_constant_i32(REG(ext2, 6) | + (REG(ext1, 6) << 3) | + (REG(ext2, 0) << 6) | + (REG(ext1, 0) << 9)); if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2); } else { @@ -2552,7 +2548,7 @@ DISAS_INSN(negx) * (X, N) = -(src + X); */ - z = tcg_const_i32(0); + z = tcg_constant_i32(0); tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X); gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); @@ -2597,8 +2593,7 @@ DISAS_INSN(clr) int opsize; TCGv zero; - zero = tcg_const_i32(0); - + zero = tcg_constant_i32(0); opsize = insn_opsize(insn); DEST_EA(env, insn, opsize, zero, NULL); gen_logic_cc(s, zero, opsize); @@ -2934,7 +2929,7 @@ DISAS_INSN(jump) } if ((insn & 0x40) == 0) { /* jsr */ - gen_push(s, tcg_const_i32(s->pc)); + gen_push(s, tcg_constant_i32(s->pc)); } gen_jmp(s, tmp); } @@ -2959,7 +2954,7 @@ DISAS_INSN(addsubq) if (imm == 0) { imm = 8; } - val = tcg_const_i32(imm); + val = tcg_constant_i32(imm); dest = tcg_temp_new(); tcg_gen_mov_i32(dest, src); if ((insn & 0x38) == 0x08) { @@ -3003,7 +2998,7 @@ DISAS_INSN(branch) } if (op == 1) { /* bsr */ - gen_push(s, tcg_const_i32(s->pc)); + gen_push(s, tcg_constant_i32(s->pc)); } if (op > 1) { /* Bcc */ @@ -3076,7 +3071,7 @@ DISAS_INSN(suba) static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) { - TCGv tmp; + TCGv tmp, zero; gen_flush_flags(s); /* compute old Z */ @@ -3085,14 +3080,15 @@ static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) * (X, N) = dest - (src + X); */ - tmp = tcg_const_i32(0); - tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp); - tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X); + zero = tcg_constant_i32(0); + tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, zero, QREG_CC_X, zero); + tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, zero, QREG_CC_N, QREG_CC_X); gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); /* Compute signed-overflow for subtract. */ + tmp = tcg_temp_new(); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); tcg_gen_xor_i32(tmp, dest, src); tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp); @@ -3151,9 +3147,10 @@ DISAS_INSN(mov3q) int val; val = (insn >> 9) & 7; - if (val == 0) + if (val == 0) { val = -1; - src = tcg_const_i32(val); + } + src = tcg_constant_i32(val); gen_logic_cc(s, src, OS_LONG); DEST_EA(env, insn, OS_LONG, src, NULL); } @@ -3279,7 +3276,7 @@ DISAS_INSN(adda) static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize) { - TCGv tmp; + TCGv tmp, zero; gen_flush_flags(s); /* compute old Z */ @@ -3288,13 +3285,14 @@ static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize) * (X, N) = src + dest + X; */ - tmp = tcg_const_i32(0); - tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp); - tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp); + zero = tcg_constant_i32(0); + tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, zero, dest, zero); + tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, zero); gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); /* Compute signed-overflow for addition. */ + tmp = tcg_temp_new(); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); tcg_gen_xor_i32(tmp, dest, src); tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp); @@ -3430,7 +3428,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); /* Note that C=0 if shift count is 0, and we get that for free. */ } else { - TCGv zero = tcg_const_i32(0); + TCGv zero = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(QREG_CC_N, t64); tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits); tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, @@ -3452,7 +3450,7 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) * V = ((s ^ t) & (-1 << (bits - 1))) != 0 */ if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) { - TCGv_i64 tt = tcg_const_i64(32); + TCGv_i64 tt = tcg_constant_i64(32); /* if shift is greater than 32, use 32 */ tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64); /* Sign extend the input to 64 bits; re-do the shift. */ @@ -3633,7 +3631,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size) { TCGv X, shl, shr, shx, sz, zero; - sz = tcg_const_i32(size); + sz = tcg_constant_i32(size); shr = tcg_temp_new(); shl = tcg_temp_new(); @@ -3644,7 +3642,7 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size) tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */ tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */ /* shx = shx < 0 ? size : shx; */ - zero = tcg_const_i32(0); + zero = tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); } else { tcg_gen_mov_i32(shr, shift); /* shr = shift */ @@ -3723,7 +3721,7 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int left) /* if shift == 0, register and X are not affected */ - zero = tcg_const_i32(0); + zero = tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X); tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo); @@ -3741,7 +3739,7 @@ DISAS_INSN(rotate_im) tmp = 8; } - shift = tcg_const_i32(tmp); + shift = tcg_constant_i32(tmp); if (insn & 8) { rotate(DREG(insn, 0), shift, left, 32); } else { @@ -3766,7 +3764,7 @@ DISAS_INSN(rotate8_im) tmp = 8; } - shift = tcg_const_i32(tmp); + shift = tcg_constant_i32(tmp); if (insn & 8) { rotate(reg, shift, left, 8); } else { @@ -3790,7 +3788,7 @@ DISAS_INSN(rotate16_im) tmp = 8; } - shift = tcg_const_i32(tmp); + shift = tcg_constant_i32(tmp); if (insn & 8) { rotate(reg, shift, left, 16); } else { @@ -3905,7 +3903,7 @@ DISAS_INSN(rotate_mem) SRC_EA(env, src, OS_WORD, 0, &addr); - shift = tcg_const_i32(1); + shift = tcg_constant_i32(1); if (insn & 0x0200) { rotate(src, shift, left, 16); } else { @@ -3999,12 +3997,12 @@ DISAS_INSN(bfext_mem) if (ext & 0x20) { len = DREG(ext, 0); } else { - len = tcg_const_i32(extract32(ext, 0, 5)); + len = tcg_constant_i32(extract32(ext, 0, 5)); } if (ext & 0x800) { ofs = DREG(ext, 6); } else { - ofs = tcg_const_i32(extract32(ext, 6, 5)); + ofs = tcg_constant_i32(extract32(ext, 6, 5)); } if (is_sign) { @@ -4024,14 +4022,8 @@ DISAS_INSN(bfop_reg) TCGv src = DREG(insn, 0); int len = ((extract32(ext, 0, 5) - 1) & 31) + 1; int ofs = extract32(ext, 6, 5); /* big bit-endian */ - TCGv mask, tofs, tlen; - - tofs = NULL; - tlen = NULL; - if ((insn & 0x0f00) == 0x0d00) { /* bfffo */ - tofs = tcg_temp_new(); - tlen = tcg_temp_new(); - } + TCGv mask, tofs = NULL, tlen = NULL; + bool is_bfffo = (insn & 0x0f00) == 0x0d00; if ((ext & 0x820) == 0) { /* Immediate width and offset. */ @@ -4042,45 +4034,49 @@ DISAS_INSN(bfop_reg) tcg_gen_rotli_i32(QREG_CC_N, src, ofs); } tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski); - mask = tcg_const_i32(ror32(maski, ofs)); - if (tofs) { - tcg_gen_movi_i32(tofs, ofs); - tcg_gen_movi_i32(tlen, len); + + mask = tcg_constant_i32(ror32(maski, ofs)); + if (is_bfffo) { + tofs = tcg_constant_i32(ofs); + tlen = tcg_constant_i32(len); } } else { TCGv tmp = tcg_temp_new(); + + mask = tcg_temp_new(); if (ext & 0x20) { /* Variable width */ tcg_gen_subi_i32(tmp, DREG(ext, 0), 1); tcg_gen_andi_i32(tmp, tmp, 31); - mask = tcg_const_i32(0x7fffffffu); - tcg_gen_shr_i32(mask, mask, tmp); - if (tlen) { + tcg_gen_shr_i32(mask, tcg_constant_i32(0x7fffffffu), tmp); + if (is_bfffo) { + tlen = tcg_temp_new(); tcg_gen_addi_i32(tlen, tmp, 1); } } else { /* Immediate width */ - mask = tcg_const_i32(0x7fffffffu >> (len - 1)); - if (tlen) { - tcg_gen_movi_i32(tlen, len); + tcg_gen_movi_i32(mask, 0x7fffffffu >> (len - 1)); + if (is_bfffo) { + tlen = tcg_constant_i32(len); } } + if (ext & 0x800) { /* Variable offset */ tcg_gen_andi_i32(tmp, DREG(ext, 6), 31); tcg_gen_rotl_i32(QREG_CC_N, src, tmp); tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); tcg_gen_rotr_i32(mask, mask, tmp); - if (tofs) { - tcg_gen_mov_i32(tofs, tmp); + if (is_bfffo) { + tofs = tmp; } } else { /* Immediate offset (and variable width) */ tcg_gen_rotli_i32(QREG_CC_N, src, ofs); tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask); tcg_gen_rotri_i32(mask, mask, ofs); - if (tofs) { - tcg_gen_movi_i32(tofs, ofs); + if (is_bfffo) { + tofs = tcg_constant_i32(ofs); } } } @@ -4122,12 +4118,12 @@ DISAS_INSN(bfop_mem) if (ext & 0x20) { len = DREG(ext, 0); } else { - len = tcg_const_i32(extract32(ext, 0, 5)); + len = tcg_constant_i32(extract32(ext, 0, 5)); } if (ext & 0x800) { ofs = DREG(ext, 6); } else { - ofs = tcg_const_i32(extract32(ext, 6, 5)); + ofs = tcg_constant_i32(extract32(ext, 6, 5)); } switch (insn & 0x0f00) { @@ -4239,12 +4235,12 @@ DISAS_INSN(bfins_mem) if (ext & 0x20) { len = DREG(ext, 0); } else { - len = tcg_const_i32(extract32(ext, 0, 5)); + len = tcg_constant_i32(extract32(ext, 0, 5)); } if (ext & 0x800) { ofs = DREG(ext, 6); } else { - ofs = tcg_const_i32(extract32(ext, 6, 5)); + ofs = tcg_constant_i32(extract32(ext, 6, 5)); } gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len); @@ -4377,7 +4373,7 @@ DISAS_INSN(move16_mem) TCGv reg, addr; reg = AREG(insn, 0); - addr = tcg_const_i32(read_im32(env, s)); + addr = tcg_constant_i32(read_im32(env, s)); if ((insn >> 3) & 1) { /* MOVE16 (xxx).L, (Ay) */ @@ -4567,14 +4563,14 @@ DISAS_INSN(cf_movec) } else { reg = DREG(ext, 12); } - gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg); + gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg); gen_exit_tb(s); } DISAS_INSN(m68k_movec) { uint16_t ext; - TCGv reg; + TCGv reg, creg; if (IS_USER(s)) { gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); @@ -4588,10 +4584,11 @@ DISAS_INSN(m68k_movec) } else { reg = DREG(ext, 12); } + creg = tcg_constant_i32(ext & 0xfff); if (insn & 1) { - gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg); + gen_helper_m68k_movec_to(cpu_env, creg, reg); } else { - gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff)); + gen_helper_m68k_movec_from(reg, cpu_env, creg); } gen_exit_tb(s); } @@ -4642,7 +4639,7 @@ DISAS_INSN(pflush) return; } - opmode = tcg_const_i32((insn >> 3) & 3); + opmode = tcg_constant_i32((insn >> 3) & 3); gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); } @@ -4654,7 +4651,7 @@ DISAS_INSN(ptest) gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } - is_read = tcg_const_i32((insn >> 5) & 1); + is_read = tcg_constant_i32((insn >> 5) & 1); gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); } #endif @@ -4824,7 +4821,7 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s, gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); return; } - tmp = tcg_const_i32(read_im32(env, s)); + tmp = tcg_constant_i32(read_im32(env, s)); gen_store_fcr(s, tmp, mask); return; } @@ -4961,7 +4958,7 @@ DISAS_INSN(fpu) case 2: if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) { /* fmovecr */ - TCGv rom_offset = tcg_const_i32(opmode); + TCGv rom_offset = tcg_constant_i32(opmode); cpu_dest = gen_fp_ptr(REG(ext, 7)); gen_helper_fconst(cpu_env, cpu_dest, rom_offset); return; @@ -5185,7 +5182,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond) { TCGv fpsr; - c->v2 = tcg_const_i32(0); + c->v2 = tcg_constant_i32(0); /* TODO: Raise BSUN exception. */ fpsr = tcg_temp_new(); gen_load_fcr(s, fpsr, M68K_FPSR); @@ -5405,7 +5402,7 @@ DISAS_INSN(fsave) if (m68k_feature(s->env, M68K_FEATURE_M68040)) { /* always write IDLE */ - TCGv idle = tcg_const_i32(0x41000000); + TCGv idle = tcg_constant_i32(0x41000000); DEST_EA(env, insn, OS_LONG, idle, NULL); } else { disas_undef(env, s, insn); @@ -5535,7 +5532,7 @@ DISAS_INSN(mac) /* Skip the accumulate if the value is already saturated. */ l1 = gen_new_label(); tmp = tcg_temp_new(); - gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); + gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc)); gen_op_jmp_nz32(tmp, l1); } #endif @@ -5546,11 +5543,11 @@ DISAS_INSN(mac) tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); if (s->env->macsr & MACSR_FI) - gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); + gen_helper_macsatf(cpu_env, tcg_constant_i32(acc)); else if (s->env->macsr & MACSR_SU) - gen_helper_macsats(cpu_env, tcg_const_i32(acc)); + gen_helper_macsats(cpu_env, tcg_constant_i32(acc)); else - gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); + gen_helper_macsatu(cpu_env, tcg_constant_i32(acc)); #if 0 /* Disabled because conditional branches clobber temporary vars. */ @@ -5569,7 +5566,7 @@ DISAS_INSN(mac) /* Skip the accumulate if the value is already saturated. */ l1 = gen_new_label(); tmp = tcg_temp_new(); - gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); + gen_op_and32(tmp, QREG_MACSR, tcg_constant_i32(MACSR_PAV0 << acc)); gen_op_jmp_nz32(tmp, l1); } #endif @@ -5578,18 +5575,18 @@ DISAS_INSN(mac) else tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); if (s->env->macsr & MACSR_FI) - gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); + gen_helper_macsatf(cpu_env, tcg_constant_i32(acc)); else if (s->env->macsr & MACSR_SU) - gen_helper_macsats(cpu_env, tcg_const_i32(acc)); + gen_helper_macsats(cpu_env, tcg_constant_i32(acc)); else - gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); + gen_helper_macsatu(cpu_env, tcg_constant_i32(acc)); #if 0 /* Disabled because conditional branches clobber temporary vars. */ if (l1 != -1) gen_set_label(l1); #endif } - gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); + gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc)); if (insn & 0x30) { TCGv rw; @@ -5639,8 +5636,8 @@ DISAS_INSN(move_mac) int src; TCGv dest; src = insn & 3; - dest = tcg_const_i32((insn >> 9) & 3); - gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); + dest = tcg_constant_i32((insn >> 9) & 3); + gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src)); gen_mac_clear_flags(); gen_helper_mac_set_flags(cpu_env, dest); } @@ -5665,7 +5662,7 @@ DISAS_INSN(from_mext) TCGv reg; TCGv acc; reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); - acc = tcg_const_i32((insn & 0x400) ? 2 : 0); + acc = tcg_constant_i32((insn & 0x400) ? 2 : 0); if (s->env->macsr & MACSR_FI) gen_helper_get_mac_extf(reg, cpu_env, acc); else @@ -5700,7 +5697,7 @@ DISAS_INSN(to_mac) } tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); gen_mac_clear_flags(); - gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); + gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum)); } DISAS_INSN(to_macsr) @@ -5723,7 +5720,7 @@ DISAS_INSN(to_mext) TCGv val; TCGv acc; SRC_EA(env, val, OS_LONG, 0, NULL); - acc = tcg_const_i32((insn & 0x400) ? 2 : 0); + acc = tcg_constant_i32((insn & 0x400) ? 2 : 0); if (s->env->macsr & MACSR_FI) gen_helper_set_mac_extf(cpu_env, val, acc); else if (s->env->macsr & MACSR_SU) diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 5e54ea0108..9770b0eb52 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -28,6 +28,5 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 -#define NB_MMU_MODES 3 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f66df02226..88324d0bc1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,7 +394,7 @@ void mb_tcg_init(void); #define MMU_NOMMU_IDX 0 #define MMU_KERNEL_IDX 1 #define MMU_USER_IDX 2 -/* See NB_MMU_MODES further up the file. */ +/* See NB_MMU_MODES in cpu-defs.h. */ #include "exec/cpu-all.h" diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 8143fcae88..29ac6e9c0f 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" /* * GDB expects SREGs in the following order: diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 480e60aeec..d45f245a67 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -332,7 +332,11 @@ const mips_def_t mips_defs[] = (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), .CP0_Config1 = MIPS_CONFIG1, .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt), + .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) | + (1 << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists), + .CP0_Config7 = 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, @@ -353,7 +357,11 @@ const mips_def_t mips_defs[] = (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt), + .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) | + (1 << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists), + .CP0_Config7 = 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, @@ -392,6 +400,7 @@ const mips_def_t mips_defs[] = .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | (1 << CP0C5_FRE) | (1 << CP0C5_UFR), + .CP0_Config7 = 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32, diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index f4c76994ea..594c91a156 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -29,6 +29,5 @@ #define TARGET_PAGE_BITS_VARY #define TARGET_PAGE_BITS_MIN 12 #endif -#define NB_MMU_MODES 4 #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 05caf54999..01e0fbe10d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "qemu/qemu-print.h" +#include "qemu/error-report.h" #include "qapi/error.h" #include "cpu.h" #include "internal.h" @@ -143,11 +144,13 @@ static bool mips_cpu_has_work(CPUState *cs) /* * Prior to MIPS Release 6 it is implementation dependent if non-enabled * interrupts wake-up the CPU, however most of the implementations only - * check for interrupts that can be taken. + * check for interrupts that can be taken. For pre-release 6 CPUs, + * check for CP0 Config7 'Wait IE ignore' bit. */ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || + (env->CP0_Config7 & (1 << CP0C7_WII)) || (env->insn_flags & ISA_MIPS_R6)) { has_work = true; } diff --git a/target/mips/cpu.h b/target/mips/cpu.h index caf2b06911..142c55af47 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -980,6 +980,7 @@ typedef struct CPUArchState { #define CP0C6_DATAPREF 0 int32_t CP0_Config7; int64_t CP0_Config7_rw_bitmask; +#define CP0C7_WII 31 #define CP0C7_NAPCGEN 2 #define CP0C7_UNIMUEN 1 #define CP0C7_VFPUCGEN 0 diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index f1c2a2cf6d..62d7b72407 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "fpu_helper.h" int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 2970df8a09..05990aa5bb 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -70,8 +70,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) /* is this AM mapped in current execution mode */ return ((adetlb_mask << am) < 0); default: - assert(0); - return TLBRET_BADADDR; + g_assert_not_reached(); }; } diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index d0bd0267b2..c1a8380e34 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -248,14 +248,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong i; for (i = 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], + cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx, GETPC()); addr += 4; } } if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); + cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); } } diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 632895cc9e..e8b193aeda 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, gen_base_offset_addr(ctx, t0, base, offset); - t1 = tcg_const_tl(reglist); - t2 = tcg_const_i32(ctx->mem_idx); + t1 = tcg_constant_tl(reglist); + t2 = tcg_constant_i32(ctx->mem_idx); save_cpu_state(ctx, 1); switch (opc) { @@ -724,9 +724,6 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t2); } @@ -1018,8 +1015,6 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) @@ -1067,7 +1062,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); - tcg_temp_free(t0); } break; #endif @@ -1276,7 +1270,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) * mode. */ ctx->base.is_jmp = DISAS_STOP; - tcg_temp_free(t0); } break; case EI: @@ -1293,7 +1286,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp = DISAS_EXIT; - tcg_temp_free(t0); } break; default: diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 736283e2af..29b31d70fe 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -5333,7 +5333,7 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } msa_move_v(pwd, pwx); } @@ -5368,7 +5368,7 @@ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ } \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } @@ -5413,7 +5413,7 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } } @@ -5461,7 +5461,7 @@ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \ } \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } @@ -5511,7 +5511,7 @@ void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ } \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } @@ -5557,7 +5557,7 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd, } break; default: - assert(0); + g_assert_not_reached(); } } @@ -5632,7 +5632,7 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \ pwd->d[1] = msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } @@ -5771,7 +5771,7 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \ pwd->d[1] = msa_ ## func ## _df(df, pwd->d[1], pws->d[1], pwt->d[1]); \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } @@ -5811,7 +5811,7 @@ static inline void msa_splat_df(uint32_t df, wr_t *pwd, } break; default: - assert(0); + g_assert_not_reached(); } } @@ -5869,7 +5869,7 @@ void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \ MSA_LOOP_D; \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ msa_move_v(pwd, pwx); \ } @@ -6090,7 +6090,7 @@ void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd, pwd->d[n] = (int64_t)pws->d[0]; break; default: - assert(0); + g_assert_not_reached(); } } @@ -6150,7 +6150,7 @@ void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } } @@ -6565,7 +6565,7 @@ static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6596,7 +6596,7 @@ static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6625,7 +6625,7 @@ static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6654,7 +6654,7 @@ static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6683,7 +6683,7 @@ static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6712,7 +6712,7 @@ static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6741,7 +6741,7 @@ static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6770,7 +6770,7 @@ static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6799,7 +6799,7 @@ static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6828,7 +6828,7 @@ static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -6857,7 +6857,7 @@ static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, retaddr); @@ -7107,7 +7107,7 @@ void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7137,7 +7137,7 @@ void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7167,7 +7167,7 @@ void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7198,7 +7198,7 @@ void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7245,7 +7245,7 @@ void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7280,7 +7280,7 @@ void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7317,7 +7317,7 @@ void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7371,7 +7371,7 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7417,7 +7417,7 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7526,7 +7526,7 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } else { - assert(0); + g_assert_not_reached(); } @@ -7555,7 +7555,7 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd, FMAXMIN_A(min, max, pwx->d[0], pws->d[0], pwt->d[0], 64, status); FMAXMIN_A(min, max, pwx->d[1], pws->d[1], pwt->d[1], 64, status); } else { - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7628,7 +7628,7 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } else { - assert(0); + g_assert_not_reached(); } @@ -7657,7 +7657,7 @@ void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd, FMAXMIN_A(max, min, pwx->d[0], pws->d[0], pwt->d[0], 64, status); FMAXMIN_A(max, min, pwx->d[1], pws->d[1], pwt->d[1], 64, status); } else { - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7681,7 +7681,7 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df, pwd->d[0] = float_class_d(pws->d[0], status); pwd->d[1] = float_class_d(pws->d[1], status); } else { - assert(0); + g_assert_not_reached(); } } @@ -7723,7 +7723,7 @@ void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7753,7 +7753,7 @@ void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7783,7 +7783,7 @@ void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7832,7 +7832,7 @@ void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7862,7 +7862,7 @@ void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7892,7 +7892,7 @@ void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7946,7 +7946,7 @@ void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -7983,7 +7983,7 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -8019,7 +8019,7 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -8046,7 +8046,7 @@ void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } msa_move_v(pwd, pwx); @@ -8072,7 +8072,7 @@ void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } msa_move_v(pwd, pwx); @@ -8100,7 +8100,7 @@ void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -8130,7 +8130,7 @@ void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -8166,7 +8166,7 @@ void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); @@ -8196,7 +8196,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } check_msacsr_cause(env, GETPC()); diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 1bcdbb1121..220cd3b048 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -217,8 +217,6 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, /* if some bit is non-zero then some element is zero */ tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(tresult, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) @@ -237,7 +235,6 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; @@ -545,8 +542,6 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a) gen_load_gpr(telm, a->ws); gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); - tcg_temp_free(telm); - return true; } @@ -563,8 +558,6 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); gen_store_gpr(telm, a->wd); - tcg_temp_free(telm); - return true; } @@ -782,8 +775,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); - tcg_temp_free(taddr); - return true; } diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index f52244e1b2..bdd20709c0 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -513,8 +513,6 @@ static void gen_mxu_s32i2m(DisasContext *ctx) } else if (XRa == 16) { gen_store_mxu_cr(t0); } - - tcg_temp_free(t0); } /* @@ -537,8 +535,6 @@ static void gen_mxu_s32m2i(DisasContext *ctx) } gen_store_gpr(t0, Rb); - - tcg_temp_free(t0); } /* @@ -613,9 +609,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx) } gen_store_mxu_gpr(t0, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); } /* @@ -664,11 +657,6 @@ static void gen_mxu_d16mul(DisasContext *ctx) } gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); } /* @@ -741,11 +729,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) } gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); } /* @@ -821,15 +804,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) gen_store_mxu_gpr(t0, XRd); gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); - tcg_temp_free(t5); - tcg_temp_free(t6); - tcg_temp_free(t7); } /* @@ -860,9 +834,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP)); gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); } @@ -1101,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) uint32_t XRx = XRb ? XRb : XRc; /* ...and do half-word-wise max/min with one operand 0 */ TCGv_i32 t0 = tcg_temp_new(); - TCGv_i32 t1 = tcg_const_i32(0); + TCGv_i32 t1 = tcg_constant_i32(0); /* the left half-word first */ tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); @@ -1125,9 +1096,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) tcg_gen_shri_i32(t0, t0, 16); /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); } else if (unlikely(XRb == XRc)) { /* both operands same -> just set destination to one of them */ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); @@ -1161,9 +1129,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) tcg_gen_shri_i32(t0, t0, 16); /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); } } @@ -1198,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) uint32_t XRx = XRb ? XRb : XRc; /* ...and do byte-wise max/min with one operand 0 */ TCGv_i32 t0 = tcg_temp_new(); - TCGv_i32 t1 = tcg_const_i32(0); + TCGv_i32 t1 = tcg_constant_i32(0); int32_t i; /* the leftmost byte (byte 3) first */ @@ -1226,9 +1191,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } - - tcg_temp_free(t1); - tcg_temp_free(t0); } else if (unlikely(XRb == XRc)) { /* both operands same -> just set destination to one of them */ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); @@ -1266,9 +1228,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } - - tcg_temp_free(t1); - tcg_temp_free(t0); } } @@ -1384,9 +1343,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 24); tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN2: @@ -1410,9 +1366,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 16); tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN3: @@ -1436,9 +1389,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 8); tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN4: @@ -1598,7 +1548,6 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) } gen_set_label(l_exit); - tcg_temp_free(t_mxu_cr); } return true; diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index faf6d679bd..9398e28000 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1005,13 +1005,9 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, tcg_gen_extr_i64_tl(tmp1, tmp2, tval); } gen_store_gpr(tmp1, reg1); - tcg_temp_free(tmp1); gen_store_gpr(tmp2, reg2); - tcg_temp_free(tmp2); tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); - tcg_temp_free_i64(tval); tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); - tcg_temp_free(taddr); } static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, @@ -1084,9 +1080,6 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count, /* adjust stack pointer */ gen_adjust_sp(ctx, -u); - - tcg_temp_free(t0); - tcg_temp_free(va); } static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, @@ -1110,9 +1103,6 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, /* adjust stack pointer */ gen_adjust_sp(ctx, u); - - tcg_temp_free(t0); - tcg_temp_free(va); } static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, @@ -1232,8 +1222,6 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, if (insn_bytes == 2) { ctx->hflags |= MIPS_HFLAG_B16; } - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_pool16c_nanomips_insn(DisasContext *ctx) @@ -1358,7 +1346,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } break; } - tcg_temp_free(t0); #endif } else { gen_slt(ctx, OPC_SLTU, rd, rs, rt); @@ -1381,10 +1368,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) /* operands of same sign, result different sign */ tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0); gen_store_gpr(t0, rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } break; case NM_MUL: @@ -1427,7 +1410,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3)); - tcg_temp_free(t0); } break; case NM_D_E_MT_VPE: @@ -1467,8 +1449,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } break; } - - tcg_temp_free(t0); } break; case NM_FORK: @@ -1480,8 +1460,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); gen_helper_fork(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case NM_MFTR: @@ -1508,7 +1486,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rs); gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; #endif @@ -1557,11 +1534,6 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free_i32(t0); - - tcg_temp_free(v0_t); - tcg_temp_free(v1_t); } @@ -1682,10 +1654,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(v0_t); } static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, @@ -1802,8 +1770,6 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free_i32(t0); } static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -1855,10 +1821,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_MULT: @@ -1878,8 +1842,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case NM_EXTRV_W: @@ -1915,10 +1877,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_MULTU: @@ -1938,8 +1898,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case NM_EXTRV_R_W: @@ -1982,10 +1940,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_EXTRV_RS_W: @@ -2027,10 +1983,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_EXTRV_S_H: @@ -2045,12 +1999,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(t0); - tcg_temp_free(t1); - - tcg_temp_free(v0_t); - tcg_temp_free(v1_t); } static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -2162,7 +2110,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_load_gpr(tv0, rt); gen_helper_insv(v0_t, cpu_env, v0_t, tv0); gen_store_gpr(v0_t, ret); - tcg_temp_free(tv0); } break; case NM_RADDU_W_QB: @@ -2188,9 +2135,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(v0_t); - tcg_temp_free(t0); } static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -2243,8 +2187,6 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); - tcg_temp_free(rs_t); } @@ -2304,7 +2246,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; - tcg_temp_free(t0); } break; case NM_EI: @@ -2317,7 +2258,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode */ ctx->base.is_jmp = DISAS_STOP; - tcg_temp_free(t0); } break; case NM_RDPGPR: @@ -2374,7 +2314,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, /* Unconditional branch */ } else if (rt == 0 && imm != 0) { /* Treat as NOP */ - goto out; + return; } else { cond = TCG_COND_EQ; } @@ -2384,12 +2324,12 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, check_nms(ctx); if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) { gen_reserved_instruction(ctx); - goto out; + return; } else if (rt == 0 && opc == NM_BBEQZC) { /* Unconditional branch */ } else if (rt == 0 && opc == NM_BBNEZC) { /* Treat as NOP */ - goto out; + return; } else { tcg_gen_shri_tl(t0, t0, imm); tcg_gen_andi_tl(t0, t0, 1); @@ -2404,7 +2344,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, case NM_BNEIC: if (rt == 0 && imm == 0) { /* Treat as NOP */ - goto out; + return; } else if (rt == 0 && imm != 0) { /* Unconditional branch */ } else { @@ -2434,7 +2374,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, default: MIPS_INVAL("Immediate Value Compact branch"); gen_reserved_instruction(ctx); - goto out; + return; } /* branch completion */ @@ -2455,10 +2395,6 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc, gen_goto_tb(ctx, 0, ctx->base.pc_next + 4); } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } /* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */ @@ -2488,9 +2424,6 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs, /* unconditional branch to register */ tcg_gen_mov_tl(cpu_PC, btarget); tcg_gen_lookup_and_goto_ptr(); - - tcg_temp_free(t0); - tcg_temp_free(t1); } /* nanoMIPS Branches */ @@ -2540,14 +2473,12 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, gen_load_gpr(tbase, rt); tcg_gen_movi_tl(toffset, offset); gen_op_addr_add(ctx, btarget, tbase, toffset); - tcg_temp_free(tbase); - tcg_temp_free(toffset); } break; default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } if (bcond_compute == 0) { @@ -2559,7 +2490,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } } else { /* Conditional compact branch */ @@ -2620,7 +2551,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, default: MIPS_INVAL("Compact conditional branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } /* branch completion */ @@ -2633,10 +2564,6 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc, gen_goto_tb(ctx, 0, ctx->base.pc_next + 4); } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } @@ -2664,15 +2591,12 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } tcg_gen_trunc_i64_tl(bcond, t0); ctx->btarget = btarget; - -out: - tcg_temp_free_i64(t0); } @@ -2709,7 +2633,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) break; default: gen_reserved_instruction(ctx); - goto out; + return; } } gen_op_addr_add(ctx, t0, t0, t1); @@ -2799,10 +2723,6 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt) gen_reserved_instruction(ctx); break; } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_pool32f_nanomips_insn(DisasContext *ctx) @@ -3439,21 +3359,19 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, case 0: /* PRECR_SRA_PH_W */ { - TCGv_i32 sa_t = tcg_const_i32(rd); + TCGv_i32 sa_t = tcg_constant_i32(rd); gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t, cpu_gpr[rt]); gen_store_gpr(v1_t, rt); - tcg_temp_free_i32(sa_t); } break; case 1: /* PRECR_SRA_R_PH_W */ { - TCGv_i32 sa_t = tcg_const_i32(rd); + TCGv_i32 sa_t = tcg_constant_i32(rd); gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t, cpu_gpr[rt]); gen_store_gpr(v1_t, rt); - tcg_temp_free_i32(sa_t); } break; } @@ -3536,8 +3454,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, tcg_gen_movi_tl(tv0, rd >> 3); tcg_gen_movi_tl(tv1, imm); gen_helper_shilo(tv0, tv1, cpu_env); - tcg_temp_free(tv1); - tcg_temp_free(tv0); } break; case NM_MULEQ_S_W_PHL: @@ -3652,10 +3568,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(v2_t); - tcg_temp_free(v1_t); - tcg_temp_free(t0); } static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) @@ -3827,7 +3739,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL); - tcg_temp_free(t0); } break; case NM_SWPC48: @@ -3844,9 +3755,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); - - tcg_temp_free(t0); - tcg_temp_free(t1); } break; default: @@ -3908,8 +3816,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rs); tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm); gen_store_gpr(t0, rt); - - tcg_temp_free(t0); } break; case NM_ADDIUNEG: @@ -3958,18 +3864,15 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_nms(ctx); if (rt != 0) { TCGv t0 = tcg_temp_new(); - TCGv_i32 shift = tcg_const_i32(extract32(ctx->opcode, 0, 5)); - TCGv_i32 shiftx = tcg_const_i32(extract32(ctx->opcode, 7, 4) - << 1); - TCGv_i32 stripe = tcg_const_i32(extract32(ctx->opcode, 6, 1)); + TCGv_i32 shift = + tcg_constant_i32(extract32(ctx->opcode, 0, 5)); + TCGv_i32 shiftx = + tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1); + TCGv_i32 stripe = + tcg_constant_i32(extract32(ctx->opcode, 6, 1)); gen_load_gpr(t0, rs); gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); - tcg_temp_free(t0); - - tcg_temp_free_i32(shift); - tcg_temp_free_i32(shiftx); - tcg_temp_free_i32(stripe); } break; case NM_P_INS: @@ -4239,8 +4142,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) MO_UNALN); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case NM_P_LL: @@ -4432,8 +4333,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } counter++; } - tcg_temp_free(va); - tcg_temp_free(t1); } break; default: @@ -4454,7 +4353,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rt); tcg_gen_mov_tl(cpu_gpr[rd], t0); gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s); - tcg_temp_free(t0); } break; case NM_P_BAL: @@ -4604,9 +4502,8 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) /* make sure instructions are on a halfword boundary */ if (ctx->base.pc_next & 0x1) { - TCGv tmp = tcg_const_tl(ctx->base.pc_next); + TCGv tmp = tcg_constant_tl(ctx->base.pc_next); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); - tcg_temp_free(tmp); generate_exception_end(ctx, EXCP_AdEL); return 2; } @@ -4941,8 +4838,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t1, rt); tcg_gen_mov_tl(cpu_gpr[rd], t0); tcg_gen_mov_tl(cpu_gpr[re], t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; default: diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 6a207d2e7e..103c304d10 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -40,8 +40,6 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) ctx->hflags |= MIPS_HFLAG_BC; ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4; ctx->hflags |= MIPS_HFLAG_BDS32; - - tcg_temp_free(t0); return true; } @@ -61,10 +59,6 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) tcg_gen_add_tl(t0, t0, t1); tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } @@ -83,10 +77,6 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) gen_load_gpr(t1, a->rt); tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } @@ -103,8 +93,6 @@ static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a) gen_load_gpr(t0, a->rs); tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); - tcg_temp_free(t0); - return true; } @@ -121,8 +109,6 @@ static bool trans_CINS(DisasContext *ctx, arg_CINS *a) gen_load_gpr(t0, a->rs); tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); - tcg_temp_free(t0); - return true; } @@ -142,8 +128,6 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a) } tcg_gen_ctpop_tl(t0, t0); gen_store_gpr(t0, a->rd); - tcg_temp_free(t0); - return true; } @@ -167,10 +151,6 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a) } else { tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); } - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } @@ -194,8 +174,5 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a) } else { tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); } - - tcg_temp_free(t0); - return true; } diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c index 85f0567a7f..f3735df7b9 100644 --- a/target/mips/tcg/sysemu/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c @@ -20,7 +20,8 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/log.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" +#include "gdbstub/helpers.h" #include "semihosting/softmmu-uaccess.h" #include "semihosting/semihost.h" #include "semihosting/console.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8cad3d15a0..1fb4ef7127 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1274,11 +1274,8 @@ static inline void gen_load_srsgpr(int from, int to) tcg_gen_add_ptr(addr, cpu_env, addr); tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); - tcg_temp_free_ptr(addr); - tcg_temp_free_i32(t2); } gen_store_gpr(t0, to); - tcg_temp_free(t0); } static inline void gen_store_srsgpr(int from, int to) @@ -1297,9 +1294,6 @@ static inline void gen_store_srsgpr(int from, int to) tcg_gen_add_ptr(addr, cpu_env, addr); tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); - tcg_temp_free_ptr(addr); - tcg_temp_free_i32(t2); - tcg_temp_free(t0); } } @@ -1396,7 +1390,6 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) t64 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t64, t); tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); - tcg_temp_free_i64(t64); } static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) @@ -1414,7 +1407,6 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) TCGv_i64 t64 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t64, t); tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); - tcg_temp_free_i64(t64); } else { gen_store_fpr32(ctx, t, reg | 1); } @@ -1439,7 +1431,6 @@ void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) t0 = tcg_temp_new_i64(); tcg_gen_shri_i64(t0, t, 32); tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); - tcg_temp_free_i64(t0); } } @@ -1852,8 +1843,6 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ default: \ abort(); \ } \ - tcg_temp_free_i##bits(fp0); \ - tcg_temp_free_i##bits(fp1); \ } FOP_CONDS(, 0, d, FMT_D, 64) @@ -1946,8 +1935,6 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \ abort(); \ } \ STORE; \ - tcg_temp_free_i ## bits(fp0); \ - tcg_temp_free_i ## bits(fp1); \ } FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) @@ -1967,7 +1954,6 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \ - tcg_temp_free(t0); \ } #else #define OP_LD_ATOMIC(insn, fname) \ @@ -2009,11 +1995,65 @@ static target_ulong pc_relative_pc(DisasContext *ctx) return pc; } +/* LWL or LDL, depending on MemOp. */ +static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr, + int mem_idx, MemOp mop) +{ + int sizem1 = memop_size(mop) - 1; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + /* + * Do a byte access to possibly trigger a page + * fault with the unaligned address. + */ + tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); + tcg_gen_andi_tl(t1, addr, sizem1); + if (!cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, sizem1); + } + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, addr, ~sizem1); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); + tcg_gen_shl_tl(t0, t0, t1); + tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); + tcg_gen_andc_tl(t1, reg, t1); + tcg_gen_or_tl(reg, t0, t1); +} + +/* LWR or LDR, depending on MemOp. */ +static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr, + int mem_idx, MemOp mop) +{ + int size = memop_size(mop); + int sizem1 = size - 1; + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + /* + * Do a byte access to possibly trigger a page + * fault with the unaligned address. + */ + tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); + tcg_gen_andi_tl(t1, addr, sizem1); + if (cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, sizem1); + } + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, addr, ~sizem1); + tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, size * 8 - 1); + tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1); + tcg_gen_and_tl(t1, reg, t1); + tcg_gen_or_tl(reg, t0, t1); +} + /* Load */ static void gen_ld(DisasContext *ctx, uint32_t opc, int rt, int base, int offset) { - TCGv t0, t1, t2; + TCGv t0, t1; int mem_idx = ctx->mem_idx; if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | @@ -2048,65 +2088,26 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, break; case OPC_LDL: t1 = tcg_temp_new(); - /* - * Do a byte access to possibly trigger a page - * fault with the unaligned address. - */ - tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 7); - if (!cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 7); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~7); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); - tcg_gen_shl_tl(t0, t0, t1); - t2 = tcg_const_tl(-1); - tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - gen_store_gpr(t0, rt); + gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ); + gen_store_gpr(t1, rt); break; case OPC_LDR: t1 = tcg_temp_new(); - /* - * Do a byte access to possibly trigger a page - * fault with the unaligned address. - */ - tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 7); - if (cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 7); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~7); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); - tcg_gen_shr_tl(t0, t0, t1); - tcg_gen_xori_tl(t1, t1, 63); - t2 = tcg_const_tl(0xfffffffffffffffeull); - tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - gen_store_gpr(t0, rt); + gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ); + gen_store_gpr(t1, rt); break; case OPC_LDPC: - t1 = tcg_const_tl(pc_relative_pc(ctx)); + t1 = tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); gen_store_gpr(t0, rt); break; #endif case OPC_LWPC: - t1 = tcg_const_tl(pc_relative_pc(ctx)); + t1 = tcg_constant_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); gen_store_gpr(t0, rt); break; @@ -2153,57 +2154,20 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, /* fall through */ case OPC_LWL: t1 = tcg_temp_new(); - /* - * Do a byte access to possibly trigger a page - * fault with the unaligned address. - */ - tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 3); - if (!cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 3); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~3); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL); - tcg_gen_shl_tl(t0, t0, t1); - t2 = tcg_const_tl(-1); - tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - tcg_gen_ext32s_tl(t0, t0); - gen_store_gpr(t0, rt); + gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL); + tcg_gen_ext32s_tl(t1, t1); + gen_store_gpr(t1, rt); break; case OPC_LWRE: mem_idx = MIPS_HFLAG_UM; /* fall through */ case OPC_LWR: t1 = tcg_temp_new(); - /* - * Do a byte access to possibly trigger a page - * fault with the unaligned address. - */ - tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 3); - if (cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 3); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~3); - tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL); - tcg_gen_shr_tl(t0, t0, t1); - tcg_gen_xori_tl(t1, t1, 31); - t2 = tcg_const_tl(0xfffffffeull); - tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - tcg_gen_ext32s_tl(t0, t0); - gen_store_gpr(t0, rt); + gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL); + tcg_gen_ext32s_tl(t1, t1); + gen_store_gpr(t1, rt); break; case OPC_LLE: mem_idx = MIPS_HFLAG_UM; @@ -2214,7 +2178,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rt); break; } - tcg_temp_free(t0); } /* Store */ @@ -2273,8 +2236,6 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt, gen_helper_0e2i(swr, t1, t0, mem_idx); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } @@ -2291,7 +2252,6 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, /* compare the address against that of the preceding LL */ gen_base_offset_addr(ctx, addr, base, offset); tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); - tcg_temp_free(addr); tcg_gen_movi_tl(t0, 0); gen_store_gpr(t0, rt); tcg_gen_br(done); @@ -2304,10 +2264,8 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); gen_store_gpr(t0, rt); - tcg_temp_free(val); gen_set_label(done); - tcg_temp_free(t0); } /* Load and store */ @@ -2325,7 +2283,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); - tcg_temp_free_i32(fp0); } break; case OPC_SWC1: @@ -2334,7 +2291,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, gen_load_fpr32(ctx, fp0, ft); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free_i32(fp0); } break; case OPC_LDC1: @@ -2343,7 +2299,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); - tcg_temp_free_i64(fp0); } break; case OPC_SDC1: @@ -2352,7 +2307,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, gen_load_fpr64(ctx, fp0, ft); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free_i64(fp0); } break; default: @@ -2381,7 +2335,6 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, } else { generate_exception_err(ctx, EXCP_CpU, 1); } - tcg_temp_free(t0); } /* Arithmetic with immediate operand */ @@ -2412,15 +2365,12 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, tcg_gen_xori_tl(t1, t1, ~uimm); tcg_gen_xori_tl(t2, t0, uimm); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; case OPC_ADDIU: @@ -2445,14 +2395,11 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, tcg_gen_xori_tl(t1, t1, ~uimm); tcg_gen_xori_tl(t2, t0, uimm); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; case OPC_DADDIU: @@ -2535,7 +2482,6 @@ static void gen_slt_imm(DisasContext *ctx, uint32_t opc, tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); break; } - tcg_temp_free(t0); } /* Shifts with immediate operand */ @@ -2575,7 +2521,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, tcg_gen_trunc_tl_i32(t1, t0); tcg_gen_rotri_i32(t1, t1, uimm); tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); - tcg_temp_free_i32(t1); } else { tcg_gen_ext32s_tl(cpu_gpr[rt], t0); } @@ -2611,7 +2556,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, break; #endif } - tcg_temp_free(t0); } /* Arithmetic */ @@ -2642,14 +2586,11 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t1, t1, t2); tcg_gen_xor_tl(t2, t0, t2); tcg_gen_andc_tl(t1, t2, t1); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_ADDU: @@ -2678,9 +2619,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t2, t1, t2); tcg_gen_xor_tl(t1, t0, t1); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* * operands of different sign, first operand and the result * of different sign @@ -2688,7 +2627,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_SUBU: @@ -2718,14 +2656,11 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t1, t1, t2); tcg_gen_xor_tl(t2, t0, t2); tcg_gen_andc_tl(t1, t2, t1); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_DADDU: @@ -2752,9 +2687,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t2, t1, t2); tcg_gen_xor_tl(t1, t0, t1); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* * Operands of different sign, first operand and result different * sign. @@ -2762,7 +2695,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_DSUBU: @@ -2801,7 +2733,7 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc, t0 = tcg_temp_new(); gen_load_gpr(t0, rt); - t1 = tcg_const_tl(0); + t1 = tcg_constant_tl(0); t2 = tcg_temp_new(); gen_load_gpr(t2, rs); switch (opc) { @@ -2818,9 +2750,6 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc, tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); break; } - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); } /* Logic */ @@ -2899,8 +2828,6 @@ static void gen_slt(DisasContext *ctx, uint32_t opc, tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } /* Shifts */ @@ -2947,8 +2874,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_gen_andi_i32(t2, t2, 0x1f); tcg_gen_rotr_i32(t2, t3, t2); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -2970,8 +2895,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); } /* Arithmetic on HI/LO registers */ @@ -3041,10 +2964,9 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) static inline void gen_r6_ld(target_long addr, int reg, int memidx, MemOp memop) { - TCGv t0 = tcg_const_tl(addr); - tcg_gen_qemu_ld_tl(t0, t0, memidx, memop); + TCGv t0 = tcg_temp_new(); + tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop); gen_store_gpr(t0, reg); - tcg_temp_free(t0); } static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, @@ -3141,8 +3063,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MOD: @@ -3160,34 +3080,28 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DIVU: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MODU: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MUL: @@ -3198,8 +3112,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mul_i32(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MUH: @@ -3210,8 +3122,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MULU: @@ -3222,8 +3132,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mul_i32(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MUHU: @@ -3234,8 +3142,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -3251,8 +3157,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMOD: @@ -3267,28 +3171,22 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DDIVU: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMODU: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMUL: @@ -3298,7 +3196,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) { TCGv t2 = tcg_temp_new(); tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); } break; case R6_OPC_DMULU: @@ -3308,18 +3205,14 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) { TCGv t2 = tcg_temp_new(); tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); } break; #endif default: MIPS_INVAL("r6 mul/div"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } #if defined(TARGET_MIPS64) @@ -3351,14 +3244,12 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) tcg_gen_rem_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case MMI_OPC_DIVU1: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); @@ -3366,18 +3257,13 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) tcg_gen_remu_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; default: MIPS_INVAL("div1 TX79"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } #endif @@ -3414,14 +3300,12 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_rem_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DIVU: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); @@ -3429,8 +3313,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_remu_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_MULT: @@ -3442,8 +3324,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case OPC_MULTU: @@ -3455,8 +3335,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -3473,19 +3351,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_LO[acc], t0, t1); tcg_gen_rem_tl(cpu_HI[acc], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DDIVU: { - TCGv t2 = tcg_const_tl(0); - TCGv t3 = tcg_const_tl(1); + TCGv t2 = tcg_constant_tl(0); + TCGv t3 = tcg_constant_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_LO[acc], t0, t1); tcg_gen_remu_i64(cpu_HI[acc], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DMULT: @@ -3505,10 +3379,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MADDU: @@ -3523,10 +3395,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MSUB: @@ -3539,10 +3409,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MSUBU: @@ -3557,20 +3425,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; default: MIPS_INVAL("mul/div"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } /* @@ -3625,8 +3488,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, } tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case MMI_OPC_MULTU1: @@ -3644,8 +3505,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, } tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case MMI_OPC_MADD1: @@ -3661,13 +3520,11 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); if (rd) { gen_move_low32(cpu_gpr[rd], t2); } - tcg_temp_free_i64(t2); } break; case MMI_OPC_MADDU1: @@ -3685,24 +3542,18 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); if (rd) { gen_move_low32(cpu_gpr[rd], t2); } - tcg_temp_free_i64(t2); } break; default: MIPS_INVAL("mul/madd TXx9"); gen_reserved_instruction(ctx); - goto out; + break; } - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_cl(DisasContext *ctx, uint32_t opc, @@ -3924,9 +3775,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(t1); } /* Loongson multimedia instructions */ @@ -4221,7 +4069,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_xor_i64(t1, t1, t2); tcg_gen_xor_i64(t2, t2, t0); tcg_gen_andc_i64(t1, t2, t1); - tcg_temp_free_i64(t2); tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); @@ -4242,7 +4089,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_xor_i64(t1, t1, t2); tcg_gen_xor_i64(t2, t2, t0); tcg_gen_and_i64(t1, t1, t2); - tcg_temp_free_i64(t2); tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); @@ -4284,12 +4130,8 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_extrl_i64_i32(t32, t64); tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, get_fp_bit(cc), 1); - - tcg_temp_free_i32(t32); - tcg_temp_free_i64(t64); } - goto no_rd; - break; + return; default: MIPS_INVAL("loongson_cp2"); gen_reserved_instruction(ctx); @@ -4297,16 +4139,12 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) } gen_store_fpr64(ctx, t0, rd); - -no_rd: - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } static void gen_loongson_lswc2(DisasContext *ctx, int rt, int rs, int rd) { - TCGv t0, t1, t2; + TCGv t0, t1; TCGv_i32 fp0; #if defined(TARGET_MIPS64) int lsq_rt1 = ctx->opcode & 0x1f; @@ -4328,7 +4166,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); - tcg_temp_free(t1); break; case OPC_GSLQC1: check_cp1_enabled(ctx); @@ -4341,7 +4178,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); - tcg_temp_free(t1); break; case OPC_GSSQ: t1 = tcg_temp_new(); @@ -4353,7 +4189,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_gpr(t1, lsq_rt1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; case OPC_GSSQC1: check_cp1_enabled(ctx); @@ -4366,7 +4201,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr64(ctx, t1, lsq_rt1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif case OPC_GSSHFL: @@ -4374,109 +4208,41 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, case OPC_GSLWLC1: check_cp1_enabled(ctx); gen_base_offset_addr(ctx, t0, rs, shf_offset); - t1 = tcg_temp_new(); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 3); - if (!cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 3); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~3); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); - tcg_gen_shl_tl(t0, t0, t1); - t2 = tcg_const_tl(-1); - tcg_gen_shl_tl(t2, t2, t1); fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, rt); + t1 = tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); -#if defined(TARGET_MIPS64) - tcg_gen_extrl_i64_i32(fp0, t0); -#else - tcg_gen_ext32s_tl(fp0, t0); -#endif + gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; case OPC_GSLWRC1: check_cp1_enabled(ctx); gen_base_offset_addr(ctx, t0, rs, shf_offset); - t1 = tcg_temp_new(); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 3); - if (cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 3); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~3); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); - tcg_gen_shr_tl(t0, t0, t1); - tcg_gen_xori_tl(t1, t1, 31); - t2 = tcg_const_tl(0xfffffffeull); - tcg_gen_shl_tl(t2, t2, t1); fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, rt); + t1 = tcg_temp_new(); tcg_gen_ext_i32_tl(t1, fp0); - tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); -#if defined(TARGET_MIPS64) - tcg_gen_extrl_i64_i32(fp0, t0); -#else - tcg_gen_ext32s_tl(fp0, t0); -#endif + gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_trunc_tl_i32(fp0, t1); gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSLDLC1: check_cp1_enabled(ctx); gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 = tcg_temp_new(); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 7); - if (!cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 7); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~7); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); - tcg_gen_shl_tl(t0, t0, t1); - t2 = tcg_const_tl(-1); - tcg_gen_shl_tl(t2, t2, t1); gen_load_fpr64(ctx, t1, rt); - tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - gen_store_fpr64(ctx, t0, rt); + gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); + gen_store_fpr64(ctx, t1, rt); break; case OPC_GSLDRC1: check_cp1_enabled(ctx); gen_base_offset_addr(ctx, t0, rs, shf_offset); t1 = tcg_temp_new(); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_andi_tl(t1, t0, 7); - if (cpu_is_bigendian(ctx)) { - tcg_gen_xori_tl(t1, t1, 7); - } - tcg_gen_shli_tl(t1, t1, 3); - tcg_gen_andi_tl(t0, t0, ~7); - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); - tcg_gen_shr_tl(t0, t0, t1); - tcg_gen_xori_tl(t1, t1, 63); - t2 = tcg_const_tl(0xfffffffffffffffeull); - tcg_gen_shl_tl(t2, t2, t1); gen_load_fpr64(ctx, t1, rt); - tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); - tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); - gen_store_fpr64(ctx, t0, rt); + gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); + gen_store_fpr64(ctx, t1, rt); break; #endif default: @@ -4495,8 +4261,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); - tcg_temp_free_i32(fp0); - tcg_temp_free(t1); break; case OPC_GSSWRC1: check_cp1_enabled(ctx); @@ -4506,8 +4270,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); - tcg_temp_free_i32(fp0); - tcg_temp_free(t1); break; #if defined(TARGET_MIPS64) case OPC_GSSDLC1: @@ -4516,7 +4278,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_load_fpr64(ctx, t1, rt); gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); - tcg_temp_free(t1); break; case OPC_GSSDRC1: check_cp1_enabled(ctx); @@ -4524,7 +4285,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_load_fpr64(ctx, t1, rt); gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); - tcg_temp_free(t1); break; #endif default: @@ -4538,7 +4298,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } /* Loongson EXT LDC2/SDC2 */ @@ -4633,7 +4392,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSLDXC1: @@ -4650,21 +4408,18 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); - tcg_temp_free(t1); break; case OPC_GSSHX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; case OPC_GSSWX: t1 = tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: @@ -4672,7 +4427,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif case OPC_GSSWXC1: @@ -4680,7 +4434,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: @@ -4688,14 +4441,11 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, gen_load_fpr64(ctx, t1, rt); tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif default: break; } - - tcg_temp_free(t0); } /* Traps */ @@ -4805,8 +4555,6 @@ static void gen_trap(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_TRAP); gen_set_label(l1); } - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) @@ -4887,6 +4635,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, break; case OPC_J: case OPC_JAL: + { + /* Jump to immediate */ + int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 + : 0xF0000000; + btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) + | (uint32_t)offset; + break; + } case OPC_JALX: /* Jump to immediate */ btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | @@ -5072,8 +4828,6 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, if (insn_bytes == 2) { ctx->hflags |= MIPS_HFLAG_B16; } - tcg_temp_free(t0); - tcg_temp_free(t1); } @@ -5142,13 +4896,9 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, fail: MIPS_INVAL("bitops"); gen_reserved_instruction(ctx); - tcg_temp_free(t0); - tcg_temp_free(t1); return; } gen_store_gpr(t0, rt); - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) @@ -5166,15 +4916,13 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_WSBH: { TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_const_tl(0x00FF00FF); + TCGv t2 = tcg_constant_tl(0x00FF00FF); tcg_gen_shri_tl(t1, t0, 8); tcg_gen_and_tl(t1, t1, t2); tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); } break; @@ -5188,21 +4936,19 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_DSBH: { TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL); + TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL); tcg_gen_shri_tl(t1, t0, 8); tcg_gen_and_tl(t1, t1, t2); tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); } break; case OPC_DSHD: { TCGv t1 = tcg_temp_new(); - TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL); + TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL); tcg_gen_shri_tl(t1, t0, 16); tcg_gen_and_tl(t1, t1, t2); @@ -5212,18 +4958,14 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) tcg_gen_shri_tl(t1, t0, 32); tcg_gen_shli_tl(t0, t0, 32); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); } break; #endif default: MIPS_INVAL("bsfhl"); gen_reserved_instruction(ctx); - tcg_temp_free(t0); return; } - tcg_temp_free(t0); } static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, @@ -5262,7 +5004,6 @@ static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, tcg_gen_concat_tl_i64(t2, t1, t0); tcg_gen_shri_i64(t2, t2, 32 - bits); gen_move_low32(cpu_gpr[rd], t2); - tcg_temp_free_i64(t2); } break; #if defined(TARGET_MIPS64) @@ -5273,10 +5014,7 @@ static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, break; #endif } - tcg_temp_free(t1); } - - tcg_temp_free(t0); } void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp) @@ -5303,7 +5041,6 @@ static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) break; #endif } - tcg_temp_free(t0); } #ifndef CONFIG_USER_ONLY @@ -5321,8 +5058,6 @@ static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off) tcg_gen_concat32_i64(t1, t1, t0); #endif tcg_gen_st_i64(t1, cpu_env, off); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t0); } static inline void gen_mthc0_store64(TCGv arg, target_ulong off) @@ -5334,8 +5069,6 @@ static inline void gen_mthc0_store64(TCGv arg, target_ulong off) tcg_gen_ld_i64(t1, cpu_env, off); tcg_gen_concat32_i64(t1, t1, t0); tcg_gen_st_i64(t1, cpu_env, off); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t0); } static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) @@ -5349,7 +5082,6 @@ static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) tcg_gen_shri_i64(t0, t0, 32); #endif gen_move_low32(arg, t0); - tcg_temp_free_i64(t0); } static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) @@ -5359,7 +5091,6 @@ static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) tcg_gen_ld_i64(t0, cpu_env, off); tcg_gen_shri_i64(t0, t0, 32 + shift); gen_move_low32(arg, t0); - tcg_temp_free_i64(t0); } static inline void gen_mfc0_load32(TCGv arg, target_ulong off) @@ -5368,7 +5099,6 @@ static inline void gen_mfc0_load32(TCGv arg, target_ulong off) tcg_gen_ld_i32(t0, cpu_env, off); tcg_gen_ext_i32_tl(arg, t0); - tcg_temp_free_i32(t0); } static inline void gen_mfc0_load64(TCGv arg, target_ulong off) @@ -5383,7 +5113,6 @@ static inline void gen_mtc0_store32(TCGv arg, target_ulong off) tcg_gen_trunc_tl_i32(t0, arg); tcg_gen_st_i32(t0, cpu_env, off); - tcg_temp_free_i32(t0); } #define CP0_CHECK(c) \ @@ -5705,7 +5434,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) } #endif gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name = "EntryLo0"; break; @@ -5763,7 +5491,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) } #endif gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name = "EntryLo1"; break; @@ -6292,7 +6019,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo)); gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name = "TagLo"; break; @@ -8733,7 +8459,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, case 5: case 6: case 7: - gen_helper_mftc0_configx(t0, cpu_env, tcg_const_tl(sel)); + gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel)); break; default: goto die; @@ -8813,13 +8539,11 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32h(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } break; case 3: @@ -8836,11 +8560,9 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, } trace_mips_translate_tr("mftr", rt, u, sel, h); gen_store_gpr(t0, rd); - tcg_temp_free(t0); return; die: - tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); gen_reserved_instruction(ctx); } @@ -9017,13 +8739,11 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, rd); - tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32h(ctx, fp0, rd); - tcg_temp_free_i32(fp0); } break; case 3: @@ -9041,11 +8761,9 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, } } trace_mips_translate_tr("mttr", rd, u, sel, h); - tcg_temp_free(t0); return; die: - tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); gen_reserved_instruction(ctx); } @@ -9071,7 +8789,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn = "mtc0"; break; @@ -9092,7 +8809,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, gen_load_gpr(t0, rt); gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn = "dmtc0"; break; @@ -9112,7 +8828,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rt); gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn = "mthc0"; break; @@ -9246,7 +8961,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { gen_reserved_instruction(ctx); - goto out; + return; } if (cc != 0) { @@ -9286,7 +9001,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); tcg_gen_nand_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9297,7 +9011,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); tcg_gen_or_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9312,7 +9025,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); tcg_gen_nand_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9327,7 +9039,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_or_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); tcg_gen_or_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9337,12 +9048,10 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } ctx->btarget = btarget; ctx->hflags |= MIPS_HFLAG_BDS32; - out: - tcg_temp_free_i32(t0); } /* R6 CP1 Branches */ @@ -9359,7 +9068,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); - goto out; + return; } gen_load_fpr64(ctx, t0, ft); @@ -9379,7 +9088,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } tcg_gen_trunc_i64_tl(bcond, t0); @@ -9394,9 +9103,6 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, ctx->hflags |= MIPS_HFLAG_BDS32; break; } - -out: - tcg_temp_free_i64(t0); } /* Coprocessor 1 (FPU) */ @@ -9624,7 +9330,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) gen_load_fpr32(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); break; @@ -9635,7 +9340,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fs); - tcg_temp_free_i32(fp0); } break; case OPC_CFC1: @@ -9665,7 +9369,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) gen_load_fpr32h(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); break; @@ -9676,17 +9379,13 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32h(ctx, fp0, fs); - tcg_temp_free_i32(fp0); } break; default: MIPS_INVAL("cp1 move"); gen_reserved_instruction(ctx); - goto out; + return; } - - out: - tcg_temp_free(t0); } static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) @@ -9710,7 +9409,6 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) t0 = tcg_temp_new_i32(); tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - tcg_temp_free_i32(t0); gen_load_gpr(cpu_gpr[rd], rs); gen_set_label(l1); } @@ -9733,7 +9431,6 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, gen_load_fpr32(ctx, t0, fs); gen_store_fpr32(ctx, t0, fd); gen_set_label(l1); - tcg_temp_free_i32(t0); } static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, @@ -9752,11 +9449,9 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - tcg_temp_free_i32(t0); fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } @@ -9784,14 +9479,13 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, tcg_gen_brcondi_i32(cond, t0, 0, l2); gen_load_fpr32h(ctx, t0, fs); gen_store_fpr32h(ctx, t0, fd); - tcg_temp_free_i32(t0); gen_set_label(l2); } static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, int fs) { - TCGv_i32 t1 = tcg_const_i32(0); + TCGv_i32 t1 = tcg_constant_i32(0); TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); @@ -9819,16 +9513,12 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(t1); } static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, int fs) { - TCGv_i64 t1 = tcg_const_i64(0); + TCGv_i64 t1 = tcg_constant_i64(0); TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp1 = tcg_temp_new_i64(); TCGv_i64 fp2 = tcg_temp_new_i64(); @@ -9856,10 +9546,6 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(t1); } static void gen_farith(DisasContext *ctx, enum fopcode op1, @@ -9875,9 +9561,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SUB_S: @@ -9888,9 +9572,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MUL_S: @@ -9901,9 +9583,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_DIV_S: @@ -9914,9 +9594,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SQRT_S: @@ -9926,7 +9604,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_sqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_ABS_S: @@ -9940,7 +9617,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_abs_s(fp0, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MOV_S: @@ -9949,7 +9625,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_NEG_S: @@ -9963,7 +9638,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_chs_s(fp0, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_ROUND_L_S: @@ -9978,9 +9652,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_round_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_TRUNC_L_S: @@ -9995,9 +9667,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_trunc_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CEIL_L_S: @@ -10012,9 +9682,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_ceil_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_FLOOR_L_S: @@ -10029,9 +9697,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_floor_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_ROUND_W_S: @@ -10045,7 +9711,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_round_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_TRUNC_W_S: @@ -10059,7 +9724,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_trunc_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CEIL_W_S: @@ -10073,7 +9737,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_ceil_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_FLOOR_W_S: @@ -10087,7 +9750,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_floor_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SEL_S: @@ -10118,7 +9780,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); gen_set_label(l1); } break; @@ -10133,7 +9794,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); gen_set_label(l1); } } @@ -10145,7 +9805,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_RSQRT_S: @@ -10155,7 +9814,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MADDF_S: @@ -10169,9 +9827,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp2, fd); gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } break; case OPC_MSUBF_S: @@ -10185,9 +9840,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp2, fd); gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } break; case OPC_RINT_S: @@ -10197,7 +9849,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rint_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CLASS_S: @@ -10207,7 +9858,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_class_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MIN_S: /* OPC_RECIP2_S */ @@ -10220,9 +9870,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_min_s(fp2, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RECIP2_S */ check_cp1_64bitmode(ctx); @@ -10233,9 +9880,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10249,9 +9894,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RECIP1_S */ check_cp1_64bitmode(ctx); @@ -10261,7 +9903,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip1_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10274,8 +9915,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_max_s(fp1, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RSQRT1_S */ check_cp1_64bitmode(ctx); @@ -10285,7 +9924,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10298,8 +9936,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RSQRT2_S */ check_cp1_64bitmode(ctx); @@ -10310,9 +9946,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10324,9 +9958,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_s(fp64, cpu_env, fp32); - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_W_S: @@ -10340,7 +9972,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_L_S: @@ -10355,9 +9986,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_PS_S: @@ -10370,10 +9999,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp32_0, fs); gen_load_fpr32(ctx, fp32_1, ft); tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); - tcg_temp_free_i32(fp32_1); - tcg_temp_free_i32(fp32_0); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CMP_F_S: @@ -10408,9 +10034,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SUB_D: @@ -10422,9 +10046,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MUL_D: @@ -10436,9 +10058,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_DIV_D: @@ -10450,9 +10070,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SQRT_D: @@ -10463,7 +10081,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_sqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ABS_D: @@ -10478,7 +10095,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_abs_d(fp0, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOV_D: @@ -10488,7 +10104,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_NEG_D: @@ -10503,7 +10118,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_chs_d(fp0, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ROUND_L_D: @@ -10518,7 +10132,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_round_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_TRUNC_L_D: @@ -10533,7 +10146,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_trunc_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CEIL_L_D: @@ -10548,7 +10160,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_ceil_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_FLOOR_L_D: @@ -10563,7 +10174,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_floor_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ROUND_W_D: @@ -10578,9 +10188,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_round_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_TRUNC_W_D: @@ -10595,9 +10203,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_trunc_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CEIL_W_D: @@ -10612,9 +10218,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_ceil_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_FLOOR_W_D: @@ -10629,9 +10233,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_floor_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_SEL_D: @@ -10662,7 +10264,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } break; @@ -10677,7 +10278,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } } @@ -10690,7 +10290,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT_D: @@ -10701,7 +10300,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MADDF_D: @@ -10715,9 +10313,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp2, fd); gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } break; case OPC_MSUBF_D: @@ -10731,9 +10326,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp2, fd); gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } break; case OPC_RINT_D: @@ -10743,7 +10335,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rint_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CLASS_D: @@ -10753,7 +10344,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_class_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MIN_D: /* OPC_RECIP2_D */ @@ -10765,8 +10355,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_min_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RECIP2_D */ check_cp1_64bitmode(ctx); @@ -10777,9 +10365,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10792,8 +10378,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RECIP1_D */ check_cp1_64bitmode(ctx); @@ -10803,7 +10387,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10816,8 +10399,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_max_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RSQRT1_D */ check_cp1_64bitmode(ctx); @@ -10827,7 +10408,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10840,8 +10420,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RSQRT2_D */ check_cp1_64bitmode(ctx); @@ -10852,9 +10430,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10889,9 +10465,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_d(fp32, cpu_env, fp64); - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_W_D: @@ -10906,9 +10480,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, } else { gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_L_D: @@ -10923,7 +10495,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_W: @@ -10933,7 +10504,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_w(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_D_W: @@ -10944,9 +10514,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_w(fp64, cpu_env, fp32); - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_S_L: @@ -10957,9 +10525,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_l(fp32, cpu_env, fp64); - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_D_L: @@ -10970,7 +10536,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtd_l(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_PS_PW: @@ -10981,7 +10546,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ADD_PS: @@ -10993,9 +10557,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SUB_PS: @@ -11007,9 +10569,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MUL_PS: @@ -11021,9 +10581,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ABS_PS: @@ -11034,7 +10592,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_abs_ps(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOV_PS: @@ -11044,7 +10601,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_NEG_PS: @@ -11055,7 +10611,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_chs_ps(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOVCF_PS: @@ -11074,7 +10629,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } break; @@ -11089,7 +10643,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } } @@ -11103,9 +10656,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MULR_PS: @@ -11117,9 +10668,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RECIP2_PS: @@ -11131,9 +10680,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RECIP1_PS: @@ -11144,7 +10691,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT1_PS: @@ -11155,7 +10701,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT2_PS: @@ -11167,9 +10712,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_PU: @@ -11180,7 +10723,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp0, fs); gen_helper_float_cvts_pu(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_PW_PS: @@ -11191,7 +10733,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_PL: @@ -11202,7 +10743,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_pl(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_PLL_PS: @@ -11215,8 +10755,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp1, ft); gen_store_fpr32h(ctx, fp0, fd); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PLU_PS: @@ -11229,8 +10767,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PUL_PS: @@ -11243,8 +10779,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PUU_PS: @@ -11257,8 +10791,6 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_CMP_F_PS: @@ -11316,7 +10848,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_LDXC1: @@ -11326,7 +10857,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, TCGv_i64 fp0 = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_LUXC1: @@ -11337,7 +10867,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SWXC1: @@ -11346,7 +10875,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, TCGv_i32 fp0 = tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); - tcg_temp_free_i32(fp0); } break; case OPC_SDXC1: @@ -11356,7 +10884,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); - tcg_temp_free_i64(fp0); } break; case OPC_SUXC1: @@ -11366,11 +10893,9 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, TCGv_i64 fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); - tcg_temp_free_i64(fp0); } break; } - tcg_temp_free(t0); } static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, @@ -11397,7 +10922,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); - tcg_temp_free(t0); if (cpu_is_bigendian(ctx)) { gen_load_fpr32(ctx, fp, fs); gen_load_fpr32h(ctx, fph, ft); @@ -11410,8 +10934,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_store_fpr32h(ctx, fp, fd); } gen_set_label(l2); - tcg_temp_free_i32(fp); - tcg_temp_free_i32(fph); } break; case OPC_MADD_S: @@ -11425,10 +10947,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_MADD_D: @@ -11443,10 +10962,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MADD_PS: @@ -11460,10 +10976,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MSUB_S: @@ -11477,10 +10990,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_MSUB_D: @@ -11495,10 +11005,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MSUB_PS: @@ -11512,10 +11019,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMADD_S: @@ -11529,10 +11033,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_NMADD_D: @@ -11547,10 +11048,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMADD_PS: @@ -11564,10 +11062,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMSUB_S: @@ -11581,10 +11076,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_NMSUB_D: @@ -11599,10 +11091,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMSUB_PS: @@ -11616,10 +11105,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; default: @@ -11708,7 +11194,6 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } static inline void clear_branch_hflags(DisasContext *ctx) @@ -11767,11 +11252,9 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) tcg_gen_andi_tl(t0, btarget, 0x1); tcg_gen_trunc_tl_i32(t1, t0); - tcg_temp_free(t0); tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16); tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); tcg_gen_or_i32(hflags, hflags, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); } else { @@ -11801,7 +11284,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); - goto out; + return; } /* Load needed operands and calculate btarget */ @@ -11855,13 +11338,12 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, gen_load_gpr(tbase, rt); gen_op_addr_add(ctx, btarget, tbase, toffset); - tcg_temp_free(tbase); } break; default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } if (bcond_compute == 0) { @@ -11882,7 +11364,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } /* Generating branch here as compact branches don't have delay slot */ @@ -11972,10 +11454,6 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, /* OPC_BNVC */ tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs); } - tcg_temp_free(input_overflow); - tcg_temp_free(t4); - tcg_temp_free(t3); - tcg_temp_free(t2); } else if (rs < rt && rs == 0) { /* OPC_BEQZALC, OPC_BNEZALC */ if (opc == OPC_BEQZALC) { @@ -12005,7 +11483,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, default: MIPS_INVAL("Compact conditional branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } /* Generating branch here as compact branches don't have delay slot */ @@ -12014,10 +11492,6 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, ctx->hflags |= MIPS_HFLAG_FBNSLOT; } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } void gen_addiupc(DisasContext *ctx, int rx, int imm, @@ -12037,19 +11511,15 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm, if (!is_64_bit) { tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); } - - tcg_temp_free(t0); } static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, int16_t offset) { - TCGv_i32 t0 = tcg_const_i32(op); + TCGv_i32 t0 = tcg_constant_i32(op); TCGv t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t1, base, offset); gen_helper_cache(cpu_env, t1, t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t0); } static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) @@ -12077,9 +11547,6 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd) tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); gen_store_gpr(t1, rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_sync(int stype) @@ -12183,7 +11650,6 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc, break; #endif } - tcg_temp_free(t0); } static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, @@ -12394,19 +11860,17 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, case OPC_PRECR_SRA_PH_W: check_dsp_r2(ctx); { - TCGv_i32 sa_t = tcg_const_i32(v2); + TCGv_i32 sa_t = tcg_constant_i32(v2); gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, cpu_gpr[ret]); - tcg_temp_free_i32(sa_t); break; } case OPC_PRECR_SRA_R_PH_W: check_dsp_r2(ctx); { - TCGv_i32 sa_t = tcg_const_i32(v2); + TCGv_i32 sa_t = tcg_constant_i32(v2); gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, cpu_gpr[ret]); - tcg_temp_free_i32(sa_t); break; } case OPC_PRECRQ_PH_W: @@ -12593,17 +12057,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, case OPC_PRECR_SRA_QH_PW: check_dsp_r2(ctx); { - TCGv_i32 ret_t = tcg_const_i32(ret); + TCGv_i32 ret_t = tcg_constant_i32(ret); gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); - tcg_temp_free_i32(ret_t); break; } case OPC_PRECR_SRA_R_QH_PW: check_dsp_r2(ctx); { - TCGv_i32 sa_v = tcg_const_i32(ret); + TCGv_i32 sa_v = tcg_constant_i32(ret); gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); - tcg_temp_free_i32(sa_v); break; } case OPC_PRECRQ_OB_QH: @@ -12630,9 +12092,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, @@ -12872,10 +12331,6 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, @@ -13182,10 +12637,6 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free_i32(t0); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, @@ -13322,8 +12773,6 @@ static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(val_t); } static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, @@ -13506,10 +12955,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, break; #endif } - - tcg_temp_free(t1); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, @@ -13597,7 +13042,6 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, break; #endif } - tcg_temp_free(t0); } static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, @@ -13814,10 +13258,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(v1_t); } /* End MIPSDSP functions. */ @@ -14668,9 +14108,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t1, rs); gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); break; } default: /* Invalid */ @@ -14940,9 +14377,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t1, rs); gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); break; } default: /* Invalid */ @@ -15169,8 +14603,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); gen_helper_fork(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case OPC_YIELD: @@ -15181,7 +14613,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) gen_load_gpr(t0, rs); gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; default: @@ -15424,7 +14855,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } #endif /* !CONFIG_USER_ONLY */ break; @@ -15872,7 +15302,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rs); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); - tcg_temp_free(t0); } #else gen_reserved_instruction(ctx); diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c index 96f483418e..a510da406c 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -30,10 +30,6 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) tcg_gen_shli_tl(t0, t0, sa + 1); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - - tcg_temp_free(t1); - tcg_temp_free(t0); - return true; } @@ -54,8 +50,5 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa) gen_load_gpr(t1, rt); tcg_gen_shli_tl(t0, t0, sa + 1); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); - return true; } diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index 4e479c2d10..3a45a1bfea 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_r *a, gen_load_gpr_hi(ax, a->rs); gen_load_gpr_hi(bx, a->rt); gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } @@ -247,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a, return true; } - c0 = tcg_const_tl(0); - c1 = tcg_const_tl(0xffffffff); + c0 = tcg_constant_tl(0); + c1 = tcg_constant_tl(0xffffffff); ax = tcg_temp_new_i64(); bx = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); @@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a, tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); } - - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); - tcg_temp_free(bx); - tcg_temp_free(ax); - tcg_temp_free(c1); - tcg_temp_free(c0); - return true; } @@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_addi_i64(addr, addr, 8); tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); gen_store_gpr_hi(t0, a->rt); - - tcg_temp_free(t0); - tcg_temp_free(addr); - return true; } @@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); - - tcg_temp_free(addr); - tcg_temp_free(t0); - return true; } @@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a) gen_load_gpr_hi(t0, a->rs); /* a1 */ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); - - tcg_temp_free(t0); - tcg_temp_free(b0); - tcg_temp_free(a0); - return true; } @@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen) tcg_gen_shri_i64(bx, bx, wlen); tcg_gen_shri_i64(ax, ax, wlen); } - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } @@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a) gen_load_gpr(ax, a->rs); gen_load_gpr(bx, a->rt); gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } @@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a) gen_load_gpr_hi(ax, a->rs); gen_load_gpr_hi(bx, a->rt); gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } @@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a) tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); - - tcg_temp_free(ax); - return true; } diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c index a7d241e4e7..804672f84c 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -49,10 +49,6 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, gen_helper_mult_acc(t0, cpu_env, t0, t1); gen_store_gpr(t0, a->rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h index 177d720864..767bba4b7b 100644 --- a/target/nios2/cpu-param.h +++ b/target/nios2/cpu-param.h @@ -16,6 +16,5 @@ #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -#define NB_MMU_MODES 2 #endif diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index cff30823da..bc5cbf81c2 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -23,7 +23,7 @@ #include "qapi/error.h" #include "cpu.h" #include "exec/log.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "hw/qdev-properties.h" static void nios2_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index f76e8588c5..3738774976 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -23,7 +23,8 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" +#include "gdbstub/helpers.h" #include "semihosting/syscalls.h" #include "semihosting/softmmu-uaccess.h" #include "qemu/log.h" diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 73be699f36..3f08207485 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -12,6 +12,5 @@ #define TARGET_PAGE_BITS 13 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define NB_MMU_MODES 3 #endif diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index 095bf76c12..d1074a0581 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index c31c6f12c4..3887812810 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #ifndef CONFIG_USER_ONLY #include "hw/loader.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 0b8afdbacf..603c26715e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -22,7 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index ea377b7d06..0a0416e0a8 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -32,6 +32,5 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #define TARGET_PAGE_BITS 12 -#define NB_MMU_MODES 10 #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d62ffe8a6f..0ce2e3c91d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "disas/dis-asm.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "kvm_ppc.h" #include "sysemu/cpus.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 1a0b9ca82c..d2bc1d7c53 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "internal.h" static int ppc_gdb_register_len_apple(int n) diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index 42f2cd04a1..d900e13cad 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -177,7 +177,7 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn) void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) { - TCGv_i32 t_sprn = tcg_const_i32(sprn); + TCGv_i32 t_sprn = tcg_constant_i32(sprn); gen_icount_io_start(ctx); gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); @@ -210,7 +210,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t_sprn = tcg_const_i32(sprn); + TCGv_i32 t_sprn = tcg_constant_i32(sprn); gen_icount_io_start(ctx); gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index df324fc7ff..9d05357d03 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -263,8 +263,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) * faulting instruction */ gen_update_nip(ctx, ctx->cia); - t0 = tcg_const_i32(excp); - t1 = tcg_const_i32(error); + t0 = tcg_constant_i32(excp); + t1 = tcg_constant_i32(error); gen_helper_raise_exception_err(cpu_env, t0, t1); ctx->base.is_jmp = DISAS_NORETURN; } @@ -278,7 +278,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp) * faulting instruction */ gen_update_nip(ctx, ctx->cia); - t0 = tcg_const_i32(excp); + t0 = tcg_constant_i32(excp); gen_helper_raise_exception(cpu_env, t0); ctx->base.is_jmp = DISAS_NORETURN; } @@ -289,7 +289,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp, TCGv_i32 t0; gen_update_nip(ctx, nip); - t0 = tcg_const_i32(excp); + t0 = tcg_constant_i32(excp); gen_helper_raise_exception(cpu_env, t0); ctx->base.is_jmp = DISAS_NORETURN; } @@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn) static void spr_load_dump_spr(int sprn) { #ifdef PPC_DUMP_SPR_ACCESSES - TCGv_i32 t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_constant_i32(sprn); gen_helper_load_dump_spr(cpu_env, t0); #endif } @@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn) static void spr_store_dump_spr(int sprn) { #ifdef PPC_DUMP_SPR_ACCESSES - TCGv_i32 t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_constant_i32(sprn); gen_helper_store_dump_spr(cpu_env, t0); #endif } @@ -672,25 +672,25 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); } void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); } void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); } void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); } @@ -712,25 +712,25 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); } void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); } void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); } void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); } @@ -1040,13 +1040,15 @@ void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_constant_i32(sprn); gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); } + void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) { gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); } + void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) { gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); @@ -1080,9 +1082,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, int bit, int sprn, int cause) { - TCGv_i32 t1 = tcg_const_i32(bit); - TCGv_i32 t2 = tcg_const_i32(sprn); - TCGv_i32 t3 = tcg_const_i32(cause); + TCGv_i32 t1 = tcg_constant_i32(bit); + TCGv_i32 t2 = tcg_constant_i32(sprn); + TCGv_i32 t3 = tcg_constant_i32(cause); gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); } @@ -1090,9 +1092,9 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, int bit, int sprn, int cause) { - TCGv_i32 t1 = tcg_const_i32(bit); - TCGv_i32 t2 = tcg_const_i32(sprn); - TCGv_i32 t3 = tcg_const_i32(cause); + TCGv_i32 t1 = tcg_constant_i32(bit); + TCGv_i32 t2 = tcg_constant_i32(sprn); + TCGv_i32 t3 = tcg_constant_i32(cause); gen_helper_msr_facility_check(cpu_env, t1, t2, t3); } @@ -1388,7 +1390,7 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) { - TCGv t0 = tcg_const_tl(arg1); + TCGv t0 = tcg_constant_tl(arg1); gen_op_cmp(arg0, t0, s, crf); } @@ -1409,7 +1411,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) { - TCGv t0 = tcg_const_tl(arg1); + TCGv t0 = tcg_constant_tl(arg1); gen_op_cmp32(arg0, t0, s, crf); } @@ -1476,7 +1478,7 @@ static void gen_isel(DisasContext *ctx) tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); tcg_gen_andi_tl(t0, t0, mask); - zr = tcg_const_tl(0); + zr = tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, cpu_gpr[rB(ctx->opcode)]); @@ -1568,7 +1570,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, tcg_gen_mov_tl(ca32, ca); } } else { - TCGv zero = tcg_const_tl(0); + TCGv zero = tcg_constant_tl(0); if (add_ca) { tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); @@ -1609,7 +1611,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ add_ca, compute_ca, compute_ov) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ - TCGv t0 = tcg_const_tl(const_val); \ + TCGv t0 = tcg_constant_tl(const_val); \ gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ cpu_gpr[rA(ctx->opcode)], t0, \ ca, glue(ca, 32), \ @@ -1636,7 +1638,7 @@ GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) /* addic addic.*/ static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) { - TCGv c = tcg_const_tl(SIMM(ctx->opcode)); + TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); } @@ -1709,7 +1711,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); #define GEN_DIVE(name, hlpr, compute_ov) \ static void gen_##name(DisasContext *ctx) \ { \ - TCGv_i32 t0 = tcg_const_i32(compute_ov); \ + TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ @@ -1802,8 +1804,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, tcg_gen_rem_i32(t3, t0, t1); tcg_gen_ext_i32_tl(ret, t3); } else { - TCGv_i32 t2 = tcg_const_i32(1); - TCGv_i32 t3 = tcg_const_i32(0); + TCGv_i32 t2 = tcg_constant_i32(1); + TCGv_i32 t3 = tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); tcg_gen_remu_i32(t3, t0, t1); tcg_gen_extu_i32_tl(ret, t3); @@ -1842,8 +1844,8 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_i64(ret, t0, t1); } else { - TCGv_i64 t2 = tcg_const_i64(1); - TCGv_i64 t3 = tcg_const_i64(0); + TCGv_i64 t2 = tcg_constant_i64(1); + TCGv_i64 t3 = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); tcg_gen_remu_i64(ret, t0, t1); } @@ -2038,7 +2040,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, } else if (add_ca) { TCGv zero, inv1 = tcg_temp_new(); tcg_gen_not_tl(inv1, arg1); - zero = tcg_const_tl(0); + zero = tcg_constant_tl(0); tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); @@ -2083,7 +2085,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ add_ca, compute_ca, compute_ov) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ - TCGv t0 = tcg_const_tl(const_val); \ + TCGv t0 = tcg_constant_tl(const_val); \ gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ cpu_gpr[rA(ctx->opcode)], t0, \ add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ @@ -2107,7 +2109,7 @@ GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) /* subfic */ static void gen_subfic(DisasContext *ctx) { - TCGv c = tcg_const_tl(SIMM(ctx->opcode)); + TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], c, 0, 1, 0, 0); } @@ -2115,7 +2117,7 @@ static void gen_subfic(DisasContext *ctx) /* neg neg. nego nego. */ static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) { - TCGv zero = tcg_const_tl(0); + TCGv zero = tcg_constant_tl(0); gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], zero, 0, 0, compute_ov, Rc(ctx->opcode)); } @@ -2214,7 +2216,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) static void gen_pause(DisasContext *ctx) { - TCGv_i32 t0 = tcg_const_i32(0); + TCGv_i32 t0 = tcg_constant_i32(0); tcg_gen_st_i32(t0, cpu_env, -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); @@ -3256,7 +3258,7 @@ static void gen_lmw(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); - t1 = tcg_const_i32(rD(ctx->opcode)); + t1 = tcg_constant_i32(rD(ctx->opcode)); gen_addr_imm_index(ctx, t0, 0); gen_helper_lmw(cpu_env, t0, t1); } @@ -3273,7 +3275,7 @@ static void gen_stmw(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); - t1 = tcg_const_i32(rS(ctx->opcode)); + t1 = tcg_constant_i32(rS(ctx->opcode)); gen_addr_imm_index(ctx, t0, 0); gen_helper_stmw(cpu_env, t0, t1); } @@ -3311,8 +3313,8 @@ static void gen_lswi(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); gen_addr_register(ctx, t0); - t1 = tcg_const_i32(nb); - t2 = tcg_const_i32(start); + t1 = tcg_constant_i32(nb); + t2 = tcg_constant_i32(start); gen_helper_lsw(cpu_env, t0, t1, t2); } @@ -3329,9 +3331,9 @@ static void gen_lswx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_INT); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - t1 = tcg_const_i32(rD(ctx->opcode)); - t2 = tcg_const_i32(rA(ctx->opcode)); - t3 = tcg_const_i32(rB(ctx->opcode)); + t1 = tcg_constant_i32(rD(ctx->opcode)); + t2 = tcg_constant_i32(rA(ctx->opcode)); + t3 = tcg_constant_i32(rB(ctx->opcode)); gen_helper_lswx(cpu_env, t0, t1, t2, t3); } @@ -3352,8 +3354,8 @@ static void gen_stswi(DisasContext *ctx) if (nb == 0) { nb = 32; } - t1 = tcg_const_i32(nb); - t2 = tcg_const_i32(rS(ctx->opcode)); + t1 = tcg_constant_i32(nb); + t2 = tcg_constant_i32(rS(ctx->opcode)); gen_helper_stsw(cpu_env, t0, t1, t2); } @@ -3373,7 +3375,7 @@ static void gen_stswx(DisasContext *ctx) t1 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t1, cpu_xer); tcg_gen_andi_i32(t1, t1, 0x7F); - t2 = tcg_const_i32(rS(ctx->opcode)); + t2 = tcg_constant_i32(rS(ctx->opcode)); gen_helper_stsw(cpu_env, t0, t1, t2); } @@ -3943,7 +3945,7 @@ static void gen_wait(DisasContext *ctx) * to occur. */ if (wc == 0) { - TCGv_i32 t0 = tcg_const_i32(1); + TCGv_i32 t0 = tcg_constant_i32(1); tcg_gen_st_i32(t0, cpu_env, -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); /* Stop translation, as the CPU is supposed to sleep from now */ @@ -3989,7 +3991,7 @@ static void gen_doze(DisasContext *ctx) TCGv_i32 t; CHK_HV(ctx); - t = tcg_const_i32(PPC_PM_DOZE); + t = tcg_constant_i32(PPC_PM_DOZE); gen_helper_pminsn(cpu_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -4004,7 +4006,7 @@ static void gen_nap(DisasContext *ctx) TCGv_i32 t; CHK_HV(ctx); - t = tcg_const_i32(PPC_PM_NAP); + t = tcg_constant_i32(PPC_PM_NAP); gen_helper_pminsn(cpu_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -4019,7 +4021,7 @@ static void gen_stop(DisasContext *ctx) TCGv_i32 t; CHK_HV(ctx); - t = tcg_const_i32(PPC_PM_STOP); + t = tcg_constant_i32(PPC_PM_STOP); gen_helper_pminsn(cpu_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -4034,7 +4036,7 @@ static void gen_sleep(DisasContext *ctx) TCGv_i32 t; CHK_HV(ctx); - t = tcg_const_i32(PPC_PM_SLEEP); + t = tcg_constant_i32(PPC_PM_SLEEP); gen_helper_pminsn(cpu_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -4049,7 +4051,7 @@ static void gen_rvwinkle(DisasContext *ctx) TCGv_i32 t; CHK_HV(ctx); - t = tcg_const_i32(PPC_PM_RVWINKLE); + t = tcg_constant_i32(PPC_PM_RVWINKLE); gen_helper_pminsn(cpu_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -4506,7 +4508,7 @@ static void gen_tw(DisasContext *ctx) if (check_unconditional_trap(ctx)) { return; } - t0 = tcg_const_i32(TO(ctx->opcode)); + t0 = tcg_constant_i32(TO(ctx->opcode)); gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); } @@ -4520,8 +4522,8 @@ static void gen_twi(DisasContext *ctx) if (check_unconditional_trap(ctx)) { return; } - t0 = tcg_const_tl(SIMM(ctx->opcode)); - t1 = tcg_const_i32(TO(ctx->opcode)); + t0 = tcg_constant_tl(SIMM(ctx->opcode)); + t1 = tcg_constant_i32(TO(ctx->opcode)); gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); } @@ -4534,7 +4536,7 @@ static void gen_td(DisasContext *ctx) if (check_unconditional_trap(ctx)) { return; } - t0 = tcg_const_i32(TO(ctx->opcode)); + t0 = tcg_constant_i32(TO(ctx->opcode)); gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); } @@ -4548,8 +4550,8 @@ static void gen_tdi(DisasContext *ctx) if (check_unconditional_trap(ctx)) { return; } - t0 = tcg_const_tl(SIMM(ctx->opcode)); - t1 = tcg_const_i32(TO(ctx->opcode)); + t0 = tcg_constant_tl(SIMM(ctx->opcode)); + t1 = tcg_constant_i32(TO(ctx->opcode)); gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); } #endif @@ -5026,7 +5028,7 @@ static void gen_dcbz(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_CACHE); tcgv_addr = tcg_temp_new(); - tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); + tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); gen_addr_reg_index(ctx, tcgv_addr); gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); } @@ -5039,7 +5041,7 @@ static void gen_dcbzep(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_CACHE); tcgv_addr = tcg_temp_new(); - tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); + tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); gen_addr_reg_index(ctx, tcgv_addr); gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); } @@ -5114,7 +5116,7 @@ static void gen_mfsr(DisasContext *ctx) TCGv t0; CHK_SV(ctx); - t0 = tcg_const_tl(SR(ctx->opcode)); + t0 = tcg_constant_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5143,7 +5145,7 @@ static void gen_mtsr(DisasContext *ctx) TCGv t0; CHK_SV(ctx); - t0 = tcg_const_tl(SR(ctx->opcode)); + t0 = tcg_constant_tl(SR(ctx->opcode)); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5175,7 +5177,7 @@ static void gen_mfsr_64b(DisasContext *ctx) TCGv t0; CHK_SV(ctx); - t0 = tcg_const_tl(SR(ctx->opcode)); + t0 = tcg_constant_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5204,7 +5206,7 @@ static void gen_mtsr_64b(DisasContext *ctx) TCGv t0; CHK_SV(ctx); - t0 = tcg_const_tl(SR(ctx->opcode)); + t0 = tcg_constant_tl(SR(ctx->opcode)); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5558,7 +5560,7 @@ static void gen_mfdcr(DisasContext *ctx) TCGv dcrn; CHK_SV(ctx); - dcrn = tcg_const_tl(SPR(ctx->opcode)); + dcrn = tcg_constant_tl(SPR(ctx->opcode)); gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5572,7 +5574,7 @@ static void gen_mtdcr(DisasContext *ctx) TCGv dcrn; CHK_SV(ctx); - dcrn = tcg_const_tl(SPR(ctx->opcode)); + dcrn = tcg_constant_tl(SPR(ctx->opcode)); gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5793,7 +5795,7 @@ static void gen_tlbre_440(DisasContext *ctx) case 1: case 2: { - TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); + TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, t0, cpu_gpr[rA(ctx->opcode)]); } @@ -5839,7 +5841,7 @@ static void gen_tlbwe_440(DisasContext *ctx) case 1: case 2: { - TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); + TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); } @@ -5875,12 +5877,10 @@ static void gen_tlbsx_booke206(DisasContext *ctx) CHK_SV(ctx); if (rA(ctx->opcode)) { t0 = tcg_temp_new(); - tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); + tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); } else { - t0 = tcg_const_tl(0); + t0 = cpu_gpr[rB(ctx->opcode)]; } - - tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); gen_helper_booke206_tlbsx(cpu_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5983,7 +5983,7 @@ static void gen_wrteei(DisasContext *ctx) /* dlmzb */ static void gen_dlmzb(DisasContext *ctx) { - TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); + TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 20ea484c3d..02d86b77a8 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a) static bool trans_ADDG6S(DisasContext *ctx, arg_X *a) { - const uint64_t carry_bits = 0x1111111111111111ULL; - TCGv t0, t1, carry, zero = tcg_constant_tl(0); + const target_ulong carry_bits = (target_ulong)-1 / 0xf; + TCGv in1, in2, carryl, carryh, tmp; + TCGv zero = tcg_constant_tl(0); REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206); - t0 = tcg_temp_new(); - t1 = tcg_const_tl(0); - carry = tcg_const_tl(0); - - for (int i = 0; i < 16; i++) { - tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4); - tcg_gen_andi_tl(t0, t0, 0xf); - tcg_gen_add_tl(t1, t1, t0); - - tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4); - tcg_gen_andi_tl(t0, t0, 0xf); - tcg_gen_add_tl(t1, t1, t0); - - tcg_gen_andi_tl(t1, t1, 0x10); - tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero); - - tcg_gen_shli_tl(t0, t1, i * 4); - tcg_gen_or_tl(carry, carry, t0); - } - - tcg_gen_xori_tl(carry, carry, (target_long)carry_bits); - tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6); + in1 = cpu_gpr[a->ra]; + in2 = cpu_gpr[a->rb]; + tmp = tcg_temp_new(); + carryl = tcg_temp_new(); + carryh = tcg_temp_new(); + + /* Addition with carry. */ + tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero); + /* Addition without carry. */ + tcg_gen_xor_tl(tmp, in1, in2); + /* Difference between the two is carry in to each bit. */ + tcg_gen_xor_tl(carryl, carryl, tmp); + + /* + * The carry-out that we're looking for is the carry-in to + * the next nibble. Shift the double-word down one nibble, + * which puts all of the bits back into one word. + */ + tcg_gen_extract2_tl(carryl, carryl, carryh, 4); + + /* Invert, isolate the carry bits, and produce 6's. */ + tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl); + tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6); return true; } diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index d5d88e7d49..57d8437851 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx) t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); - crf = tcg_const_i32(crfD(ctx->opcode)); + crf = tcg_constant_i32(crfD(ctx->opcode)); get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); gen_helper_fcmpo(cpu_env, t0, t1, crf); @@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx) t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); - crf = tcg_const_i32(crfD(ctx->opcode)); + crf = tcg_constant_i32(crfD(ctx->opcode)); get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); gen_helper_fcmpu(cpu_env, t0, t1, crf); @@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx) tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS)); /* FEX and VX need to be updated, so don't set fpscr directly */ - tmask = tcg_const_i32(1 << nibble); + tmask = tcg_constant_i32(1 << nibble); gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); } @@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx) crb = 31 - crbD(ctx->opcode); gen_reset_fpstatus(); if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { - TCGv_i32 t0; - t0 = tcg_const_i32(crb); - gen_helper_fpscr_clrbit(cpu_env, t0); + gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb)); } if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx) crb = 31 - crbD(ctx->opcode); /* XXX: we pretend we can only do IEEE floating-point computations */ if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { - TCGv_i32 t0; - t0 = tcg_const_i32(crb); - gen_helper_fpscr_setbit(cpu_env, t0); + gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb)); } if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } - if (l) { - t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); + if (!l) { + t0 = tcg_constant_i32(flm << (w * 8)); + } else if (ctx->insns_flags2 & PPC2_ISA205) { + t0 = tcg_constant_i32(0xffff); } else { - t0 = tcg_const_i32(flm << (w * 8)); + t0 = tcg_constant_i32(0xff); } t1 = tcg_temp_new_i64(); get_fpr(t1, rB(ctx->opcode)); @@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx) return; } sh = (8 * w) + 7 - bf; - t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); - t1 = tcg_const_i32(1 << sh); + t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); + t1 = tcg_constant_i32(1 << sh); gen_helper_store_fpscr(cpu_env, t0, t1); if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 05ba9c9492..112233b541 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -171,53 +171,56 @@ static void gen_mtvscr(DisasContext *ctx) gen_helper_mtvscr(cpu_env, val); } +static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry) +{ + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; + TCGv_i64 avr; + TCGv_i64 ten, z; + + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + avr = tcg_temp_new_i64(); + ten = tcg_constant_i64(10); + z = tcg_constant_i64(0); + + if (add_cin) { + get_avr64(avr, rA(ctx->opcode), false); + tcg_gen_mulu2_i64(t0, t1, avr, ten); + get_avr64(avr, rB(ctx->opcode), false); + tcg_gen_andi_i64(t2, avr, 0xF); + tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); + set_avr64(rD(ctx->opcode), avr, false); + } else { + get_avr64(avr, rA(ctx->opcode), false); + tcg_gen_mulu2_i64(avr, t2, avr, ten); + set_avr64(rD(ctx->opcode), avr, false); + } + + if (ret_carry) { + get_avr64(avr, rA(ctx->opcode), true); + tcg_gen_mulu2_i64(t0, t1, avr, ten); + tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); + set_avr64(rD(ctx->opcode), avr, false); + set_avr64(rD(ctx->opcode), z, true); + } else { + get_avr64(avr, rA(ctx->opcode), true); + tcg_gen_mul_i64(t0, avr, ten); + tcg_gen_add_i64(avr, t0, t2); + set_avr64(rD(ctx->opcode), avr, true); + } +} + #define GEN_VX_VMUL10(name, add_cin, ret_carry) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv_i64 t0; \ - TCGv_i64 t1; \ - TCGv_i64 t2; \ - TCGv_i64 avr; \ - TCGv_i64 ten, z; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - t0 = tcg_temp_new_i64(); \ - t1 = tcg_temp_new_i64(); \ - t2 = tcg_temp_new_i64(); \ - avr = tcg_temp_new_i64(); \ - ten = tcg_const_i64(10); \ - z = tcg_const_i64(0); \ - \ - if (add_cin) { \ - get_avr64(avr, rA(ctx->opcode), false); \ - tcg_gen_mulu2_i64(t0, t1, avr, ten); \ - get_avr64(avr, rB(ctx->opcode), false); \ - tcg_gen_andi_i64(t2, avr, 0xF); \ - tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \ - set_avr64(rD(ctx->opcode), avr, false); \ - } else { \ - get_avr64(avr, rA(ctx->opcode), false); \ - tcg_gen_mulu2_i64(avr, t2, avr, ten); \ - set_avr64(rD(ctx->opcode), avr, false); \ - } \ - \ - if (ret_carry) { \ - get_avr64(avr, rA(ctx->opcode), true); \ - tcg_gen_mulu2_i64(t0, t1, avr, ten); \ - tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \ - set_avr64(rD(ctx->opcode), avr, false); \ - set_avr64(rD(ctx->opcode), z, true); \ - } else { \ - get_avr64(avr, rA(ctx->opcode), true); \ - tcg_gen_mul_i64(t0, avr, ten); \ - tcg_gen_add_i64(avr, t0, t2); \ - set_avr64(rD(ctx->opcode), avr, true); \ - } \ -} \ + static void glue(gen_, name)(DisasContext *ctx) \ + { gen_vx_vmul10(ctx, add_cin, ret_carry); } GEN_VX_VMUL10(vmul10uq, 0, 0); GEN_VX_VMUL10(vmul10euq, 1, 0); @@ -903,7 +906,6 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right, hi = tcg_temp_new_i64(); lo = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); - t1 = tcg_const_i64(0); get_avr64(lo, a->vra, false); get_avr64(hi, a->vra, true); @@ -914,7 +916,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right, if (right) { tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo); if (alg) { + t1 = tcg_temp_new_i64(); tcg_gen_sari_i64(t1, lo, 63); + } else { + t1 = zero; } tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi); } else { @@ -1619,7 +1624,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ + uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \ rb = gen_avr_ptr(rB(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(cpu_env, rd, rb, uimm); \ @@ -1960,7 +1965,7 @@ static void gen_vsldoi(DisasContext *ctx) ra = gen_avr_ptr(rA(ctx->opcode)); rb = gen_avr_ptr(rB(ctx->opcode)); rd = gen_avr_ptr(rD(ctx->opcode)); - sh = tcg_const_i32(VSH(ctx->opcode)); + sh = tcg_constant_i32(VSH(ctx->opcode)); gen_helper_vsldoi(rd, ra, rb, sh); } @@ -2231,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a) static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece) { - TCGv_i64 rt, vrb, mask; - rt = tcg_const_i64(0); - vrb = tcg_temp_new_i64(); + TCGv_i64 r[2], mask; + + r[0] = tcg_temp_new_i64(); + r[1] = tcg_temp_new_i64(); mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1))); for (int i = 0; i < 2; i++) { - get_avr64(vrb, a->vrb, i); + get_avr64(r[i], a->vrb, i); if (a->mp) { - tcg_gen_and_i64(vrb, mask, vrb); + tcg_gen_and_i64(r[i], mask, r[i]); } else { - tcg_gen_andc_i64(vrb, mask, vrb); + tcg_gen_andc_i64(r[i], mask, r[i]); } - tcg_gen_ctpop_i64(vrb, vrb); - tcg_gen_add_i64(rt, rt, vrb); + tcg_gen_ctpop_i64(r[i], r[i]); } - tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece); - tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt); + tcg_gen_add_i64(r[0], r[0], r[1]); + tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece); + tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]); return true; } @@ -2569,7 +2575,7 @@ static void gen_##op(DisasContext *ctx) \ rb = gen_avr_ptr(rB(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \ \ - ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ + ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \ \ gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ } @@ -2588,7 +2594,7 @@ static void gen_##op(DisasContext *ctx) \ rb = gen_avr_ptr(rB(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \ \ - ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ + ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \ \ gen_helper_##op(cpu_crf[6], rd, rb, ps); \ } @@ -2720,7 +2726,7 @@ static void gen_##op(DisasContext *ctx) \ } \ ra = gen_avr_ptr(rA(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \ - st_six = tcg_const_i32(rB(ctx->opcode)); \ + st_six = tcg_constant_i32(rB(ctx->opcode)); \ gen_helper_##op(rd, ra, st_six); \ } diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 6e63403727..0f5b0056f1 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx) static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, TCGv_i64 inh, TCGv_i64 inl) { - TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF); + TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF); TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); @@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a) REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_VSX(ctx); - ro = tcg_const_i32(a->rc); + ro = tcg_constant_i32(a->rc); xt = gen_avr_ptr(a->rt); xb = gen_avr_ptr(a->rb); @@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - opc = tcg_const_i32(ctx->opcode); \ + opc = tcg_constant_i32(ctx->opcode); \ gen_helper_##name(cpu_env, opc); \ } @@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - opc = tcg_const_i32(ctx->opcode); \ + opc = tcg_constant_i32(ctx->opcode); \ xa = gen_vsr_ptr(xA(ctx->opcode)); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \ gen_helper_##name(cpu_env, opc, xa, xb); \ @@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - opc = tcg_const_i32(ctx->opcode); \ + opc = tcg_constant_i32(ctx->opcode); \ xb = gen_vsr_ptr(xB(ctx->opcode)); \ gen_helper_##name(cpu_env, opc, xb); \ } @@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - opc = tcg_const_i32(ctx->opcode); \ + opc = tcg_constant_i32(ctx->opcode); \ xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ @@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - opc = tcg_const_i32(ctx->opcode); \ + opc = tcg_constant_i32(ctx->opcode); \ xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ gen_helper_##name(cpu_env, opc, xt, xb); \ @@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - opc = tcg_const_i32(ctx->opcode); \ + opc = tcg_constant_i32(ctx->opcode); \ xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \ xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \ gen_helper_##name(cpu_env, opc, xa, xb); \ @@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx) exp = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); - zr = tcg_const_i64(0); - nan = tcg_const_i64(2047); + zr = tcg_constant_i64(0); + nan = tcg_constant_i64(2047); get_cpu_vsr(t1, xB(ctx->opcode), true); tcg_gen_extract_i64(exp, t1, 52, 11); @@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx) get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false); exp = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); - zr = tcg_const_i64(0); - nan = tcg_const_i64(32767); + zr = tcg_constant_i64(0); + nan = tcg_constant_i64(32767); tcg_gen_extract_i64(exp, xbh, 48, 15); tcg_gen_movi_i64(t0, 0x0001000000000000); @@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx) get_cpu_vsr(xbl, xB(ctx->opcode), false); exp = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); - zr = tcg_const_i64(0); - nan = tcg_const_i64(2047); + zr = tcg_constant_i64(0); + nan = tcg_constant_i64(2047); tcg_gen_extract_i64(exp, xbh, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); @@ -2449,7 +2449,8 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c, TCGv_i64 conj, disj; conj = tcg_temp_new_i64(); - disj = tcg_const_i64(0); + disj = tcg_temp_new_i64(); + tcg_gen_movi_i64(disj, 0); /* Iterate over set bits from the least to the most significant bit */ while (imm) { @@ -2492,8 +2493,9 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b, int bit; TCGv_vec disj, conj; - disj = tcg_const_zeros_vec_matching(t); conj = tcg_temp_new_vec_matching(t); + disj = tcg_temp_new_vec_matching(t); + tcg_gen_dupi_vec(vece, disj, 0); /* Iterate over set bits from the least to the most significant bit */ while (imm) { @@ -2546,7 +2548,7 @@ static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a) /* Equivalent functions that can be implemented with a single gen_gvec */ switch (a->imm) { - case 0b00000000: /* true */ + case 0b00000000: /* false */ set_cpu_vsr(a->xt, tcg_constant_i64(0), true); set_cpu_vsr(a->xt, tcg_constant_i64(0), false); break; diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index ebaf26d26d..b2a9396dec 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -27,6 +27,5 @@ * - S mode HLV/HLVX/HSV 0b101 * - M mode HLV/HLVX/HSV 0b111 */ -#define NB_MMU_MODES 8 #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..d522efc0b6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "time_helper.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "sysemu/cpu-timers.h" #include "qemu/guest-random.h" #include "qapi/error.h" diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 6048541606..840d1ec5c6 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "cpu.h" struct TypeSize { diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index b156ad1ca0..521d669bdf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -25,6 +25,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define NB_MMU_MODES 1 - #endif diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c index 7eb2059a84..d7e0e6689b 100644 --- a/target/rx/gdbstub.c +++ b/target/rx/gdbstub.c @@ -17,7 +17,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/rx/translate.c b/target/rx/translate.c index 6624414739..70fad98e93 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) { TCGv imm, mem; - imm = tcg_const_i32(a->imm); + imm = tcg_constant_i32(a->imm); mem = tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); rx_gen_st(a->sz, imm, mem); @@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm) { TCGv z; TCGv _imm; - z = tcg_const_i32(0); - _imm = tcg_const_i32(imm); + z = tcg_constant_i32(0); + _imm = tcg_constant_i32(imm); tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, _imm, cpu_regs[rd]); } @@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) { - TCGv imm = tcg_const_i32(src2); + TCGv imm = tcg_constant_i32(src2); opr(cpu_regs[dst], cpu_regs[src], imm); } @@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) /* ret = arg1 + arg2 + psw_c */ static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv z; - z = tcg_const_i32(0); + TCGv z = tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - tcg_gen_xor_i32(z, arg1, arg2); - tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_mov_i32(ret, cpu_psw_s); } @@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) /* ret = arg1 + arg2 */ static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv z; - z = tcg_const_i32(0); + TCGv z = tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - tcg_gen_xor_i32(z, arg1, arg2); - tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_mov_i32(ret, cpu_psw_s); } @@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) /* ret = arg1 - arg2 */ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv temp; tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - temp = tcg_temp_new_i32(); - tcg_gen_xor_i32(temp, arg1, arg2); - tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); /* CMP not required return */ if (ret) { tcg_gen_mov_i32(ret, cpu_psw_s); } } + static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) { rx_sub(NULL, arg1, arg2); } + /* ret = arg1 - arg2 - !psw_c */ /* -> ret = arg1 + ~arg2 + psw_c */ static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) @@ -1126,21 +1124,11 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) return true; } -static void rx_abs(TCGv ret, TCGv arg1) -{ - TCGv neg; - TCGv zero; - neg = tcg_temp_new(); - zero = tcg_const_i32(0); - tcg_gen_neg_i32(neg, arg1); - tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1); -} - /* abs rd */ /* abs rs, rd */ static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) { - rx_gen_op_rr(rx_abs, a->rd, a->rs); + rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs); return true; } @@ -1200,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) /* emul #imm, rd */ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) { - TCGv imm = tcg_const_i32(a->imm); + TCGv imm = tcg_constant_i32(a->imm); if (a->rd > 14) { qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); } @@ -1227,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) /* emulu #imm, rd */ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) { - TCGv imm = tcg_const_i32(a->imm); + TCGv imm = tcg_constant_i32(a->imm); if (a->rd > 14) { qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); } @@ -1325,10 +1313,10 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) done = gen_new_label(); /* if (cpu_regs[a->rs]) { */ tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); - count = tcg_const_i32(32); + count = tcg_temp_new(); tmp = tcg_temp_new(); tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); - tcg_gen_sub_i32(count, count, tmp); + tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp); tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); @@ -1597,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) static inline void rx_save_pc(DisasContext *ctx) { - TCGv pc = tcg_const_i32(ctx->base.pc_next); + TCGv pc = tcg_constant_i32(ctx->base.pc_next); push(pc); } @@ -1680,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) #define STRING(op) \ do { \ - TCGv size = tcg_const_i32(a->sz); \ + TCGv size = tcg_constant_i32(a->sz); \ gen_helper_##op(cpu_env, size); \ } while (0) @@ -1811,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) /* racw #imm */ static bool trans_RACW(DisasContext *ctx, arg_RACW *a) { - TCGv imm = tcg_const_i32(a->imm + 1); + TCGv imm = tcg_constant_i32(a->imm + 1); gen_helper_racw(cpu_env, imm); return true; } @@ -1821,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a) { TCGv tmp, z; tmp = tcg_temp_new(); - z = tcg_const_i32(0); + z = tcg_constant_i32(0); /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ tcg_gen_sari_i32(tmp, cpu_psw_s, 31); /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ @@ -1843,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ cat3(arg_, name, _ir) * a) \ { \ - TCGv imm = tcg_const_i32(li(ctx, 0)); \ + TCGv imm = tcg_constant_i32(li(ctx, 0)); \ gen_helper_##op(cpu_regs[a->rd], cpu_env, \ cpu_regs[a->rd], imm); \ return true; \ @@ -1877,7 +1865,7 @@ FOP(FDIV, fdiv) /* fcmp #imm, rd */ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) { - TCGv imm = tcg_const_i32(li(ctx, 0)); + TCGv imm = tcg_constant_i32(li(ctx, 0)); gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); return true; } @@ -1974,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) { \ TCGv mask, mem, addr; \ mem = tcg_temp_new(); \ - mask = tcg_const_i32(1 << a->imm); \ + mask = tcg_constant_i32(1 << a->imm); \ addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ cat3(rx_, op, m)(addr, mask); \ return true; \ @@ -1983,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) cat3(arg_, name, _ir) * a) \ { \ TCGv mask; \ - mask = tcg_const_i32(1 << a->imm); \ + mask = tcg_constant_i32(1 << a->imm); \ cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ return true; \ } \ @@ -1991,10 +1979,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) cat3(arg_, name, _rr) * a) \ { \ TCGv mask, b; \ - mask = tcg_const_i32(1); \ + mask = tcg_temp_new(); \ b = tcg_temp_new(); \ tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ - tcg_gen_shl_i32(mask, mask, b); \ + tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ return true; \ } \ @@ -2002,10 +1990,10 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) cat3(arg_, name, _rm) * a) \ { \ TCGv mask, mem, addr, b; \ - mask = tcg_const_i32(1); \ + mask = tcg_temp_new(); \ b = tcg_temp_new(); \ tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ - tcg_gen_shl_i32(mask, mask, b); \ + tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \ mem = tcg_temp_new(); \ addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ cat3(rx_, op, m)(addr, mask); \ @@ -2128,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) { TCGv imm; - imm = tcg_const_i32(a->imm); + imm = tcg_constant_i32(a->imm); move_to_cr(ctx, imm, a->cr); return true; } @@ -2190,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) TCGv vec; tcg_debug_assert(a->imm < 0x100); - vec = tcg_const_i32(a->imm); + vec = tcg_constant_i32(a->imm); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_rxint(cpu_env, vec); ctx->base.is_jmp = DISAS_NORETURN; diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index bf951a002e..84ca08626b 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,5 @@ #define TARGET_PAGE_BITS 12 #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 -#define NB_MMU_MODES 4 #endif diff --git a/target/s390x/cpu-sysemu.c b/target/s390x/cpu-sysemu.c index 948e4bd3e0..97d6c760a8 100644 --- a/target/s390x/cpu-sysemu.c +++ b/target/s390x/cpu-sysemu.c @@ -21,6 +21,7 @@ */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qapi/error.h" #include "cpu.h" #include "s390x-internal.h" diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b10a8541ff..40fdeaa905 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -41,6 +41,26 @@ #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; +#ifndef CONFIG_USER_ONLY +static bool is_early_exception_psw(uint64_t mask, uint64_t addr) +{ + if (mask & PSW_MASK_RESERVED) { + return true; + } + + switch (mask & (PSW_MASK_32 | PSW_MASK_64)) { + case 0: + return addr & ~0xffffffULL; + case PSW_MASK_32: + return addr & ~0x7fffffffULL; + case PSW_MASK_32 | PSW_MASK_64: + return false; + default: /* PSW_MASK_64 */ + return true; + } +} +#endif + void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) { #ifndef CONFIG_USER_ONLY @@ -57,6 +77,12 @@ void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) env->cc_op = (mask >> 44) & 3; #ifndef CONFIG_USER_ONLY + if (is_early_exception_psw(mask, addr)) { + env->int_pgm_ilen = 0; + trigger_pgm_exception(env, PGM_SPECIFICATION); + return; + } + if ((old_mask ^ mask) & PSW_MASK_PER) { s390_cpu_recompute_watchpoints(env_cpu(env)); } diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7d6d01325b..c47e7adcb1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -29,6 +29,7 @@ #include "cpu_models.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" +#include "tcg/tcg_s390x.h" #define ELF_MACHINE_UNAME "S390X" @@ -87,6 +88,7 @@ struct CPUArchState { uint64_t cc_vr; uint64_t ex_value; + uint64_t ex_target; uint64_t __excp_addr; uint64_t psa; @@ -292,6 +294,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define PSW_MASK_32 0x0000000080000000ULL #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL +#define PSW_MASK_RESERVED 0xb80800fe7fffffffULL #undef PSW_ASC_PRIMARY #undef PSW_ASC_ACCREG @@ -381,6 +384,14 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { + if (env->psw.addr & 1) { + /* + * Instructions must be at even addresses. + * This needs to be checked before address translation. + */ + env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); + } *pc = env->psw.addr; *cs_base = env->ex_value; *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 065ec6d66c..457b5cb10c 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -17,6 +17,7 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qapi/visitor.h" #include "qemu/module.h" #include "qemu/hw-version.h" diff --git a/target/s390x/diag.c b/target/s390x/diag.c index 76b01dcd68..e5f0df19e7 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -22,6 +22,8 @@ #include "hw/s390x/pv.h" #include "sysemu/kvm.h" #include "kvm/kvm_s390x.h" +#include "qemu/error-report.h" + int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3) { diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index a5d69d0e0b..0cb69395b4 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -23,6 +23,7 @@ #include "s390x-internal.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/bitops.h" #include "sysemu/hw_accel.h" #include "sysemu/tcg.h" diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 473c8e51b0..2b363aa959 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/timer.h" #include "hw/s390x/ioinst.h" #include "hw/s390x/pv.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index bc767f0443..228aa9f237 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -85,8 +85,8 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc) /* * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment, - * this is only for the atomic operations, for which we want to raise a - * specification exception. + * this is only for the atomic and relative long operations, for which we want + * to raise a specification exception. */ static G_NORETURN void do_unaligned_access(CPUState *cs, uintptr_t retaddr) @@ -212,7 +212,8 @@ static void do_program_interrupt(CPUS390XState *env) LowCore *lowcore; int ilen = env->int_pgm_ilen; - assert(ilen == 2 || ilen == 4 || ilen == 6); + assert((env->int_pgm_code == PGM_SPECIFICATION && ilen == 0) || + ilen == 2 || ilen == 4 || ilen == 6); switch (env->int_pgm_code) { case PGM_PER: diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index 9d2d35f084..597d968b0e 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -199,8 +199,8 @@ C(0xe55c, CHSI, SIL, GIE, m1_32s, i2, 0, 0, 0, cmps64) C(0xe558, CGHSI, SIL, GIE, m1_64, i2, 0, 0, 0, cmps64) /* COMPARE HALFWORD RELATIVE LONG */ - C(0xc605, CHRL, RIL_b, GIE, r1_o, mri2_32s, 0, 0, 0, cmps32) - C(0xc604, CGHRL, RIL_b, GIE, r1_o, mri2_64, 0, 0, 0, cmps64) + C(0xc605, CHRL, RIL_b, GIE, r1_o, mri2_16s, 0, 0, 0, cmps32) + C(0xc604, CGHRL, RIL_b, GIE, r1_o, mri2_16s, 0, 0, 0, cmps64) /* COMPARE HIGH */ C(0xb9cd, CHHR, RRE, HW, r1_sr32, r2_sr32, 0, 0, 0, cmps32) C(0xb9dd, CHLR, RRE, HW, r1_sr32, r2_o, 0, 0, 0, cmps32) @@ -410,12 +410,12 @@ /* LOAD */ C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0) - C(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0) - C(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0) + D(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0, 0) + D(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0, 0) C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0) C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0) - C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0) - C(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0) + D(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0, 0) + D(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0, 0) F(0x2800, LDR, RR_a, Z, 0, f2, 0, f1, mov2, 0, IF_AFP1 | IF_AFP2) F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_AFP1) F(0xed65, LDY, RXY_a, LD, 0, m2_64, 0, f1, mov2, 0, IF_AFP1) @@ -426,9 +426,9 @@ /* LOAD IMMEDIATE */ C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0) /* LOAD RELATIVE LONG */ - C(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0) - C(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0) - C(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0) + D(0xc40d, LRL, RIL_b, GIE, 0, ri2, new, r1_32, ld32s, 0, MO_ALIGN) + D(0xc408, LGRL, RIL_b, GIE, 0, ri2, r1, 0, ld64, 0, MO_ALIGN) + D(0xc40c, LGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32s, 0, MO_ALIGN) /* LOAD ADDRESS */ C(0x4100, LA, RX_a, Z, 0, a2, 0, r1, mov2, 0) C(0xe371, LAY, RXY_a, LD, 0, a2, 0, r1, mov2, 0) @@ -456,9 +456,9 @@ C(0x1200, LTR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, s32) C(0xb902, LTGR, RRE, Z, 0, r2_o, 0, r1, mov2, s64) C(0xb912, LTGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, s64) - C(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64) - C(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64) - C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64) + D(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64, 0) + D(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64, 0) + D(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64, 0) F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP) F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP) F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP) @@ -502,16 +502,16 @@ C(0xc405, LHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16s, 0) C(0xc404, LGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16s, 0) /* LOAD HIGH */ - C(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0) + D(0xe3ca, LFH, RXY_a, HW, 0, a2, new, r1_32h, ld32u, 0, 0) /* LOAG HIGH AND TRAP */ C(0xe3c8, LFHAT, RXY_a, LAT, 0, m2_32u, r1, 0, lfhat, 0) /* LOAD LOGICAL */ C(0xb916, LLGFR, RRE, Z, 0, r2_32u, 0, r1, mov2, 0) - C(0xe316, LLGF, RXY_a, Z, 0, a2, r1, 0, ld32u, 0) + D(0xe316, LLGF, RXY_a, Z, 0, a2, r1, 0, ld32u, 0, 0) /* LOAD LOGICAL AND TRAP */ C(0xe39d, LLGFAT, RXY_a, LAT, 0, a2, r1, 0, llgfat, 0) /* LOAD LOGICAL RELATIVE LONG */ - C(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0) + D(0xc40e, LLGFRL, RIL_b, GIE, 0, ri2, r1, 0, ld32u, 0, MO_ALIGN) /* LOAD LOGICAL CHARACTER */ C(0xb994, LLCR, RRE, EI, 0, r2_8u, 0, r1_32, mov2, 0) C(0xb984, LLGCR, RRE, EI, 0, r2_8u, 0, r1, mov2, 0) @@ -840,16 +840,16 @@ F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) /* STORE */ - C(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0) - C(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0) - C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0) - F(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, IF_AFP1) - F(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, IF_AFP1) - F(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, IF_AFP1) - F(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, IF_AFP1) + D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0) + D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0) + D(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0, 0) + E(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, 0, IF_AFP1) + E(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, 0, IF_AFP1) + E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1) + E(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1) /* STORE RELATIVE LONG */ - C(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0) - C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0) + D(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN) + D(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0, MO_ALIGN) /* STORE CHARACTER */ C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0) C(0xe372, STCY, RXY_a, LD, r1_o, a2, 0, 0, st8, 0) @@ -867,7 +867,7 @@ /* STORE HALFWORD RELATIVE LONG */ C(0xc407, STHRL, RIL_b, GIE, r1_o, ri2, 0, 0, st16, 0) /* STORE HIGH */ - C(0xe3cb, STFH, RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0) + D(0xe3cb, STFH, RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0, 0) /* STORE ON CONDITION */ D(0xebf3, STOC, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0) D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 6835c26dda..b93dbd3dad 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -149,7 +149,6 @@ static inline int s390_probe_access(CPUArchState *env, target_ulong addr, nonfault, phost, ra); if (unlikely(flags & TLB_INVALID_MASK)) { - assert(!nonfault); #ifdef CONFIG_USER_ONLY /* Address is in TEC in system mode; see s390_cpu_record_sigsegv. */ env->__excp_addr = addr & TARGET_PAGE_MASK; @@ -2468,8 +2467,16 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, */ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) { - uint64_t insn = cpu_lduw_code(env, addr); - uint8_t opc = insn >> 8; + uint64_t insn; + uint8_t opc; + + /* EXECUTE targets must be at even addresses. */ + if (addr & 1) { + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC()); + } + + insn = cpu_lduw_code(env, addr); + opc = insn >> 8; /* Or in the contents of R1[56:63]. */ insn |= r1 & 0xff; @@ -2530,6 +2537,7 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) that ex_value is non-zero, which flags that we are in a state that requires such execution. */ env->ex_value = insn | ilen; + env->ex_target = addr; } uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 21a57d5eb2..2d9b4bbb1f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -156,8 +156,6 @@ struct DisasContext { typedef struct { TCGCond cond:8; bool is_64; - bool g1; - bool g2; union { struct { TCGv_i64 a, b; } s64; struct { TCGv_i32 a, b; } s32; @@ -308,8 +306,6 @@ static TCGv_i128 load_freg_128(int reg) TCGv_i128 r = tcg_temp_new_i128(); tcg_gen_concat_i64_i128(r, l, h); - tcg_temp_free_i64(h); - tcg_temp_free_i64(l); return r; } @@ -722,7 +718,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER); c->u.s32.a = cc_op; c->u.s32.b = cc_op; - c->g1 = c->g2 = true; c->is_64 = false; return; } @@ -839,7 +834,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) /* Load up the arguments of the comparison. */ c->is_64 = true; - c->g1 = c->g2 = false; switch (old_cc_op) { case CC_OP_LTGT0_32: c->is_64 = false; @@ -861,13 +855,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_FLOGR: c->u.s64.a = cc_dst; c->u.s64.b = tcg_constant_i64(0); - c->g1 = true; break; case CC_OP_LTGT_64: case CC_OP_LTUGTU_64: c->u.s64.a = cc_src; c->u.s64.b = cc_dst; - c->g1 = c->g2 = true; break; case CC_OP_TM_32: @@ -882,7 +874,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_SUBU: c->is_64 = true; c->u.s64.b = tcg_constant_i64(0); - c->g1 = true; switch (mask) { case 8 | 2: case 4 | 1: /* result */ @@ -900,7 +891,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_STATIC: c->is_64 = false; c->u.s32.a = cc_op; - c->g1 = true; switch (mask) { case 0x8 | 0x4 | 0x2: /* cc != 3 */ cond = TCG_COND_NE; @@ -916,7 +906,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) break; case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ cond = TCG_COND_EQ; - c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -935,7 +924,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) break; case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ cond = TCG_COND_NE; - c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -959,7 +947,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) default: /* CC is masked by something else: (8 >> cc) & mask. */ cond = TCG_COND_NE; - c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); c->u.s32.b = tcg_constant_i32(0); tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); @@ -974,24 +961,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) c->cond = cond; } -static void free_compare(DisasCompare *c) -{ - if (!c->g1) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.a); - } else { - tcg_temp_free_i32(c->u.s32.a); - } - } - if (!c->g2) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.b); - } else { - tcg_temp_free_i32(c->u.s32.b); - } - } -} - /* ====================================================================== */ /* Define the insn format enumeration. */ #define F0(N) FMT_##N, @@ -1092,7 +1061,6 @@ static const DisasFormatInfo format_info[] = { them, and store them back. See the "in1", "in2", "prep", "wout" sets of routines below for more details. */ typedef struct { - bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; TCGv_i128 out_128, in1_128, in2_128; @@ -1292,17 +1260,14 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, TCGv_i64 z = tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); - tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); - tcg_temp_free_i64(t1); } ret = DISAS_PC_UPDATED; } egress: - free_compare(c); return ret; } @@ -1462,11 +1427,11 @@ static DisasJumpType op_andi(DisasContext *s, DisasOps *o) int shift = s->insn->data & 0xff; int size = s->insn->data >> 8; uint64_t mask = ((1ull << size) - 1) << shift; + TCGv_i64 t = tcg_temp_new_i64(); - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_ori_i64(o->in2, o->in2, ~mask); - tcg_gen_and_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_ori_i64(t, t, ~mask); + tcg_gen_and_i64(o->out, o->in1, t); /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -1555,7 +1520,6 @@ static void save_link_info(DisasContext *s, DisasOps *o) tcg_gen_extu_i32_i64(t, cc_op); tcg_gen_shli_i64(t, t, 28); tcg_gen_or_i64(o->out, o->out, t); - tcg_temp_free_i64(t); } static DisasJumpType op_bal(DisasContext *s, DisasOps *o) @@ -1612,8 +1576,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o) c.cond = TCG_COND_NE; c.is_64 = false; - c.g1 = false; - c.g2 = false; t = tcg_temp_new_i64(); tcg_gen_subi_i64(t, regs[r1], 1); @@ -1621,7 +1583,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o) c.u.s32.a = tcg_temp_new_i32(); c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); - tcg_temp_free_i64(t); return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1635,8 +1596,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o) c.cond = TCG_COND_NE; c.is_64 = false; - c.g1 = false; - c.g2 = false; t = tcg_temp_new_i64(); tcg_gen_shri_i64(t, regs[r1], 32); @@ -1645,7 +1604,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o) c.u.s32.a = tcg_temp_new_i32(); c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); - tcg_temp_free_i64(t); return help_branch(s, &c, 1, imm, o->in2); } @@ -1659,8 +1617,6 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o) c.cond = TCG_COND_NE; c.is_64 = true; - c.g1 = true; - c.g2 = false; tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a = regs[r1]; @@ -1680,8 +1636,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOps *o) c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT); c.is_64 = false; - c.g1 = false; - c.g2 = false; t = tcg_temp_new_i64(); tcg_gen_add_i64(t, regs[r1], regs[r3]); @@ -1690,7 +1644,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOps *o) tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_gen_extrl_i64_i32(c.u.s32.b, regs[r3 | 1]); store_reg32_i64(r1, t); - tcg_temp_free_i64(t); return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1708,15 +1661,12 @@ static DisasJumpType op_bx64(DisasContext *s, DisasOps *o) if (r1 == (r3 | 1)) { c.u.s64.b = load_reg(r3 | 1); - c.g2 = false; } else { c.u.s64.b = regs[r3 | 1]; - c.g2 = true; } tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]); c.u.s64.a = regs[r1]; - c.g1 = true; return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1731,7 +1681,7 @@ static DisasJumpType op_cj(DisasContext *s, DisasOps *o) if (s->insn->data) { c.cond = tcg_unsigned_cond(c.cond); } - c.is_64 = c.g1 = c.g2 = true; + c.is_64 = true; c.u.s64.a = o->in1; c.u.s64.b = o->in2; @@ -2012,11 +1962,9 @@ static DisasJumpType op_cksm(DisasContext *s, DisasOps *o) gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); tcg_gen_extr_i128_i64(o->out, len, pair); - tcg_temp_free_i128(pair); tcg_gen_add_i64(regs[r2], regs[r2], len); tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len); - tcg_temp_free_i64(len); return DISAS_NEXT; } @@ -2118,7 +2066,6 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps *o) tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); - tcg_temp_free_i32(t1); return DISAS_NEXT; } @@ -2128,7 +2075,6 @@ static DisasJumpType op_clst(DisasContext *s, DisasOps *o) gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); tcg_gen_extr_i128_i64(o->in2, o->in1, pair); - tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; @@ -2140,7 +2086,6 @@ static DisasJumpType op_cps(DisasContext *s, DisasOps *o) tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull); tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); tcg_gen_or_i64(o->out, o->out, t); - tcg_temp_free_i64(t); return DISAS_NEXT; } @@ -2156,14 +2101,12 @@ static DisasJumpType op_cs(DisasContext *s, DisasOps *o) addr = get_address(s, 0, b2, d2); tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1, get_mem_index(s), s->insn->data | MO_ALIGN); - tcg_temp_free_i64(addr); /* Are the memory and expected values (un)equal? Note that this setcond produces the output CC value, thus the NE sense of the test. */ cc = tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out); tcg_gen_extrl_i64_i32(cc_op, cc); - tcg_temp_free_i64(cc); set_cc_static(s); return DISAS_NEXT; @@ -2223,7 +2166,6 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o) tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE)); tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2, get_mem_index(s), mop | MO_ALIGN); - tcg_temp_free_i64(addr); /* Are the memory and expected values (un)equal? */ cc = tcg_temp_new_i64(); @@ -2237,14 +2179,12 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o) } else { tcg_gen_mov_i64(o->out, old); } - tcg_temp_free_i64(old); /* If the comparison was equal, and the LSB of R2 was set, then we need to flush the TLB (for all cpus). */ tcg_gen_xori_i64(cc, cc, 1); tcg_gen_and_i64(cc, cc, o->in2); tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab); - tcg_temp_free_i64(cc); gen_helper_purge(cpu_env); gen_set_label(lab); @@ -2259,9 +2199,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o) TCGv_i32 t2 = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, o->in1); gen_helper_cvd(t1, t2); - tcg_temp_free_i32(t2); tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s)); - tcg_temp_free_i64(t1); return DISAS_NEXT; } @@ -2363,7 +2301,6 @@ static DisasJumpType op_divs64(DisasContext *s, DisasOps *o) gen_helper_divs64(t, cpu_env, o->in1, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); - tcg_temp_free_i128(t); return DISAS_NEXT; } @@ -2373,7 +2310,6 @@ static DisasJumpType op_divu64(DisasContext *s, DisasOps *o) gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); - tcg_temp_free_i128(t); return DISAS_NEXT; } @@ -2428,8 +2364,6 @@ static DisasJumpType op_epsw(DisasContext *s, DisasOps *o) if (r2 != 0) { store_reg32_i64(r2, psw_mask); } - - tcg_temp_free_i64(t); return DISAS_NEXT; } @@ -2569,7 +2503,6 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o) tcg_gen_movi_i64(tmp, ccm); gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -2592,8 +2525,6 @@ static DisasJumpType op_ipm(DisasContext *s, DisasOps *o) tcg_gen_extu_i32_i64(t2, cc_op); tcg_gen_deposit_i64(t1, t1, t2, 4, 60); tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NEXT; } @@ -2839,19 +2770,22 @@ static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o) static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), + MO_TESL | s->insn->data); return DISAS_NEXT; } static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), + MO_TEUL | s->insn->data); return DISAS_NEXT; } static DisasJumpType op_ld64(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), + MO_TEUQ | s->insn->data); return DISAS_NEXT; } @@ -2925,21 +2859,17 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) if (c.is_64) { tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b, o->in2, o->in1); - free_compare(&c); } else { TCGv_i32 t32 = tcg_temp_new_i32(); TCGv_i64 t, z; tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b); - free_compare(&c); t = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t, t32); - tcg_temp_free_i32(t32); z = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); - tcg_temp_free_i64(t); } return DISAS_NEXT; @@ -2983,21 +2913,21 @@ static DisasJumpType op_lpp(DisasContext *s, DisasOps *o) static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o) { - TCGv_i64 t1, t2; + TCGv_i64 mask, addr; per_breaking_event(s); - t1 = tcg_temp_new_i64(); - t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), - MO_TEUL | MO_ALIGN_8); - tcg_gen_addi_i64(o->in2, o->in2, 4); - tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s)); - /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ - tcg_gen_shli_i64(t1, t1, 32); - gen_helper_load_psw(cpu_env, t1, t2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); + /* + * Convert the short PSW into the normal PSW, similar to what + * s390_cpu_load_normal() does. + */ + mask = tcg_temp_new_i64(); + addr = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8); + tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR); + tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL); + tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW); + gen_helper_load_psw(cpu_env, mask, addr); return DISAS_NORETURN; } @@ -3014,8 +2944,6 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); gen_helper_load_psw(cpu_env, t1, t2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NORETURN; } #endif @@ -3040,7 +2968,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) if (unlikely(r1 == r3)) { tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32_i64(r1, t1); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -3055,8 +2982,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) /* Only two registers to read. */ if (((r1 + 1) & 15) == r3) { - tcg_temp_free(t2); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -3069,9 +2994,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32_i64(r1, t1); } - tcg_temp_free(t2); - tcg_temp_free(t1); - return DISAS_NEXT; } @@ -3086,7 +3008,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) if (unlikely(r1 == r3)) { tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32h_i64(r1, t1); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -3101,8 +3022,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) /* Only two registers to read. */ if (((r1 + 1) & 15) == r3) { - tcg_temp_free(t2); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -3115,9 +3034,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32h_i64(r1, t1); } - tcg_temp_free(t2); - tcg_temp_free(t1); - return DISAS_NEXT; } @@ -3141,11 +3057,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s)); tcg_gen_mov_i64(regs[r1], t1); - tcg_temp_free(t2); /* Only two registers to read. */ if (((r1 + 1) & 15) == r3) { - tcg_temp_free(t1); return DISAS_NEXT; } @@ -3157,8 +3071,6 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o) tcg_gen_add_i64(o->in2, o->in2, t1); tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s)); } - tcg_temp_free(t1); - return DISAS_NEXT; } @@ -3180,8 +3092,6 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o) a2 = get_address(s, 0, get_field(s, b2), get_field(s, d2)); tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN); tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN); - tcg_temp_free_i64(a1); - tcg_temp_free_i64(a2); /* ... and indicate that we performed them while interlocked. */ gen_op_movi_cc(s, 0); @@ -3253,9 +3163,7 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o) static DisasJumpType op_mov2(DisasContext *s, DisasOps *o) { o->out = o->in2; - o->g_out = o->g_in2; o->in2 = NULL; - o->g_in2 = false; return DISAS_NEXT; } @@ -3265,9 +3173,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o) TCGv ar1 = tcg_temp_new_i64(); o->out = o->in2; - o->g_out = o->g_in2; o->in2 = NULL; - o->g_in2 = false; switch (s->base.tb->flags & FLAG_MASK_ASC) { case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT: @@ -3289,8 +3195,6 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o) } tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1])); - tcg_temp_free_i64(ar1); - return DISAS_NEXT; } @@ -3298,11 +3202,8 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o) { o->out = o->in1; o->out2 = o->in2; - o->g_out = o->g_in1; - o->g_out2 = o->g_in2; o->in1 = NULL; o->in2 = NULL; - o->g_in1 = o->g_in2 = false; return DISAS_NEXT; } @@ -3509,7 +3410,6 @@ static DisasJumpType op_maeb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 = load_freg32_i64(get_field(s, r3)); gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } @@ -3517,7 +3417,6 @@ static DisasJumpType op_madb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 = load_freg(get_field(s, r3)); gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } @@ -3525,7 +3424,6 @@ static DisasJumpType op_mseb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 = load_freg32_i64(get_field(s, r3)); gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } @@ -3533,7 +3431,6 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 = load_freg(get_field(s, r3)); gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } @@ -3544,7 +3441,6 @@ static DisasJumpType op_nabs(DisasContext *s, DisasOps *o) tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); - tcg_temp_free_i64(n); return DISAS_NEXT; } @@ -3621,10 +3517,10 @@ static DisasJumpType op_ori(DisasContext *s, DisasOps *o) int shift = s->insn->data & 0xff; int size = s->insn->data >> 8; uint64_t mask = ((1ull << size) - 1) << shift; + TCGv_i64 t = tcg_temp_new_i64(); - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_or_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_or_i64(o->out, o->in1, t); /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -3804,12 +3700,15 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o) int i3 = get_field(s, i3); int i4 = get_field(s, i4); int i5 = get_field(s, i5); + TCGv_i64 orig_out; uint64_t mask; /* If this is a test-only form, arrange to discard the result. */ if (i3 & 0x80) { + tcg_debug_assert(o->out != NULL); + orig_out = o->out; o->out = tcg_temp_new_i64(); - o->g_out = false; + tcg_gen_mov_i64(o->out, orig_out); } i3 &= 63; @@ -3879,9 +3778,6 @@ static DisasJumpType op_rll32(DisasContext *s, DisasOps *o) tcg_gen_extrl_i64_i32(t2, o->in2); tcg_gen_rotl_i32(to, t1, t2); tcg_gen_extu_i32_i64(o->out, to); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(to); return DISAS_NEXT; } @@ -4022,7 +3918,6 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o) } else { tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab); } - free_compare(&c); r1 = get_field(s, r1); a = get_address(s, 0, get_field(s, b2), get_field(s, d2)); @@ -4037,12 +3932,10 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o) h = tcg_temp_new_i64(); tcg_gen_shri_i64(h, regs[r1], 32); tcg_gen_qemu_st32(h, a, get_mem_index(s)); - tcg_temp_free_i64(h); break; default: g_assert_not_reached(); } - tcg_temp_free_i64(a); gen_set_label(lab); return DISAS_NEXT; @@ -4059,9 +3952,6 @@ static DisasJumpType op_sla(DisasContext *s, DisasOps *o) t = o->in1; } gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2); - if (s->insn->data == 31) { - tcg_temp_free_i64(t); - } tcg_gen_shl_i64(o->out, o->in1, o->in2); /* The arithmetic left shift is curious in that it does not affect the sign bit. Copy that over from the source unchanged. */ @@ -4128,8 +4018,6 @@ static DisasJumpType op_srnmt(DisasContext *s, DisasOps *o) tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3); tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); - - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -4170,8 +4058,6 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o) /* store second operand in GR1 */ tcg_gen_mov_i64(regs[1], o->in2); - - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -4189,9 +4075,23 @@ static DisasJumpType op_sske(DisasContext *s, DisasOps *o) return DISAS_NEXT; } +static void gen_check_psw_mask(DisasContext *s) +{ + TCGv_i64 reserved = tcg_temp_new_i64(); + TCGLabel *ok = gen_new_label(); + + tcg_gen_andi_i64(reserved, psw_mask, PSW_MASK_RESERVED); + tcg_gen_brcondi_i64(TCG_COND_EQ, reserved, 0, ok); + gen_program_exception(s, PGM_SPECIFICATION); + gen_set_label(ok); +} + static DisasJumpType op_ssm(DisasContext *s, DisasOps *o) { tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8); + + gen_check_psw_mask(s); + /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -4231,9 +4131,6 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o) tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s)); tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s)); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - tcg_temp_free_i64(todpr); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4447,7 +4344,6 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o) t = tcg_temp_new_i64(); tcg_gen_shri_i64(t, psw_mask, 56); tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s)); - tcg_temp_free_i64(t); if (s->fields.op == 0xac) { tcg_gen_andi_i64(psw_mask, psw_mask, @@ -4456,6 +4352,8 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o) tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56); } + gen_check_psw_mask(s); + /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -4494,13 +4392,15 @@ static DisasJumpType op_st16(DisasContext *s, DisasOps *o) static DisasJumpType op_st32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s), + MO_TEUL | s->insn->data); return DISAS_NEXT; } static DisasJumpType op_st64(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), + MO_TEUQ | s->insn->data); return DISAS_NEXT; } @@ -4558,7 +4458,6 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o) } break; } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -4602,8 +4501,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) tcg_gen_add_i64(o->in2, o->in2, t4); r1 = (r1 + 1) & 15; } - - tcg_temp_free_i64(t); return DISAS_NEXT; } @@ -4790,7 +4687,6 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o) gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, pair); - tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; } @@ -4836,7 +4732,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); - tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; } @@ -4955,10 +4850,10 @@ static DisasJumpType op_xori(DisasContext *s, DisasOps *o) int shift = s->insn->data & 0xff; int size = s->insn->data >> 8; uint64_t mask = ((1ull << size) - 1) << shift; + TCGv_i64 t = tcg_temp_new_i64(); - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_xor_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_xor_i64(o->out, o->in1, t); /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -4989,15 +4884,14 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o) static DisasJumpType op_zero(DisasContext *s, DisasOps *o) { - o->out = tcg_const_i64(0); + o->out = tcg_constant_i64(0); return DISAS_NEXT; } static DisasJumpType op_zero2(DisasContext *s, DisasOps *o) { - o->out = tcg_const_i64(0); + o->out = tcg_constant_i64(0); o->out2 = o->out; - o->g_out2 = true; return DISAS_NEXT; } @@ -5265,7 +5159,6 @@ static void prep_new_x(DisasContext *s, DisasOps *o) static void prep_r1(DisasContext *s, DisasOps *o) { o->out = regs[get_field(s, r1)]; - o->g_out = true; } #define SPEC_prep_r1 0 @@ -5274,7 +5167,6 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); o->out = regs[r1]; o->out2 = regs[r1 + 1]; - o->g_out = o->g_out2 = true; } #define SPEC_prep_r1_P SPEC_r1_even @@ -5343,7 +5235,6 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) store_reg32_i64(r1 + 1, o->out); tcg_gen_shri_i64(t, o->out, 32); store_reg32_i64(r1, t); - tcg_temp_free_i64(t); } #define SPEC_wout_r1_D32 SPEC_r1_even @@ -5499,7 +5390,6 @@ static void in1_r1(DisasContext *s, DisasOps *o) static void in1_r1_o(DisasContext *s, DisasOps *o) { o->in1 = regs[get_field(s, r1)]; - o->g_in1 = true; } #define SPEC_in1_r1_o 0 @@ -5533,7 +5423,6 @@ static void in1_r1p1(DisasContext *s, DisasOps *o) static void in1_r1p1_o(DisasContext *s, DisasOps *o) { o->in1 = regs[get_field(s, r1) + 1]; - o->g_in1 = true; } #define SPEC_in1_r1p1_o SPEC_r1_even @@ -5588,7 +5477,6 @@ static void in1_r3(DisasContext *s, DisasOps *o) static void in1_r3_o(DisasContext *s, DisasOps *o) { o->in1 = regs[get_field(s, r3)]; - o->g_in1 = true; } #define SPEC_in1_r3_o 0 @@ -5719,7 +5607,6 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) static void in2_r1_o(DisasContext *s, DisasOps *o) { o->in2 = regs[get_field(s, r1)]; - o->g_in2 = true; } #define SPEC_in2_r1_o 0 @@ -5754,7 +5641,6 @@ static void in2_r2(DisasContext *s, DisasOps *o) static void in2_r2_o(DisasContext *s, DisasOps *o) { o->in2 = regs[get_field(s, r2)]; - o->g_in2 = true; } #define SPEC_in2_r2_o 0 @@ -5888,7 +5774,18 @@ static void in2_a2(DisasContext *s, DisasOps *o) static TCGv gen_ri2(DisasContext *s) { - return tcg_constant_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2); + int64_t delta = (int64_t)get_field(s, i2) * 2; + TCGv ri2; + + if (unlikely(s->ex_value)) { + ri2 = tcg_temp_new_i64(); + tcg_gen_ld_i64(ri2, cpu_env, offsetof(CPUS390XState, ex_target)); + tcg_gen_addi_i64(ri2, ri2, delta); + } else { + ri2 = tcg_constant_i64(s->base.pc_next + delta); + } + + return ri2; } static void in2_ri2(DisasContext *s, DisasOps *o) @@ -5903,7 +5800,7 @@ static void in2_sh(DisasContext *s, DisasOps *o) int d2 = get_field(s, d2); if (b2 == 0) { - o->in2 = tcg_const_i64(d2 & 0x3f); + o->in2 = tcg_constant_i64(d2 & 0x3f); } else { o->in2 = get_address(s, 0, b2, d2); tcg_gen_andi_i64(o->in2, o->in2, 0x3f); @@ -5979,6 +5876,13 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o) #define SPEC_in2_m2_64a 0 #endif +static void in2_mri2_16s(DisasContext *s, DisasOps *o) +{ + o->in2 = tcg_temp_new_i64(); + tcg_gen_qemu_ld16s(o->in2, gen_ri2(s), get_mem_index(s)); +} +#define SPEC_in2_mri2_16s 0 + static void in2_mri2_16u(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); @@ -5989,66 +5893,69 @@ static void in2_mri2_16u(DisasContext *s, DisasOps *o) static void in2_mri2_32s(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32s(o->in2, gen_ri2(s), get_mem_index(s)); + tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), + MO_TESL | MO_ALIGN); } #define SPEC_in2_mri2_32s 0 static void in2_mri2_32u(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(o->in2, gen_ri2(s), get_mem_index(s)); + tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), + MO_TEUL | MO_ALIGN); } #define SPEC_in2_mri2_32u 0 static void in2_mri2_64(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(o->in2, gen_ri2(s), get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), + MO_TEUQ | MO_ALIGN); } #define SPEC_in2_mri2_64 0 static void in2_i2(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64(get_field(s, i2)); + o->in2 = tcg_constant_i64(get_field(s, i2)); } #define SPEC_in2_i2 0 static void in2_i2_8u(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64((uint8_t)get_field(s, i2)); + o->in2 = tcg_constant_i64((uint8_t)get_field(s, i2)); } #define SPEC_in2_i2_8u 0 static void in2_i2_16u(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64((uint16_t)get_field(s, i2)); + o->in2 = tcg_constant_i64((uint16_t)get_field(s, i2)); } #define SPEC_in2_i2_16u 0 static void in2_i2_32u(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64((uint32_t)get_field(s, i2)); + o->in2 = tcg_constant_i64((uint32_t)get_field(s, i2)); } #define SPEC_in2_i2_32u 0 static void in2_i2_16u_shl(DisasContext *s, DisasOps *o) { uint64_t i2 = (uint16_t)get_field(s, i2); - o->in2 = tcg_const_i64(i2 << s->insn->data); + o->in2 = tcg_constant_i64(i2 << s->insn->data); } #define SPEC_in2_i2_16u_shl 0 static void in2_i2_32u_shl(DisasContext *s, DisasOps *o) { uint64_t i2 = (uint32_t)get_field(s, i2); - o->in2 = tcg_const_i64(i2 << s->insn->data); + o->in2 = tcg_constant_i64(i2 << s->insn->data); } #define SPEC_in2_i2_32u_shl 0 #ifndef CONFIG_USER_ONLY static void in2_insn(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64(s->fields.raw_insn); + o->in2 = tcg_constant_i64(s->fields.raw_insn); } #define SPEC_in2_insn 0 #endif @@ -6474,31 +6381,6 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } } - /* Free any temporaries created by the helpers. */ - if (o.out && !o.g_out) { - tcg_temp_free_i64(o.out); - } - if (o.out2 && !o.g_out2) { - tcg_temp_free_i64(o.out2); - } - if (o.in1 && !o.g_in1) { - tcg_temp_free_i64(o.in1); - } - if (o.in2 && !o.g_in2) { - tcg_temp_free_i64(o.in2); - } - if (o.addr1) { - tcg_temp_free_i64(o.addr1); - } - if (o.out_128) { - tcg_temp_free_i128(o.out_128); - } - if (o.in1_128) { - tcg_temp_free_i128(o.in1_128); - } - if (o.in2_128) { - tcg_temp_free_i128(o.in2_128); - } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret == DISAS_NEXT)) { ret = DISAS_TOO_MANY; diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc index 3fadc82e5c..43dfbfd03f 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -183,8 +183,6 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, /* generate the final ptr by adding cpu_env */ tcg_gen_trunc_i64_ptr(ptr, tmp); tcg_gen_add_ptr(ptr, ptr, cpu_env); - - tcg_temp_free_i64(tmp); } #define gen_gvec_2(v1, v2, gen) \ @@ -272,13 +270,6 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a, fn(dl, dh, al, ah, bl, bh); write_vec_element_i64(dh, d, 0, ES_64); write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); } typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -305,15 +296,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, fn(dl, dh, al, ah, bl, bh, cl, ch); write_vec_element_i64(dh, d, 0, ES_64); write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(ch); - tcg_temp_free_i64(cl); } static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, @@ -351,7 +333,6 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -386,7 +367,6 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o) write_vec_element_i64(t, get_field(s, v1), 0, ES_64); tcg_gen_movi_i64(t, generate_byte_mask(i2)); write_vec_element_i64(t, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t); } return DISAS_NEXT; } @@ -427,8 +407,6 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -451,7 +429,6 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -469,7 +446,6 @@ static DisasJumpType op_vlebr(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -486,7 +462,6 @@ static DisasJumpType op_vlbrrep(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -518,7 +493,6 @@ static DisasJumpType op_vllebrz(DisasContext *s, DisasOps *o) write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); write_vec_element_i64(tcg_constant_i64(0), get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -572,9 +546,6 @@ static DisasJumpType op_vlbr(DisasContext *s, DisasOps *o) write: write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -592,7 +563,6 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -647,8 +617,6 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps *o) write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -688,8 +656,6 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o) default: g_assert_not_reached(); } - tcg_temp_free_ptr(ptr); - return DISAS_NEXT; } @@ -730,7 +696,6 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); gen_gvec_dup_imm(es, get_field(s, v1), 0); write_vec_element_i64(t, get_field(s, v1), enr, es); - tcg_temp_free_i64(t); return DISAS_NEXT; } @@ -768,9 +733,6 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *o) /* Store the last element, loaded first */ write_vec_element_i64(t0, v1, 1, ES_64); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); return DISAS_NEXT; } @@ -794,8 +756,6 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o) tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vll(cpu_env, a0, o->addr1, bytes); - tcg_temp_free_i64(bytes); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } @@ -835,8 +795,6 @@ static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o) default: g_assert_not_reached(); } - tcg_temp_free_ptr(ptr); - return DISAS_NEXT; } @@ -856,7 +814,6 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *o) tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vll(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } @@ -898,7 +855,6 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *o) write_vec_element_i64(tmp, v1, dst_idx, es); } } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -974,7 +930,6 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o) } write_vec_element_i64(tmp, v1, dst_idx, dst_es); } - tcg_temp_free_i64(tmp); } else { gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]); } @@ -1004,8 +959,6 @@ static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o) read_vec_element_i64(t1, get_field(s, v3), i3, ES_64); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); return DISAS_NEXT; } @@ -1057,7 +1010,6 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o) read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1098,7 +1050,6 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN); write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1116,7 +1067,6 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o) gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1134,7 +1084,6 @@ static DisasJumpType op_vstebr(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1189,9 +1138,6 @@ write: tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_LEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_LEUQ); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -1209,7 +1155,6 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o) tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1251,9 +1196,6 @@ static DisasJumpType op_vster(DisasContext *s, DisasOps *o) tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } @@ -1284,7 +1226,6 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) } gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1297,7 +1238,6 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOps *o) tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } @@ -1335,7 +1275,6 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o) write_vec_element_i64(tmp, v1, dst_idx, dst_es); } } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1377,10 +1316,6 @@ static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) /* Isolate and shift the carry into position */ tcg_gen_and_i64(d, d, msb_mask); tcg_gen_shri_i64(d, d, msb_bit_nr); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1399,7 +1334,6 @@ static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) tcg_gen_add_i32(t, a, b); tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b); - tcg_temp_free_i32(t); } static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1408,7 +1342,6 @@ static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) tcg_gen_add_i64(t, a, b); tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); - tcg_temp_free_i64(t); } static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -1422,9 +1355,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); } static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1460,8 +1390,6 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); - - tcg_temp_free_i64(tl); } static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1490,9 +1418,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1533,9 +1458,6 @@ static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) tcg_gen_addi_i64(t0, t0, 1); tcg_gen_shri_i64(t0, t0, 1); tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) @@ -1550,10 +1472,6 @@ static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(bh); } static DisasJumpType op_vavg(DisasContext *s, DisasOps *o) @@ -1586,9 +1504,6 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) tcg_gen_addi_i64(t0, t0, 1); tcg_gen_shri_i64(t0, t0, 1); tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) @@ -1599,8 +1514,6 @@ static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); } static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -1635,9 +1548,6 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o) } gen_gvec_dup_imm(ES_32, get_field(s, v1), 0); write_vec_element_i32(sum, get_field(s, v1), 1, ES_32); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(sum); return DISAS_NEXT; } @@ -1682,9 +1592,6 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps *o) read_vec_element_i64(high, get_field(s, v1), 0, ES_64); read_vec_element_i64(low, get_field(s, v1), 1, ES_64); gen_op_update2_cc_i64(s, CC_OP_VC, low, high); - - tcg_temp_free_i64(low); - tcg_temp_free_i64(high); } return DISAS_NEXT; } @@ -1853,8 +1760,6 @@ static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) tcg_gen_mul_i32(t0, a, b); tcg_gen_add_i32(d, t0, c); - - tcg_temp_free_i32(t0); } static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) @@ -1869,10 +1774,6 @@ static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) tcg_gen_mul_i64(t0, t0, t1); tcg_gen_add_i64(t0, t0, t2); tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) @@ -1887,10 +1788,6 @@ static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) tcg_gen_mul_i64(t0, t0, t1); tcg_gen_add_i64(t0, t0, t2); tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } static DisasJumpType op_vma(DisasContext *s, DisasOps *o) @@ -1974,7 +1871,6 @@ static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) TCGv_i32 t = tcg_temp_new_i32(); tcg_gen_muls2_i32(t, d, a, b); - tcg_temp_free_i32(t); } static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) @@ -1982,7 +1878,6 @@ static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) TCGv_i32 t = tcg_temp_new_i32(); tcg_gen_mulu2_i32(t, d, a, b); - tcg_temp_free_i32(t); } static DisasJumpType op_vm(DisasContext *s, DisasOps *o) @@ -2099,11 +1994,6 @@ static DisasJumpType op_vmsl(DisasContext *s, DisasOps *o) /* Store final result into v1. */ write_vec_element_i64(h1, get_field(s, v1), 0, ES_64); write_vec_element_i64(l1, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(l1); - tcg_temp_free_i64(h1); - tcg_temp_free_i64(l2); - tcg_temp_free_i64(h2); return DISAS_NEXT; } @@ -2169,8 +2059,6 @@ static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c) tcg_gen_and_i32(t, t, b); tcg_gen_andc_i32(d, d, b); tcg_gen_or_i32(d, d, t); - - tcg_temp_free_i32(t); } static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c) @@ -2181,8 +2069,6 @@ static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c) tcg_gen_and_i64(t, t, b); tcg_gen_andc_i64(d, d, b); tcg_gen_or_i64(d, d, t); - - tcg_temp_free_i64(t); } static DisasJumpType op_verim(DisasContext *s, DisasOps *o) @@ -2291,7 +2177,6 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o) default: g_assert_not_reached(); } - tcg_temp_free_i32(shift); } return DISAS_NEXT; } @@ -2311,7 +2196,6 @@ static DisasJumpType gen_vsh_by_byte(DisasContext *s, DisasOps *o, read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); tcg_gen_andi_i64(shift, shift, byte ? 0x78 : 7); gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), shift, 0, gen); - tcg_temp_free_i64(shift); } return DISAS_NEXT; } @@ -2367,10 +2251,6 @@ static DisasJumpType op_vsld(DisasContext *s, DisasOps *o) write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); return DISAS_NEXT; } @@ -2397,10 +2277,6 @@ static DisasJumpType op_vsrd(DisasContext *s, DisasOps *o) write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); return DISAS_NEXT; } @@ -2445,9 +2321,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, /* "invert" the result: -1 -> 0; 0 -> 1 */ tcg_gen_addi_i64(dl, th, 1); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); } static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2482,8 +2355,6 @@ static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_gen_not_i64(tl, bl); tcg_gen_not_i64(th, bh); gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o) @@ -2508,9 +2379,6 @@ static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_gen_not_i64(tl, bl); tcg_gen_not_i64(th, bh); gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o) @@ -2550,8 +2418,6 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o) } write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64); } - tcg_temp_free_i64(sum); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -2580,10 +2446,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) } write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64); write_vec_element_i64(suml, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(sumh); - tcg_temp_free_i64(suml); - tcg_temp_free_i64(tmpl); return DISAS_NEXT; } @@ -2611,8 +2473,6 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o) } write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32); } - tcg_temp_free_i32(sum); - tcg_temp_free_i32(tmp); return DISAS_NEXT; } @@ -3399,9 +3259,6 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o) read_vec_element_i64(tmp, v2, 1, ES_64); write_vec_element_i64(tmp, v1, 1, ES_64); } - - tcg_temp_free_i64(tmp); - return DISAS_NEXT; } diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index 98a02509bb..a7cdb7edb6 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,6 +16,5 @@ #else # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -#define NB_MMU_MODES 2 #endif diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index 3488f68e32..d8e199fc06 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ /* FIXME: We should use XML for this. */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index ad6de41712..6e40d5dd6a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -171,16 +171,16 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", env->sgr, env->dbr, env->delayed_pc, env->fpul); for (i = 0; i < 24; i += 4) { - qemu_printf("r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", - i, env->gregs[i], i + 1, env->gregs[i + 1], - i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); + qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", + i, env->gregs[i], i + 1, env->gregs[i + 1], + i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); } if (env->flags & TB_FLAG_DELAY_SLOT) { - qemu_printf("in delay slot (delayed_pc=0x%08x)\n", - env->delayed_pc); + qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", + env->delayed_pc); } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) { - qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n", - env->delayed_pc); + qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", + env->delayed_pc); } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) { qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", env->delayed_pc); @@ -526,13 +526,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0x9000: /* mov.w @(disp,PC),Rn */ { - TCGv addr = tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2); + TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); } return; case 0xd000: /* mov.l @(disp,PC),Rn */ { - TCGv addr = tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3); + TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); } return; @@ -694,7 +694,7 @@ static void _decode_opc(DisasContext * ctx) case 0x300e: /* addc Rm,Rn */ { TCGv t0, t1; - t0 = tcg_const_tl(0); + t0 = tcg_constant_tl(0); t1 = tcg_temp_new(); tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, @@ -754,7 +754,7 @@ static void _decode_opc(DisasContext * ctx) TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); TCGv t2 = tcg_temp_new(); - TCGv zero = tcg_const_i32(0); + TCGv zero = tcg_constant_i32(0); /* shift left arg1, saving the bit being pushed out and inserting T on the right */ @@ -849,7 +849,7 @@ static void _decode_opc(DisasContext * ctx) return; case 0x600a: /* negc Rm,Rn */ { - TCGv t0 = tcg_const_i32(0); + TCGv t0 = tcg_constant_i32(0); tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, REG(B7_4), t0, cpu_sr_t, t0); tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, @@ -913,7 +913,7 @@ static void _decode_opc(DisasContext * ctx) case 0x300a: /* subc Rm,Rn */ { TCGv t0, t1; - t0 = tcg_const_tl(0); + t0 = tcg_constant_tl(0); t1 = tcg_temp_new(); tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, @@ -1242,7 +1242,7 @@ static void _decode_opc(DisasContext * ctx) TCGv imm; CHECK_NOT_DELAY_SLOT gen_save_cpu_state(ctx, true); - imm = tcg_const_i32(B7_0); + imm = tcg_constant_i32(B7_0); gen_helper_trapa(cpu_env, imm); ctx->base.is_jmp = DISAS_NORETURN; } @@ -1610,12 +1610,9 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); return; case 0x401b: /* tas.b @Rn */ - { - TCGv val = tcg_const_i32(0x80); - tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val, - ctx->memidx, MO_UB); - tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - } + tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8), + tcg_constant_i32(0x80), ctx->memidx, MO_UB); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0); return; case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ CHECK_FPU_ENABLED @@ -1712,8 +1709,8 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED CHECK_FPSCR_PR_1 { - TCGv m = tcg_const_i32((ctx->opcode >> 8) & 3); - TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3); + TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3); + TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); gen_helper_fipr(cpu_env, m, n); return; } @@ -1725,7 +1722,7 @@ static void _decode_opc(DisasContext * ctx) if ((ctx->opcode & 0x0300) != 0x0100) { goto do_illegal; } - TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3); + TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3); gen_helper_ftrv(cpu_env, n); return; } @@ -1929,7 +1926,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) } op_dst = B11_8; op_opc = INDEX_op_xor_i32; - op_arg = tcg_const_i32(-1); + op_arg = tcg_constant_i32(-1); break; case 0x7000 ... 0x700f: /* add #imm,Rn */ @@ -1937,7 +1934,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) goto fail; } op_opc = INDEX_op_add_i32; - op_arg = tcg_const_i32(B7_0s); + op_arg = tcg_constant_i32(B7_0s); break; case 0x3000: /* cmp/eq Rm,Rn */ @@ -1983,7 +1980,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) goto fail; } op_opc = INDEX_op_setcond_i32; - op_arg = tcg_const_i32(0); + op_arg = tcg_constant_i32(0); NEXT_INSN; if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */ diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 72ddc4a34f..cb11980404 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -16,13 +16,11 @@ # else # define TARGET_VIRT_ADDR_SPACE_BITS 44 # endif -# define NB_MMU_MODES 6 #else # define TARGET_LONG_BITS 32 # define TARGET_PAGE_BITS 12 /* 4k */ # define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 -# define NB_MMU_MODES 3 #endif #endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ed0069d0b1..fb98843dad 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -197,8 +197,7 @@ enum { #define FSR_FTT2 (1ULL << 16) #define FSR_FTT1 (1ULL << 15) #define FSR_FTT0 (1ULL << 14) -//gcc warns about constant overflow for ~FSR_FTT_MASK -//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) +#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) #ifdef TARGET_SPARC64 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 5d1e808e8c..a1c8fdc4d5 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #ifdef TARGET_ABI32 #define gdb_get_rega(buf, val) gdb_get_reg32(buf, val) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5ee293326c..137bdc5159 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2838,7 +2838,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, int width, bool cc, bool left) { - TCGv lo1, lo2, t1, t2; + TCGv lo1, lo2; uint64_t amask, tabl, tabr; int shift, imask, omask; @@ -2905,10 +2905,8 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, tcg_gen_shli_tl(lo1, lo1, shift); tcg_gen_shli_tl(lo2, lo2, shift); - t1 = tcg_const_tl(tabl); - t2 = tcg_const_tl(tabr); - tcg_gen_shr_tl(lo1, t1, lo1); - tcg_gen_shr_tl(lo2, t2, lo2); + tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); + tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); tcg_gen_andi_tl(dst, lo1, omask); tcg_gen_andi_tl(lo2, lo2, omask); @@ -2927,9 +2925,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, lo2 |= -(s1 == s2) dst &= lo2 */ - tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2); - tcg_gen_neg_tl(t1, t1); - tcg_gen_or_tl(lo2, lo2, t1); + tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2); + tcg_gen_neg_tl(lo1, lo1); + tcg_gen_or_tl(lo2, lo2, lo1); tcg_gen_and_tl(dst, dst, lo2); } diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 2727913047..e29d551dd6 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,6 +12,5 @@ #define TARGET_PAGE_BITS 14 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define NB_MMU_MODES 3 #endif diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c index 3a27a7e65d..e8f8e5e6ea 100644 --- a/target/tricore/gdbstub.c +++ b/target/tricore/gdbstub.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #define LCX_REGNUM 32 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 127f9a989a..2646cb3eb5 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -124,7 +124,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) /* Makros for generating helpers */ #define gen_helper_1arg(name, arg) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg); \ + TCGv_i32 helper_tmp = tcg_constant_i32(arg); \ gen_helper_##name(cpu_env, helper_tmp); \ } while (0) @@ -513,7 +513,7 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_madd32_d(ret, r1, r2, temp); } @@ -579,7 +579,7 @@ static inline void gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); } @@ -587,7 +587,7 @@ static inline void gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); } @@ -595,21 +595,22 @@ static inline void gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -621,21 +622,22 @@ static inline void gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -647,22 +649,22 @@ static inline void gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); TCGv_i64 temp64_3 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); @@ -682,23 +684,24 @@ static inline void gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv temp3 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -718,23 +721,24 @@ static inline void gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv temp3 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -752,22 +756,22 @@ static inline void gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ @@ -785,22 +789,22 @@ static inline void gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); TCGv_i64 temp64_3 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); break; } tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); @@ -813,21 +817,21 @@ static inline void gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); break; } tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); @@ -839,20 +843,20 @@ static inline void gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); @@ -872,21 +876,22 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) static inline void gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_andi_tl(temp2, r1, 0xffff0000); @@ -899,20 +904,20 @@ static inline void gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); @@ -932,21 +937,22 @@ gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) static inline void gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_andi_tl(temp2, r1, 0xffff0000); @@ -957,15 +963,15 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) static inline void gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { - TCGv temp = tcg_const_i32(n); - gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); + TCGv t_n = tcg_constant_i32(n); + gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n); } static inline void gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { - TCGv temp = tcg_const_i32(n); - gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); + TCGv t_n = tcg_constant_i32(n); + gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n); } static inline void @@ -1176,10 +1182,10 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, TCGv arg3, uint32_t n) { TCGv_i64 r1 = tcg_temp_new_i64(); - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); - gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); + gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); tcg_gen_extr_i64_i32(rl, rh, r1); } @@ -1218,7 +1224,7 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_msub32_d(ret, r1, r2, temp); } @@ -1254,7 +1260,7 @@ static inline void gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); } @@ -1290,13 +1296,13 @@ static inline void gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); } static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) { - TCGv temp = tcg_const_i32(r2); + TCGv temp = tcg_constant_i32(r2); gen_add_d(ret, r1, temp); } @@ -1326,7 +1332,7 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_add_CC(ret, r1, temp); } @@ -1358,7 +1364,7 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_addc_CC(ret, r1, temp); } @@ -1369,7 +1375,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv temp2 = tcg_temp_new(); TCGv result = tcg_temp_new(); TCGv mask = tcg_temp_new(); - TCGv t0 = tcg_const_i32(0); + TCGv t0 = tcg_constant_i32(0); /* create mask for sticky bits */ tcg_gen_setcond_tl(cond, mask, r4, t0); @@ -1398,7 +1404,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, TCGv r3, TCGv r4) { - TCGv temp = tcg_const_i32(r2); + TCGv temp = tcg_constant_i32(r2); gen_cond_add(cond, r1, temp, r3, r4); } @@ -1486,7 +1492,7 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, TCGv temp2 = tcg_temp_new(); TCGv result = tcg_temp_new(); TCGv mask = tcg_temp_new(); - TCGv t0 = tcg_const_i32(0); + TCGv t0 = tcg_constant_i32(0); /* create mask for sticky bits */ tcg_gen_setcond_tl(cond, mask, r4, t0); @@ -1516,21 +1522,22 @@ static inline void gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -1542,23 +1549,24 @@ static inline void gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv temp3 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -1576,22 +1584,22 @@ static inline void gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); TCGv_i64 temp64_3 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); break; } tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); @@ -1604,21 +1612,21 @@ static inline void gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n); break; } tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); @@ -1630,20 +1638,20 @@ static inline void gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); @@ -1664,20 +1672,20 @@ static inline void gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); @@ -1697,14 +1705,14 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) static inline void gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { - TCGv temp = tcg_const_i32(n); + TCGv temp = tcg_constant_i32(n); gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); } static inline void gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { - TCGv temp = tcg_const_i32(n); + TCGv temp = tcg_constant_i32(n); gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); } @@ -1912,10 +1920,10 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, TCGv arg3, uint32_t n) { TCGv_i64 r1 = tcg_temp_new_i64(); - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); - gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); + gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); tcg_gen_extr_i64_i32(rl, rh, r1); } @@ -1923,21 +1931,22 @@ static inline void gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -1949,22 +1958,22 @@ static inline void gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); TCGv_i64 temp64_3 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); @@ -1981,21 +1990,22 @@ gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, static inline void gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_andi_tl(temp2, r1, 0xffff0000); @@ -2007,23 +2017,24 @@ static inline void gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv temp3 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_extr_i64_i32(temp, temp2, temp64); @@ -2041,22 +2052,22 @@ static inline void gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); TCGv_i64 temp64 = tcg_temp_new_i64(); TCGv_i64 temp64_2 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ @@ -2072,21 +2083,22 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, static inline void gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) { - TCGv temp = tcg_const_i32(n); + TCGv t_n = tcg_constant_i32(n); + TCGv temp = tcg_temp_new(); TCGv temp2 = tcg_temp_new(); TCGv_i64 temp64 = tcg_temp_new_i64(); switch (mode) { case MODE_LL: - GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n); break; case MODE_LU: - GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n); break; case MODE_UL: - GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n); break; case MODE_UU: - GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); + GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } tcg_gen_andi_tl(temp2, r1, 0xffff0000); @@ -2137,13 +2149,13 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_absdif(ret, r1, temp); } static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_absdif_ssov(ret, cpu_env, r1, temp); } @@ -2169,7 +2181,7 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_mul_i32s(ret, r1, temp); } @@ -2190,7 +2202,7 @@ static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_mul_i64s(ret_low, ret_high, r1, temp); } @@ -2211,31 +2223,32 @@ static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_mul_i64u(ret_low, ret_high, r1, temp); } static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_mul_ssov(ret, cpu_env, r1, temp); } static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_mul_suov(ret, cpu_env, r1, temp); } + /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); } static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); } @@ -2358,7 +2371,7 @@ static inline void gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); } @@ -2376,19 +2389,19 @@ static inline void gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); } static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); } static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); } @@ -2406,7 +2419,7 @@ static inline void gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); } @@ -2424,27 +2437,19 @@ static inline void gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); } static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) { - TCGv sat_neg = tcg_const_i32(low); - TCGv temp = tcg_const_i32(up); - - /* sat_neg = (arg < low ) ? low : arg; */ - tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); - - /* ret = (sat_neg > up ) ? up : sat_neg; */ - tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); + tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low)); + tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up)); } static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) { - TCGv temp = tcg_const_i32(up); - /* sat_neg = (arg > up ) ? up : arg; */ - tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); + tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up)); } static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) @@ -2495,8 +2500,8 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) /* clear PSW.V */ tcg_gen_movi_tl(cpu_PSW_V, 0); } else if (shift_count > 0) { - TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); - TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count); + TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count); + TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count); /* calc carry */ msk_start = 32 - shift_count; @@ -2534,7 +2539,7 @@ static void gen_shas(TCGv ret, TCGv r1, TCGv r2) static void gen_shasi(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_shas(ret, r1, temp); } @@ -2576,7 +2581,7 @@ static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_sh_cond(cond, ret, r1, temp); } @@ -2587,13 +2592,13 @@ static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_add_ssov(ret, cpu_env, r1, temp); } static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_helper_add_suov(ret, cpu_env, r1, temp); } @@ -2663,7 +2668,7 @@ static inline void gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, void(*op)(TCGv, TCGv, TCGv)) { - TCGv temp = tcg_const_i32(con); + TCGv temp = tcg_constant_i32(con); gen_accumulating_cond(cond, ret, r1, temp, op); } @@ -2830,8 +2835,8 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) static void generate_trap(DisasContext *ctx, int class, int tin) { - TCGv_i32 classtemp = tcg_const_i32(class); - TCGv_i32 tintemp = tcg_const_i32(tin); + TCGv_i32 classtemp = tcg_constant_i32(class); + TCGv_i32 tintemp = tcg_constant_i32(tin); gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); @@ -2853,7 +2858,7 @@ static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, int r2, int16_t address) { - TCGv temp = tcg_const_i32(r2); + TCGv temp = tcg_constant_i32(r2); gen_branch_cond(ctx, cond, r1, temp, address); } @@ -3182,14 +3187,14 @@ static void decode_src_opc(DisasContext *ctx, int op1) cpu_gpr_d[15]); break; case OPC1_16_SRC_CMOV: - temp = tcg_const_tl(0); - temp2 = tcg_const_tl(const4); + temp = tcg_constant_tl(0); + temp2 = tcg_constant_tl(const4); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, temp2, cpu_gpr_d[r1]); break; case OPC1_16_SRC_CMOVN: - temp = tcg_const_tl(0); - temp2 = tcg_const_tl(const4); + temp = tcg_constant_tl(0); + temp2 = tcg_constant_tl(const4); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, temp2, cpu_gpr_d[r1]); break; @@ -3255,12 +3260,12 @@ static void decode_srr_opc(DisasContext *ctx, int op1) tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC1_16_SRR_CMOV: - temp = tcg_const_tl(0); + temp = tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, cpu_gpr_d[r2], cpu_gpr_d[r1]); break; case OPC1_16_SRR_CMOVN: - temp = tcg_const_tl(0); + temp = tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, cpu_gpr_d[r2], cpu_gpr_d[r1]); break; @@ -3502,17 +3507,14 @@ static void decode_sr_accu(DisasContext *ctx) { uint32_t op2; uint32_t r1; - TCGv temp; r1 = MASK_OP_SR_S1D(ctx->opcode); op2 = MASK_OP_SR_OP2(ctx->opcode); switch (op2) { case OPC2_16_SR_RSUB: - /* overflow only if r1 = -0x80000000 */ - temp = tcg_const_i32(-0x80000000); - /* calc V bit */ - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp); + /* calc V bit -- overflow only if r1 = -0x80000000 */ + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000); tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); /* calc SV bit */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); @@ -3788,7 +3790,7 @@ static void decode_abs_ldw(DisasContext *ctx) address = MASK_OP_ABS_OFF18(ctx->opcode); op2 = MASK_OP_ABS_OP2(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); switch (op2) { case OPC2_32_ABS_LD_A: @@ -3821,7 +3823,7 @@ static void decode_abs_ldb(DisasContext *ctx) address = MASK_OP_ABS_OFF18(ctx->opcode); op2 = MASK_OP_ABS_OP2(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); switch (op2) { case OPC2_32_ABS_LD_B: @@ -3852,7 +3854,7 @@ static void decode_abs_ldst_swap(DisasContext *ctx) address = MASK_OP_ABS_OFF18(ctx->opcode); op2 = MASK_OP_ABS_OP2(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); switch (op2) { case OPC2_32_ABS_LDMST: @@ -3903,7 +3905,7 @@ static void decode_abs_store(DisasContext *ctx) address = MASK_OP_ABS_OFF18(ctx->opcode); op2 = MASK_OP_ABS_OP2(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); switch (op2) { case OPC2_32_ABS_ST_A: @@ -3936,7 +3938,7 @@ static void decode_abs_storeb_h(DisasContext *ctx) address = MASK_OP_ABS_OFF18(ctx->opcode); op2 = MASK_OP_ABS_OP2(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); switch (op2) { case OPC2_32_ABS_ST_B: @@ -4368,7 +4370,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) uint32_t op2; uint32_t off10; int32_t r1, r2; - TCGv temp, temp2, temp3; + TCGv temp, temp2, t_off10; r1 = MASK_OP_BO_S1D(ctx->opcode); r2 = MASK_OP_BO_S2(ctx->opcode); @@ -4377,7 +4379,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) temp = tcg_temp_new(); temp2 = tcg_temp_new(); - temp3 = tcg_const_i32(off10); + t_off10 = tcg_constant_i32(off10); CHECK_REG_PAIR(r2); tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); @@ -4391,7 +4393,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) case OPC2_32_BO_CACHEA_WI_CIRC: case OPC2_32_BO_CACHEA_W_CIRC: case OPC2_32_BO_CACHEA_I_CIRC: - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_A_BR: tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); @@ -4399,7 +4401,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_ST_A_CIRC: tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_B_BR: tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); @@ -4407,7 +4409,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_ST_B_CIRC: tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_D_BR: CHECK_REG_PAIR(r1); @@ -4422,7 +4424,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) tcg_gen_rem_tl(temp, temp, temp2); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_DA_BR: CHECK_REG_PAIR(r1); @@ -4437,7 +4439,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) tcg_gen_rem_tl(temp, temp, temp2); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_H_BR: tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); @@ -4445,7 +4447,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_ST_H_CIRC: tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_Q_BR: tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); @@ -4455,7 +4457,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) case OPC2_32_BO_ST_Q_CIRC: tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_ST_W_BR: tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); @@ -4463,7 +4465,7 @@ static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_ST_W_CIRC: tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -4607,8 +4609,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) uint32_t op2; uint32_t off10; int r1, r2; - - TCGv temp, temp2, temp3; + TCGv temp, temp2, t_off10; r1 = MASK_OP_BO_S1D(ctx->opcode); r2 = MASK_OP_BO_S2(ctx->opcode); @@ -4617,7 +4618,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) temp = tcg_temp_new(); temp2 = tcg_temp_new(); - temp3 = tcg_const_i32(off10); + t_off10 = tcg_constant_i32(off10); CHECK_REG_PAIR(r2); tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); @@ -4630,7 +4631,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_A_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_B_BR: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); @@ -4638,7 +4639,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_B_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_BU_BR: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); @@ -4646,7 +4647,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_BU_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_D_BR: CHECK_REG_PAIR(r1); @@ -4661,7 +4662,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) tcg_gen_rem_tl(temp, temp, temp2); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_DA_BR: CHECK_REG_PAIR(r1); @@ -4676,7 +4677,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) tcg_gen_rem_tl(temp, temp, temp2); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_H_BR: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); @@ -4684,7 +4685,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_H_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_HU_BR: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); @@ -4692,7 +4693,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_HU_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_Q_BR: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); @@ -4702,7 +4703,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) case OPC2_32_BO_LD_Q_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_LD_W_BR: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); @@ -4710,7 +4711,7 @@ static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LD_W_CIRC: tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -4811,8 +4812,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) uint32_t op2; uint32_t off10; int r1, r2; - - TCGv temp, temp2, temp3; + TCGv temp, temp2, t_off10; r1 = MASK_OP_BO_S1D(ctx->opcode); r2 = MASK_OP_BO_S2(ctx->opcode); @@ -4821,7 +4821,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) temp = tcg_temp_new(); temp2 = tcg_temp_new(); - temp3 = tcg_const_i32(off10); + t_off10 = tcg_constant_i32(off10); CHECK_REG_PAIR(r2); tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); @@ -4833,7 +4833,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_LDMST_CIRC: gen_ldmst(ctx, r1, temp2); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_SWAP_W_BR: gen_swap(ctx, r1, temp2); @@ -4841,7 +4841,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_SWAP_W_CIRC: gen_swap(ctx, r1, temp2); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_CMPSWAP_W_BR: gen_cmpswap(ctx, r1, temp2); @@ -4849,7 +4849,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_CMPSWAP_W_CIRC: gen_cmpswap(ctx, r1, temp2); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; case OPC2_32_BO_SWAPMSK_W_BR: gen_swapmsk(ctx, r1, temp2); @@ -4857,7 +4857,7 @@ static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) break; case OPC2_32_BO_SWAPMSK_W_CIRC: gen_swapmsk(ctx, r1, temp2); - gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); + gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -5296,7 +5296,7 @@ static void decode_rcpw_insert(DisasContext *ctx) case OPC2_32_RCPW_INSERT: /* if pos + width > 32 undefined result */ if (pos + width <= 32) { - temp = tcg_const_i32(const4); + temp = tcg_constant_i32(const4); tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); } break; @@ -5372,14 +5372,14 @@ static void decode_rcr_cond_select(DisasContext *ctx) cpu_gpr_d[r3]); break; case OPC2_32_RCR_SEL: - temp = tcg_const_i32(0); - temp2 = tcg_const_i32(const9); + temp = tcg_constant_i32(0); + temp2 = tcg_constant_i32(const9); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp2); break; case OPC2_32_RCR_SELN: - temp = tcg_const_i32(0); - temp2 = tcg_const_i32(const9); + temp = tcg_constant_i32(0); + temp2 = tcg_constant_i32(const9); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp2); break; @@ -6256,7 +6256,7 @@ static void decode_rr1_mul(DisasContext *ctx) r1 = MASK_OP_RR1_S1(ctx->opcode); r2 = MASK_OP_RR1_S2(ctx->opcode); r3 = MASK_OP_RR1_D(ctx->opcode); - n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode)); + n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode)); op2 = MASK_OP_RR1_OP2(ctx->opcode); switch (op2) { @@ -6550,12 +6550,12 @@ static void decode_rrr_cond_select(DisasContext *ctx) cpu_gpr_d[r3]); break; case OPC2_32_RRR_SEL: - temp = tcg_const_i32(0); + temp = tcg_constant_i32(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_SELN: - temp = tcg_const_i32(0); + temp = tcg_constant_i32(0); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; @@ -6907,7 +6907,7 @@ static void decode_rrr1_maddq_h(DisasContext *ctx) r4 = MASK_OP_RRR1_D(ctx->opcode); n = MASK_OP_RRR1_N(ctx->opcode); - temp = tcg_const_i32(n); + temp = tcg_temp_new(); temp2 = tcg_temp_new(); switch (op2) { @@ -7389,7 +7389,7 @@ static void decode_rrr1_msubq_h(DisasContext *ctx) r4 = MASK_OP_RRR1_D(ctx->opcode); n = MASK_OP_RRR1_N(ctx->opcode); - temp = tcg_const_i32(n); + temp = tcg_temp_new(); temp2 = tcg_temp_new(); switch (op2) { @@ -7957,7 +7957,7 @@ static void decode_32Bit_opc(DisasContext *ctx) case OPC1_32_ABS_STOREQ: address = MASK_OP_ABS_OFF18(ctx->opcode); r1 = MASK_OP_ABS_S1D(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); temp2 = tcg_temp_new(); tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); @@ -7966,7 +7966,7 @@ static void decode_32Bit_opc(DisasContext *ctx) case OPC1_32_ABS_LD_Q: address = MASK_OP_ABS_OFF18(ctx->opcode); r1 = MASK_OP_ABS_S1D(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); @@ -7982,7 +7982,7 @@ static void decode_32Bit_opc(DisasContext *ctx) b = MASK_OP_ABSB_B(ctx->opcode); bpos = MASK_OP_ABSB_BPOS(ctx->opcode); - temp = tcg_const_i32(EA_ABS_FORMAT(address)); + temp = tcg_constant_i32(EA_ABS_FORMAT(address)); temp2 = tcg_temp_new(); tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); @@ -8109,7 +8109,7 @@ static void decode_32Bit_opc(DisasContext *ctx) r2 = MASK_OP_RCRR_S3(ctx->opcode); r3 = MASK_OP_RCRR_D(ctx->opcode); const16 = MASK_OP_RCRR_CONST4(ctx->opcode); - temp = tcg_const_i32(const16); + temp = tcg_constant_i32(const16); temp2 = tcg_temp_new(); /* width*/ temp3 = tcg_temp_new(); /* pos */ diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c index c982d09c24..9aba2667e3 100644 --- a/target/xtensa/core-dc232b.c +++ b/target/xtensa/core-dc232b.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "qemu/timer.h" diff --git a/target/xtensa/core-dc233c.c b/target/xtensa/core-dc233c.c index 595ab9a90f..9b0a625063 100644 --- a/target/xtensa/core-dc233c.c +++ b/target/xtensa/core-dc233c.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-dc233c/core-isa.h" diff --git a/target/xtensa/core-de212.c b/target/xtensa/core-de212.c index 50c995ba79..b08fe22e65 100644 --- a/target/xtensa/core-de212.c +++ b/target/xtensa/core-de212.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-de212/core-isa.h" diff --git a/target/xtensa/core-de233_fpu.c b/target/xtensa/core-de233_fpu.c index 41af8057fb..8845cdb592 100644 --- a/target/xtensa/core-de233_fpu.c +++ b/target/xtensa/core-de233_fpu.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-de233_fpu/core-isa.h" diff --git a/target/xtensa/core-dsp3400.c b/target/xtensa/core-dsp3400.c index 81e425c568..c0f94b9e27 100644 --- a/target/xtensa/core-dsp3400.c +++ b/target/xtensa/core-dsp3400.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-dsp3400/core-isa.h" diff --git a/target/xtensa/core-fsf.c b/target/xtensa/core-fsf.c index 3327c50b4f..310be8d61f 100644 --- a/target/xtensa/core-fsf.c +++ b/target/xtensa/core-fsf.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-fsf/core-isa.h" diff --git a/target/xtensa/core-lx106.c b/target/xtensa/core-lx106.c index 7a771d09a6..7f71d088f3 100644 --- a/target/xtensa/core-lx106.c +++ b/target/xtensa/core-lx106.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-lx106/core-isa.h" diff --git a/target/xtensa/core-sample_controller.c b/target/xtensa/core-sample_controller.c index fd5de5576b..8867001aac 100644 --- a/target/xtensa/core-sample_controller.c +++ b/target/xtensa/core-sample_controller.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-sample_controller/core-isa.h" diff --git a/target/xtensa/core-test_kc705_be.c b/target/xtensa/core-test_kc705_be.c index 294c16f2f4..bd082f49aa 100644 --- a/target/xtensa/core-test_kc705_be.c +++ b/target/xtensa/core-test_kc705_be.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-test_kc705_be/core-isa.h" diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c index c0e5d32d1e..3090dd01ed 100644 --- a/target/xtensa/core-test_mmuhifi_c3.c +++ b/target/xtensa/core-test_mmuhifi_c3.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-test_mmuhifi_c3/core-isa.h" diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index b53e9a3e08..b1da0555de 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,5 @@ #else #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -#define NB_MMU_MODES 4 #endif diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index b6696063e5..4b3bfb7e59 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/log.h" enum { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2aa9777a8e..dbeb97a953 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -29,7 +29,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index b4c15556c2..17dfec8957 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -41,7 +41,7 @@ tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \ cat <<EOF > "${TARGET}.c" #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-$NAME/core-isa.h" |