diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/hexagon/macros.h | 4 | ||||
| -rw-r--r-- | target/hexagon/opcodes.c | 1 | ||||
| -rw-r--r-- | target/i386/kvm/kvm.c | 9 | ||||
| -rw-r--r-- | target/sh4/cpu.h | 11 | ||||
| -rw-r--r-- | target/sh4/helper.c | 101 |
5 files changed, 60 insertions, 66 deletions
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 78c4efb5cb..cfcb8173ba 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -459,7 +459,7 @@ static inline void gen_logical_not(TCGv dest, TCGv src) : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ - (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) + (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) #define fROTL(SRC, SHAMT, REGSTYPE) \ (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ ((fCAST##REGSTYPE##u(SRC) >> \ @@ -469,7 +469,7 @@ static inline void gen_logical_not(TCGv dest, TCGv src) ((fCAST##REGSTYPE##u(SRC) << \ ((sizeof(SRC) * 8) - (SHAMT)))))) #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ - (((SHAMT) >= 64) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) + (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) #ifdef QEMU_GENERATE #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) diff --git a/target/hexagon/opcodes.c b/target/hexagon/opcodes.c index 4eef5fc40f..35d790cdd5 100644 --- a/target/hexagon/opcodes.c +++ b/target/hexagon/opcodes.c @@ -82,6 +82,7 @@ static void init_attribs(int tag, ...) while ((attr = va_arg(ap, int)) != 0) { set_bit(attr, opcode_attribs[tag]); } + va_end(ap); } const OpcodeEncoding opcode_encodings[] = { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 0b5755e42b..c8d61daf68 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4352,8 +4352,13 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) { uint8_t int3; - if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { + if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) { + return -EINVAL; + } + if (int3 != 0xcc) { + return 0; + } + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { return -EINVAL; } return 0; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 714e3b5641..01c4344082 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -271,17 +271,6 @@ typedef SuperHCPU ArchCPU; #include "exec/cpu-all.h" -/* Memory access type */ -enum { - /* Privilege */ - ACCESS_PRIV = 0x01, - /* Direction */ - ACCESS_WRITE = 0x02, - /* Type of instruction */ - ACCESS_CODE = 0x10, - ACCESS_INT = 0x20 -}; - /* MMU control register */ #define MMUCR 0x1F000010 #define MMUCR_AT (1<<0) diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 408478ce5d..bd8e034f17 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -330,22 +330,22 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE. */ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, - int *prot, target_ulong address, - int rw, int access_type) + int *prot, target_ulong address, + MMUAccessType access_type) { int use_asid, n; tlb_t *matching = NULL; use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); - if (rw == 2) { + if (access_type == MMU_INST_FETCH) { n = find_itlb_entry(env, address, use_asid); - if (n >= 0) { - matching = &env->itlb[n]; + if (n >= 0) { + matching = &env->itlb[n]; if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { - n = MMU_ITLB_VIOLATION; + n = MMU_ITLB_VIOLATION; } else { - *prot = PAGE_EXEC; + *prot = PAGE_EXEC; } } else { n = find_utlb_entry(env, address, use_asid); @@ -365,17 +365,17 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, } else if (n == MMU_DTLB_MISS) { n = MMU_ITLB_MISS; } - } + } } else { - n = find_utlb_entry(env, address, use_asid); - if (n >= 0) { - matching = &env->utlb[n]; + n = find_utlb_entry(env, address, use_asid); + if (n >= 0) { + matching = &env->utlb[n]; if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { - n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE : - MMU_DTLB_VIOLATION_READ; - } else if ((rw == 1) && !(matching->pr & 1)) { + n = (access_type == MMU_DATA_STORE) + ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ; + } else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) { n = MMU_DTLB_VIOLATION_WRITE; - } else if ((rw == 1) && !matching->d) { + } else if ((access_type == MMU_DATA_STORE) && !matching->d) { n = MMU_DTLB_INITIAL_WRITE; } else { *prot = PAGE_READ; @@ -383,56 +383,56 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, *prot |= PAGE_WRITE; } } - } else if (n == MMU_DTLB_MISS) { - n = (rw == 1) ? MMU_DTLB_MISS_WRITE : - MMU_DTLB_MISS_READ; - } + } else if (n == MMU_DTLB_MISS) { + n = (access_type == MMU_DATA_STORE) + ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ; + } } if (n >= 0) { - n = MMU_OK; - *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | - (address & (matching->size - 1)); + n = MMU_OK; + *physical = ((matching->ppn << 10) & ~(matching->size - 1)) + | (address & (matching->size - 1)); } return n; } static int get_physical_address(CPUSH4State * env, target_ulong * physical, int *prot, target_ulong address, - int rw, int access_type) + MMUAccessType access_type) { /* P1, P2 and P4 areas do not use translation */ - if ((address >= 0x80000000 && address < 0xc0000000) || - address >= 0xe0000000) { + if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) { if (!(env->sr & (1u << SR_MD)) - && (address < 0xe0000000 || address >= 0xe4000000)) { - /* Unauthorized access in user mode (only store queues are available) */ + && (address < 0xe0000000 || address >= 0xe4000000)) { + /* Unauthorized access in user mode (only store queues are available) */ qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n"); - if (rw == 0) - return MMU_DADDR_ERROR_READ; - else if (rw == 1) - return MMU_DADDR_ERROR_WRITE; - else - return MMU_IADDR_ERROR; - } - if (address >= 0x80000000 && address < 0xc0000000) { - /* Mask upper 3 bits for P1 and P2 areas */ - *physical = address & 0x1fffffff; - } else { - *physical = address; - } - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return MMU_OK; + if (access_type == MMU_DATA_LOAD) { + return MMU_DADDR_ERROR_READ; + } else if (access_type == MMU_DATA_STORE) { + return MMU_DADDR_ERROR_WRITE; + } else { + return MMU_IADDR_ERROR; + } + } + if (address >= 0x80000000 && address < 0xc0000000) { + /* Mask upper 3 bits for P1 and P2 areas */ + *physical = address & 0x1fffffff; + } else { + *physical = address; + } + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return MMU_OK; } /* If MMU is disabled, return the corresponding physical page */ if (!(env->mmucr & MMUCR_AT)) { - *physical = address & 0x1FFFFFFF; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return MMU_OK; + *physical = address & 0x1FFFFFFF; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return MMU_OK; } /* We need to resort to the MMU */ - return get_mmu_address(env, physical, prot, address, rw, access_type); + return get_mmu_address(env, physical, prot, address, access_type); } hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -441,7 +441,8 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) target_ulong physical; int prot; - get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0); + get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_LOAD); + return physical; } @@ -813,11 +814,9 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMU_DTLB_VIOLATION_READ); #else target_ulong physical; - int prot, sh_access_type; + int prot; - sh_access_type = ACCESS_INT; - ret = get_physical_address(env, &physical, &prot, address, - access_type, sh_access_type); + ret = get_physical_address(env, &physical, &prot, address, access_type); if (ret == MMU_OK) { address &= TARGET_PAGE_MASK; |