diff options
Diffstat (limited to 'target')
48 files changed, 94 insertions, 53 deletions
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8ed29e343..de705c3703 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -203,7 +203,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps alpha_tcg_ops = { +static const TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, .restore_state_to_opc = alpha_restore_state_to_opc, diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..134eb7225b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b60e103046..6a96b245f2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2458,7 +2458,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #endif #ifdef CONFIG_TCG -static const struct TCGCPUOps arm_tcg_ops = { +static const TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..1125305115 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -1018,7 +1018,7 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } -static const struct TCGCPUOps arm_v7m_tcg_ops = { +static const TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b3660173d1..5fa8249723 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9691,7 +9691,7 @@ static const TranslatorOps thumb_translator_ops = { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = { }; const TranslatorOps *ops = &arm_translator_ops; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..1c68748b24 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -210,7 +210,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps avr_tcg_ops = { +static const TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .restore_state_to_opc = avr_restore_state_to_opc, diff --git a/target/avr/translate.c b/target/avr/translate.c index cdffa04519..e5dd057799 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = { }; translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..6349148b65 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -178,7 +178,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps crisv10_tcg_ops = { +static const TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, .restore_state_to_opc = cris_restore_state_to_opc, @@ -189,7 +189,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; -static const struct TCGCPUOps crisv32_tcg_ops = { +static const TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, .restore_state_to_opc = cris_restore_state_to_opc, diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..ee1402a9a3 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c0cd739e15..759ea62814 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -337,7 +337,7 @@ static void hexagon_cpu_init(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps hexagon_tcg_ops = { +static const TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 95579ae243..f163eefe97 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, g_assert(ctx->base.num_insns == 1); } - HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); + HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n", + ctx->base.pc_next); HEX_DEBUG_LOG(" words = { "); for (int i = 0; i < nwords; i++) { HEX_DEBUG_LOG("0x%x, ", words[i]); @@ -1154,7 +1155,7 @@ static const TranslatorOps hexagon_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 14e17fa9aa..3c019855b4 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -170,7 +170,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps hppa_tcg_ops = { +static const TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..08d09d50d7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4631,7 +4631,7 @@ static const TranslatorOps hppa_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index ce34b737bb..effc2c1c98 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -39,6 +39,8 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); */ void x86_cpu_do_interrupt(CPUState *cpu); #ifndef CONFIG_USER_ONLY +void x86_cpu_exec_halt(CPUState *cpu); +bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c index 1cb5a0db45..2db8083748 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" @@ -127,6 +128,28 @@ void x86_cpu_do_interrupt(CPUState *cs) } } +void x86_cpu_exec_halt(CPUState *cpu) +{ + if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + X86CPU *x86_cpu = X86_CPU(cpu); + + bql_lock(); + apic_poll_irq(x86_cpu->apic_state); + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); + bql_unlock(); + } +} + +bool x86_need_replay_interrupt(int interrupt_request) +{ + /* + * CPU_INTERRUPT_POLL is a virtual event which gets converted into a + * "real" interrupt event later. It does not need to be recorded for + * replay purposes. + */ + return !(interrupt_request & CPU_INTERRUPT_POLL); +} + bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e1405b7be9..cca19cd40e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps x86_tcg_ops = { +static const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, @@ -119,10 +119,12 @@ static const struct TCGCPUOps x86_tcg_ops = { #else .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, + .cpu_exec_halt = x86_cpu_exec_halt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .do_unaligned_access = x86_cpu_do_unaligned_access, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, + .need_replay_interrupt = x86_need_replay_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e193c74472..2808903661 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7088,7 +7088,7 @@ static const TranslatorOps i386_tr_ops = { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 064540397d..fb8dde7def 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -734,7 +734,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps loongarch_tcg_ops = { +static const TCGCPUOps loongarch_tcg_ops = { .initialize = loongarch_translate_init, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 21f4db6fbd..235515c629 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -343,7 +343,7 @@ static const TranslatorOps loongarch_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1421e77c2c..44000f5869 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -525,7 +525,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps m68k_tcg_ops = { +static const TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, .restore_state_to_opc = m68k_restore_state_to_opc, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..f886190f88 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1457,7 +1457,7 @@ DISAS_INSN(undef) * for the 680x0 series, as well as those that are implemented * but actually illegal for CPU32 or pre-68020. */ - qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n", + qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\n", insn, s->base.pc_next); gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); } @@ -6088,7 +6088,7 @@ static const TranslatorOps m68k_tr_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base); diff --git a/target/meson.build b/target/meson.build index a53a60486f..dee2ac47e0 100644 --- a/target/meson.build +++ b/target/meson.build @@ -19,3 +19,5 @@ subdir('sh4') subdir('sparc') subdir('tricore') subdir('xtensa') + +specific_ss.add(files('target-common.c')) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..2318ad7013 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -387,7 +387,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps mb_tcg_ops = { +static const TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..2e628647d1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1792,7 +1792,7 @@ static const TranslatorOps mb_tr_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..df544ab39b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,7 +549,7 @@ static const struct SysemuCPUOps mips_sysemu_ops = { * NB: cannot be const, as some elements are changed for specific * mips hardware (see hw/mips/jazz.c). */ -static const struct TCGCPUOps mips_tcg_ops = { +static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 13e43fa3b6..12094cc1e7 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" - TARGET_FMT_lx "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); goto out; @@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; @@ -11274,8 +11274,8 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; @@ -15554,7 +15554,7 @@ static const TranslatorOps mips_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index cffcfeab8c..93a78b8121 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -202,7 +202,8 @@ extern TCGv bcond; do { \ if (MIPS_DEBUG_DISAS) { \ qemu_log_mask(CPU_LOG_TB_IN_ASM, \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ + "%016" VADDR_PRIx \ + ": %08x Invalid %s %03x %03x %03x\n", \ ctx->base.pc_next, ctx->opcode, op, \ ctx->opcode >> 26, ctx->opcode & 0x3F, \ ((ctx->opcode >> 16) & 0x1F)); \ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a27732bf2b..596c0c5617 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -354,7 +354,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps nios2_tcg_ops = { +static const TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, .restore_state_to_opc = nios2_restore_state_to_opc, diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..3078372b36 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -1036,7 +1036,7 @@ static const TranslatorOps nios2_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.base); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 381ebe00d3..477d49d4bc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -213,7 +213,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps openrisc_tcg_ops = { +static const TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..d4cbc5eaea 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1658,7 +1658,7 @@ static const TranslatorOps openrisc_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..23eb5522b6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7332,7 +7332,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps ppc_tcg_ops = { +static const TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, .restore_state_to_opc = ppc_restore_state_to_opc, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 329da4d518..049f636927 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7518,7 +7518,7 @@ static const TranslatorOps ppc_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..b7da92783b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -129,7 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->bins = data[1]; } -static const struct TCGCPUOps riscv_tcg_ops = { +static const TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef..ab18899122 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1287,7 +1287,7 @@ static const TranslatorOps riscv_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c5ffeffe32..353132dac2 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -178,7 +178,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps rx_tcg_ops = { +static const TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, diff --git a/target/rx/translate.c b/target/rx/translate.c index c6ce717a95..2265bd14ac 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2266,7 +2266,7 @@ static const TranslatorOps rx_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6acfa1c91b..7f123863dc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -319,7 +319,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps s390_tcg_ops = { +static const TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, .restore_state_to_opc = s390x_restore_state_to_opc, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8df00b7df9..a5fd9cccaa 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6547,7 +6547,7 @@ static const TranslatorOps s390x_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 806a0ef875..39772955b5 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -237,7 +237,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps superh_tcg_ops = { +static const TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 81f825f125..6a6d862b10 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2317,7 +2317,7 @@ static const TranslatorOps sh4_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..7d0d629a3d 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -874,7 +874,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps sparc_tcg_ops = { +static const TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..97184fa403 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5327,7 +5327,7 @@ static const TranslatorOps sparc_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = {}; diff --git a/target/target-common.c b/target/target-common.c new file mode 100644 index 0000000000..903b10cfe4 --- /dev/null +++ b/target/target-common.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/target_page.h" + +int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8acacdf0c0..e6d91c74b5 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -173,7 +173,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps tricore_tcg_ops = { +static const TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 66553d1be0..f1156c39e7 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8472,7 +8472,7 @@ static const TranslatorOps tricore_tr_ops = { void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c0ca130f..62020b1f33 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -222,7 +222,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps xtensa_tcg_ops = { +static const TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, .debug_excp_handler = xtensa_breakpoint_handler, .restore_state_to_opc = xtensa_restore_state_to_opc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 87947236ca..e4772462b5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1239,7 +1239,7 @@ static const TranslatorOps xtensa_translator_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = {}; translator_loop(cpu, tb, max_insns, pc, host_pc, |