diff options
Diffstat (limited to 'tcg/s390')
| -rw-r--r-- | tcg/s390/tcg-target-con-set.h | 29 | ||||
| -rw-r--r-- | tcg/s390/tcg-target-con-str.h | 28 | ||||
| -rw-r--r-- | tcg/s390/tcg-target.c.inc | 174 |
3 files changed, 121 insertions, 110 deletions
diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390/tcg-target-con-set.h new file mode 100644 index 0000000000..31985e4903 --- /dev/null +++ b/tcg/s390/tcg-target-con-set.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define S390 target-specific constraint sets. + * Copyright (c) 2021 Linaro + */ + +/* + * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs. + * Each operand should be a sequence of constraint letters as defined by + * tcg-target-con-str.h; the constraint combination is inclusive or. + */ +C_O0_I1(r) +C_O0_I2(L, L) +C_O0_I2(r, r) +C_O0_I2(r, ri) +C_O1_I1(r, L) +C_O1_I1(r, r) +C_O1_I2(r, 0, ri) +C_O1_I2(r, 0, rI) +C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, ri) +C_O1_I2(r, rZ, r) +C_O1_I4(r, r, ri, r, 0) +C_O1_I4(r, r, ri, rI, 0) +C_O2_I2(b, a, 0, r) +C_O2_I3(b, a, 0, 1, r) +C_O2_I4(r, r, 0, 1, rA, r) +C_O2_I4(r, r, 0, 1, ri, r) +C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390/tcg-target-con-str.h new file mode 100644 index 0000000000..892d8f8c06 --- /dev/null +++ b/tcg/s390/tcg-target-con-str.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define S390 target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +/* + * A (single) even/odd pair for division. + * TODO: Add something to the register allocator to allow + * this kind of regno+1 pairing to be done more generally. + */ +REGS('a', 1u << TCG_REG_R2) +REGS('b', 1u << TCG_REG_R3) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('A', TCG_CT_CONST_S33) +CONST('I', TCG_CT_CONST_S16) +CONST('J', TCG_CT_CONST_S32) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 8517e55232..b67470137c 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -42,6 +42,19 @@ #define TCG_CT_CONST_S33 0x400 #define TCG_CT_CONST_ZERO 0x800 +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) +/* + * For softmmu, we need to avoid conflicts with the first 3 + * argument registers to perform the tlb lookup, and to call + * the helper function. + */ +#ifdef CONFIG_SOFTMMU +#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) +#else +#define SOFTMMU_RESERVE_REGS 0 +#endif + + /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -403,46 +416,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type, return false; } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': /* all registers */ - ct->regs = 0xffff; - break; - case 'L': /* qemu_ld/st constraint */ - ct->regs = 0xffff; - tcg_regset_reset_reg(ct->regs, TCG_REG_R2); - tcg_regset_reset_reg(ct->regs, TCG_REG_R3); - tcg_regset_reset_reg(ct->regs, TCG_REG_R4); - break; - case 'a': /* force R2 for division */ - ct->regs = 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R2); - break; - case 'b': /* force R3 for division */ - ct->regs = 0; - tcg_regset_set_reg(ct->regs, TCG_REG_R3); - break; - case 'A': - ct->ct |= TCG_CT_CONST_S33; - break; - case 'I': - ct->ct |= TCG_CT_CONST_S16; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S32; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -2301,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { - static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; - static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; - static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; - static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; - static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; - static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; - static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef a2_r - = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; - static const TCGTargetOpDef a2_ri - = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; - static const TCGTargetOpDef a2_rA - = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; - switch (op) { case INDEX_op_goto_ptr: - return &r; + return C_O0_I1(r); case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: @@ -2335,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: + return C_O1_I1(r, r); + case INDEX_op_st8_i32: case INDEX_op_st8_i64: case INDEX_op_st16_i32: @@ -2342,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - return &r_r; + return C_O0_I2(r, r); case INDEX_op_add_i32: case INDEX_op_add_i64: - return &r_r_ri; + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, ri); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: @@ -2355,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, ri) + : C_O1_I2(r, 0, rI)); + case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); + return (s390_facilities & FACILITY_GEN_INST_EXT + ? C_O1_I2(r, 0, rJ) + : C_O1_I2(r, 0, rI)); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); - - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - return &r_r_ri; - - case INDEX_op_rotl_i32: - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i32: - case INDEX_op_rotr_i64: - return &r_r_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)); case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return &r_ri; + return C_O0_I2(r, ri); case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2406,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: - return &r_r; - - case INDEX_op_clz_i64: - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return &r_r_ri; + return C_O1_I1(r, r); case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return &r_L; + return C_O1_I1(r, L); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return &L_L; + return C_O0_I2(L, L); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: - { - static const TCGTargetOpDef dep - = { .args_ct_str = { "r", "rZ", "r" } }; - return &dep; - } + return C_O1_I2(r, rZ, r); + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - { - static const TCGTargetOpDef movc - = { .args_ct_str = { "r", "r", "ri", "r", "0" } }; - static const TCGTargetOpDef movc_l - = { .args_ct_str = { "r", "r", "ri", "rI", "0" } }; - return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc); - } + return (s390_facilities & FACILITY_LOAD_ON_COND2 + ? C_O1_I4(r, r, ri, rI, 0) + : C_O1_I4(r, r, ri, r, 0)); + case INDEX_op_div2_i32: case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - { - static const TCGTargetOpDef div2 - = { .args_ct_str = { "b", "a", "0", "1", "r" } }; - return &div2; - } + return C_O2_I3(b, a, 0, 1, r); + case INDEX_op_mulu2_i64: - { - static const TCGTargetOpDef mul2 - = { .args_ct_str = { "b", "a", "0", "r" } }; - return &mul2; - } + return C_O2_I2(b, a, 0, r); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, ri, r) + : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + return (s390_facilities & FACILITY_EXT_IMM + ? C_O2_I4(r, r, 0, 1, rA, r) + : C_O2_I4(r, r, 0, 1, r, r)); default: - break; + g_assert_not_reached(); } - return NULL; } static void query_s390_facilities(void) |