diff options
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/arm/tcg-target.c | 14 | ||||
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 11 | ||||
| -rw-r--r-- | tcg/s390/tcg-target.c | 95 |
3 files changed, 19 insertions, 101 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index e93a4a237b..82658a170c 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -22,6 +22,7 @@ * THE SOFTWARE. */ +#include "elf.h" #include "tcg-be-ldst.h" /* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */ @@ -58,9 +59,6 @@ static int arm_arch = __ARM_ARCH; #ifndef use_idiv_instructions bool use_idiv_instructions; #endif -#ifdef CONFIG_GETAUXVAL -# include <sys/auxv.h> -#endif #ifndef NDEBUG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { @@ -2036,22 +2034,20 @@ static const TCGTargetOpDef arm_op_defs[] = { static void tcg_target_init(TCGContext *s) { -#if defined(CONFIG_GETAUXVAL) /* Only probe for the platform and capabilities if we havn't already determined maximum values at compile time. */ -# if !defined(use_idiv_instructions) +#ifndef use_idiv_instructions { - unsigned long hwcap = getauxval(AT_HWCAP); + unsigned long hwcap = qemu_getauxval(AT_HWCAP); use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; } -# endif +#endif if (__ARM_ARCH < 7) { - const char *pl = (const char *)getauxval(AT_PLATFORM); + const char *pl = (const char *)qemu_getauxval(AT_PLATFORM); if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { arm_arch = pl[1] - '0'; } } -#endif /* GETAUXVAL */ tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 6109d862db..06e440f9bc 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -45,15 +45,10 @@ static uint8_t *tb_ret_addr; #define GUEST_BASE 0 #endif -#ifdef CONFIG_GETAUXVAL -#include <sys/auxv.h> +#include "elf.h" static bool have_isa_2_06; #define HAVE_ISA_2_06 have_isa_2_06 #define HAVE_ISEL have_isa_2_06 -#else -#define HAVE_ISA_2_06 0 -#define HAVE_ISEL 0 -#endif #ifdef CONFIG_USE_GUEST_BASE #define TCG_GUEST_BASE_REG 30 @@ -2132,12 +2127,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { static void tcg_target_init(TCGContext *s) { -#ifdef CONFIG_GETAUXVAL - unsigned long hwcap = getauxval(AT_HWCAP); + unsigned long hwcap = qemu_getauxval(AT_HWCAP); if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa_2_06 = true; } -#endif tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 0a4f3be0e9..248726e82f 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -31,6 +31,8 @@ #error "unsupported code generation mode" #endif +#include "elf.h" + /* ??? The translation blocks produced by TCG are generally small enough to be entirely reachable with a 16-bit displacement. Leaving the option for a 32-bit displacement here Just In Case. */ @@ -2233,91 +2235,18 @@ static void sigill_handler(int sig) static void query_facilities(void) { - struct sigaction sa_old, sa_new; - register int r0 __asm__("0"); - register void *r1 __asm__("1"); - int fail; - - memset(&sa_new, 0, sizeof(sa_new)); - sa_new.sa_handler = sigill_handler; - sigaction(SIGILL, &sa_new, &sa_old); - - /* First, try STORE FACILITY LIST EXTENDED. If this is present, then - we need not do any more probing. Unfortunately, this itself is an - extension and the original STORE FACILITY LIST instruction is - kernel-only, storing its results at absolute address 200. */ - /* stfle 0(%r1) */ - r1 = &facilities; - asm volatile(".word 0xb2b0,0x1000" - : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); - - if (got_sigill) { - /* STORE FACILITY EXTENDED is not available. Probe for one of each - kind of instruction that we're interested in. */ - /* ??? Possibly some of these are in practice never present unless - the store-facility-extended facility is also present. But since - that isn't documented it's just better to probe for each. */ - - /* Test for z/Architecture. Required even in 31-bit mode. */ - got_sigill = 0; - /* agr %r0,%r0 */ - asm volatile(".word 0xb908,0x0000" : "=r"(r0) : : "cc"); - if (!got_sigill) { - facilities |= FACILITY_ZARCH_ACTIVE; - } - - /* Test for long displacement. */ - got_sigill = 0; - /* ly %r0,0(%r1) */ - r1 = &facilities; - asm volatile(".word 0xe300,0x1000,0x0058" - : "=r"(r0) : "r"(r1) : "cc"); - if (!got_sigill) { - facilities |= FACILITY_LONG_DISP; - } - - /* Test for extended immediates. */ - got_sigill = 0; - /* afi %r0,0 */ - asm volatile(".word 0xc209,0x0000,0x0000" : : : "cc"); - if (!got_sigill) { - facilities |= FACILITY_EXT_IMM; - } - - /* Test for general-instructions-extension. */ - got_sigill = 0; - /* msfi %r0,1 */ - asm volatile(".word 0xc201,0x0000,0x0001"); - if (!got_sigill) { - facilities |= FACILITY_GEN_INST_EXT; - } - } - - sigaction(SIGILL, &sa_old, NULL); + unsigned long hwcap = qemu_getauxval(AT_HWCAP); - /* The translator currently uses these extensions unconditionally. - Pruning this back to the base ESA/390 architecture doesn't seem - worthwhile, since even the KVM target requires z/Arch. */ - fail = 0; - if ((facilities & FACILITY_ZARCH_ACTIVE) == 0) { - fprintf(stderr, "TCG: z/Arch facility is required.\n"); - fprintf(stderr, "TCG: Boot with a 64-bit enabled kernel.\n"); - fail = 1; - } - if ((facilities & FACILITY_LONG_DISP) == 0) { - fprintf(stderr, "TCG: long-displacement facility is required.\n"); - fail = 1; - } + /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this + is present on all 64-bit systems, but let's check for it anyway. */ + if (hwcap & HWCAP_S390_STFLE) { + register int r0 __asm__("0"); + register void *r1 __asm__("1"); - /* So far there's just enough support for 31-bit mode to let the - compile succeed. This is good enough to run QEMU with KVM. */ - if (sizeof(void *) != 8) { - fprintf(stderr, "TCG: 31-bit mode is not supported.\n"); - fail = 1; - } - - if (fail) { - exit(-1); + /* stfle 0(%r1) */ + r1 = &facilities; + asm volatile(".word 0xb2b0,0x1000" + : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); } } |